Tag Archives: letter-wafer-top

By Jay Chittooran

U.S. Government Imposes Tariffs on $200 Billion of Goods and China Retaliates on $60 Billion of Goods

Earlier this week, the U.S. Trade Representative (USTR) released a 10 percent tariff on $200 billion in imports from China, including more than 90 tariff lines central to the semiconductor industry.

The 10 percent tariff will take effect on September 24, 2018, and rise to 25 percent on January 1. These tariff lines will cost SEMI’s 400 U.S. members tens of millions of dollars annually in additional duties. However, counting the products included in the previous rounds of tariffs, the total estimated impact exceeds $700 million annually. China has already announced that it will respond with tariffs on $60 billion worth of U.S. goods. In his notice, President Trump said the U.S. will impose tariffs on $267 billion worth of goods if China retaliates.

The U.S. government removed 279 total tariff lines, including three lines that impact our industry: silicon carbide, tungsten, and network hubs used in the manufacturing process.

As we’ve noted, intellectual property is critical to the semiconductor industry, and SEMI strongly supports efforts to better protect valuable IP. However, we believe that these tariffs will ultimately do nothing to address the concerns with China’s trade practices. This sledgehammer approach will introduce significant uncertainty, impose greater costs, and potentially lead to a trade war. This undue harm will ultimately undercut our companies’ ability to sell overseas, which will only stifle innovation and curb U.S. technological leadership.

Product Exclusion Process – List 2

USTR formally published the details for the product exclusion process for products subject to the List 2 China 301 tariffs (the $16 billion tariff list). If your company’s products are subject to tariffs, you can request an exclusion.

In evaluating product exclusion requests, the USTR will consider whether a product is available from a source outside of China, whether the additional duties would cause severe economic harm to the requestor or other U.S. interests, and whether the product is strategically important or related to Chinese industrial programs (such as “Made in China 2025”)

The request period ends on December 18, 2018, and approved exclusions will be effective for one year, applying retroactively to August 23, 2018. Because exclusions will be made on a product basis, a particular exclusion will apply to all imports of the product, regardless of whether the importer filed a request.

More information, including the process for submitting the product exclusion request and details what information should be included in your submission can be found here.

Please let me know if your company plans on filing an exclusion. SEMI has prepared a document that includes guidelines for your exclusion filing, an explainer on how to submit, and links to official government info. SEMI is glad to assist your companies file exclusion requests for your products.

SEMI will continue tracking ongoing trade developments. Any SEMI members with questions should contact Jay Chittooran, Public Policy Manager at SEMI, at [email protected].

By Christian G. Dieseldorff and Eugenia Liu

SEMI FabView update for calendar year Q3 2018

Global fab construction investment shows continuing strength, with 19 new fab projects expected to begin construction in 2019 and 2020, based on the latest data published in SEMI’s World Fab Forecast.

Fab investment is just one indicator of how growing demand in areas such as high-performance computing, data storage, artificial intelligence (AI), cloud computing, and automotive are driving the fourth consecutive year of spending growth in the semiconductor industry. Below are a few highlights* from September’s SEMI FabView:

Memory: Not fading

  • Micron plans to invest $3 billion by 2030 in Manassas, Virginia – These investments, driven by strong demand for automotive applications, are contemplated in Micron’s long-term model. The production ramp is anticipated to be in the first half of 2020.
  • SK Hynix to build new DRAM fab in Icheon (Gyeonggi Province), Korea – The construction, to be completed by the end of 2020, will adopt 1znm node (probably EUV). Total investment is estimated to exceed $13 billion.
  • Nanya Technology doubles 2018 capex plan – The increase is for additional DRAM capacity and more 20nm DRAM conversion (from 30nm).

200mm and below: Not leading edge, but continues to draw investment

  • Vanguard changes fab investment strategy – Vanguard will focus on 200 mm and has scrapped its plan for 300mm expansion.
  • Murata to invest into 150mm expansion – Murata announced a 5 billion Yen investment (US$44.6 million) in a new fab extension in Vantaa, Finland.

Investment, M&A in Analog, Logic, Power and Opto Segments

  • Texas Instruments is looking to invest $3.2 billion in new fab construction in 2019 – Texas Instruments is eyeing Richardson, Texas and also considering sites outside Texas.
  • Bosch 300mm fab in Dresden, Germany – Bosch held a groundbreaking ceremony on April 24. Equipment installation is expected in 2H19.
  • Microchip completes acquisition of Microsemi – Microchip closed its $8.45 billion acquisition of Microsemi on May 29. Microsemi has five fabs in the U.S. with a wide range of semiconductor products and system solutions.

New fabs in China keep on coming

  • Shanghai Jita Semiconductor/Huada Semiconductor – Shanghai Jita Semiconductor, a subsidiary of Huada Semiconductor and China Electronics Corporation (CEC), announced plans earlier this month to build both 200 mm and 300 mm semiconductor fabs for analog and power semiconductors in Shanghai. The combined fab investment will total $5.18 billion.
  • Hamamatsu Photonics building 200 mm fab – Hamamatsu announced that it is building a new facility Investment of 2.8 billion Yen (US$25 million) to boost opto semiconductor capacity. Production is anticipated to start in late 2019.

*Actual FabView updates provide more detail

SEMI FabView, a mobile-friendly, interactive version of SEMI’s popular World Fab Forecast, delivers on-demand fab information such as fab spending and capacity for over 1,200 facilities, including over 60 planned facilities worldwide, across a wide range of product segments including Power, GPU, Memory, Foundry, MEMS and Sensors fabs. Fab data include region, start of construction, operation, construction and equipment spending, capacity, wafer sizes, product types and geometries. SEMI FabView subscribers receive forecast model updates through SEMI’s World Fab Database.  Click here for a trial if you want to experience SEMI FabView first hand.

Christian G. Dieseldorff is senior principal analyst and Eugenia Liu is senior product marketing manager, Industry Research and Statistics, SEMI, Milpitas, California. 

Originally published on the SEMI blog.

Toshiba Memory Corporation and Western Digital Corporation (NASDAQ:WDC) yesterday celebrated the opening of a new semiconductor fabrication facility, Fab 6, and the Memory R&D Center, at Yokkaichi operations in Mie Prefecture, Japan.

Fab 6 and Memory R&D Center, Yokkaichi Operations (Photo: Business Wire)

Toshiba Memory started construction of Fab 6, a dedicated 3D flash memory fabrication facility, in February 2017. Toshiba Memory and Western Digital have installed cutting-edge manufacturing equipment for key production processes including deposition and etching. Mass production of 96-layer 3D flash memory utilizing the new fab began earlier this month.

Demand for 3D flash memory is growing for enterprise servers, data centers and smartphones, and is expected to continue to expand in the years ahead. Further investments to expand its production will be made in line with market trends.

The Memory R&D Center, located adjacent to Fab 6, began operations in March of this year, and will explore and promote advances in the development of 3D flash memory.

Toshiba Memory and Western Digital will continue to cultivate and extend their leadership in the memory business by actively developing initiatives aimed at strengthening competitiveness, advancing joint development of 3D flash memory, and making capital investments according to market trends.

Dr. Yasuo Naruke, President and CEO of Toshiba Memory said, “We are excited about opportunities to expand the market for our latest generation of 3D flash memory. Fab 6 and Memory R&D Center enable us to maintain our position as a leading player in the 3D flash memory market. We are confident that our joint venture with Western Digital will allow us to continue producing leading edge memories at Yokkaichi.”

“We are pleased to be opening Fab 6 and the Memory R&D Center with our valued partner Toshiba Memory. For nearly two decades, the successful collaboration between our companies has fostered growth and innovation of NAND flash technology,” said Steve Milligan, Chief Executive Officer, Western Digital. “We are ramping production of 96-layer 3D NAND to address the full range of end market opportunities from consumer and mobile applications to cloud data centers. Fab 6 is a cutting-edge facility that will enable us to further our technology and cost leadership position in the industry.”

By Anand Chamarthy

Materials innovation has always been vital to the semiconductor industry. In the past, it was high-κ gate dielectrics. Today, Cobalt is seen as a replacement for Tungsten in middle-of-line (MOL) contacts.

What materials innovation will the future bring?

A likely answer is Graphene, the wonder material discovered in 2004.

Graphene is one atomic layer of carbon, the thinnest and strongest material that has ever existed. It is 200 times stronger than steel and the lightest material known to man (1 square meter weighing around 0.77 mg). It is an excellent electrical and thermal conductor at room temperature with an electron mobility of ~ 200,000

cm2.V-1.s-1. At one atomic layer, graphene is flexible and transparent. Other notable properties of Graphene are its uniform absorption of light across the visible and near infrared spectrum and its applicability towards spintronics-based devices.

Graphene and Moore’s Law

Moore’s Law scaling can be broken down into 4 key areas:

  • Lithography
  • FET
  • Advanced Packaging (2.5D and 3D IC)
  • Interconnect Material

Solutions for upcoming nodes are starting to emerge in the first two areas (EUV and Nanowire- or Nanosheet-based FET respectively). Graphene play an important role in the latter two areas. For advanced packaging, Graphene can be used as a heat spreader (to lower overall thermal resistance), or as an EM shield (to lower crosstalk) as part of a 3D IC package.

Active Graphene device layers can potentially be stacked on top of each other using a low-temperature transfer process (< 400°C) to allow for a dense heterogeneous “memory near compute” configuration. This is an area DARPA is actively researching as part of its new $1.5 billion Electronics Resurgence Initiative.

Regarding interconnects, Copper interconnects are running out of steam and becoming a major IC bottleneck (projected 40% total delay for 7 nm node). Graphene’s high electron mobility and thermal conductivity make it an attractive interconnect material for MOL and back-end-of-line (BEOL), especially at line widths < 30 nm.

Graphene Device Applications

Graphene-based semiconductor applications are already starting to hit the market. A fully integrated optical transceiver (with a Graphene modulator and photodetector) operating at 25 Gb/s/channel was on display at the recent Mobile World Congress in Barcelona. San Diego-based Nanomedical Diagnostics is selling a medical device that uses a Graphene biosensor. Europe-based Emberion is building Graphene optoelectronic sensors that might find a home in LIDAR applications, where there is currently a focus on improving sensing in low-light conditions.

What will the overall Graphene roadmap in the semiconductor industry look like? The history of ion implantation serves as a good example of how a fundamental scientific discovery moves from the lab to the foundry floor.

The dominant view in the semiconductor industry at the time was that ion implantation would not work in practice (vs. thermal diffusion) and that, if it did, it would only marginally improve the manufacturing yields of existing products. There was nothing obvious about the transfer of ion bombardment techniques from nuclear physics research to semiconductor production.

Varian (led by British physicist Peter Rose) built a new, advanced ion implant tool that Mostek (DRAM manufacturer based in Texas) was able to use to create MOS ICs with clear competitive advantages. The successful collaboration between Varian and Mostek was the turning point in the development of ion implantation as a major semiconductor manufacturing process. Over the next few years, semiconductor firms used ion implantation in a growing number of process steps and, by the late 1970s, it became one of the main processes used in semiconductor manufacturing.

Likewise, the Graphene world needs to work closely with the semiconductor industry to develop the tools and techniques required to solve fundamental issues around Graphene growth (good uniformity over large area, low defect density) and Graphene transfer (high throughput, CMOS compatible). It is only then will we fully realize a future that includes 2D materials.

The first step in this process is cross-industry education and initiating the dialogue between semiconductor industry and graphene companies. The National Graphene Association will be hosting the largest gathering of graphene companies and commercial stakeholders at the Global Graphene Expo & Conference, October 15-17, 2018, in Austin, Texas.

Learn more about graphene at the upcoming Global Graphene Expo & Conference with dedicated panels of experts and investors, and roundtable discussions on how Graphene will impact the semiconductor industry. The event promo code is SEMINGA.

About the Author

Anand Chamarthy is the CEO and Co-Founder of Lab 91, an Austin-based startup that is working towards Graphene/CMOS integration at the foundry level. Anand can be reached at [email protected].

About the National Graphene Association

The National Graphene Association is the main organization and body in the U.S. promoting and advocating for commercialization of graphene and addressing critical issues such as standards and policy development.

Originally published on the SEMI blog.

Global fab equipment spending will increase 14 percent this year to US$62.8 billion and is expected to rise 7.5 percent, to US$67.5 billion, in 2019, marking the fourth consecutive year of spending growth and the highest investment year for fab equipment in the history of the industry, according to the latest World Fab Forecast Report published today by SEMI. Investments in new fab construction are also nearing a record with a fourth consecutive year of growth predicted and capital outlays next year approaching US$17 billion.

Investments for fab technology and product upgrades, as well as for additional capacity, will grow as the emergence of numerous new fabs significantly increases equipment demand, the forecast shows. The World Fab Forecast Report currently tracks 78 new fabs and lines that have or will start construction between 2017 to 2020 (with various probabilities) and will eventually require more US$220 billion in fab equipment (Figure 1). Construction spending for these fabs and lines is expected to reach US$53 billion during this period.

Figure 1: Shows the investment potential of new fabs and lines starting construction between 2017 and 2020.

Korea is projected to lead other regions in fab equipment investments with US$63 billion, US$1 billion more than second-place China. Taiwan is expected to claim the third spot at US$40 billon, followed by Japan at US$22 billion and the Americas at US$15 billion. Europe and Southeast Asia will share sixth place, with investments totaling US$8 billion each. Fully 60 percent of these fabs will serve the Memory sector (the lion’s share will be 3D NAND), and a third will go to Foundry.

Of the 78 fab construction projects starting construction between 2017 and 2020, 59 began construction in the first two years (2017 and 2018), while 19 are expected to begin in the last two years (2019 and 2020) of the tracking period.

Equipping a new fab typically takes one to one and a half years, though some fabs take two years and others longer, depending on various factors as such the company, fab size, product type and region. Approximately half of the projected US$220 billion will be spent from 2017 and 2020, with less than 10 percent invested in 2017 and 2018, nearly 40 percent in 2019 and 2020, and the rest after 2020.

While the US$220 billion estimate is based on current insights of known and announced fab plans, total spending could exceed this level as many companies continue to announce plans for new fabs. Since the last quarterly publication of the report published last quarter, 18 new records – all new fabs – have been added to the forecast. Up-to-date and detailed analysis, with a bottoms-up approach, is available by subscribing to SEMI’s World Fab Forecast Report.

Since its June 1 publication, more than 340 updates have been made to the World Fab Forecast. The report now includes more than 1,200 records of current and future front-end semiconductor facilities from high-volume production to research and development. The report covers data and predictions through 2019, including milestones, detailed investments by quarter, product types, technology nodes and capacities down to fab and project level.

Learn more about the SEMI fab databases at www.semi.org/en/MarketInfo/FabDatabase and www.youtube.com/user/SEMImktstats.

The market for microcontrollers—the IC industry’s original system-on-chip (SoC) product category—is expected to continue hitting record-high annual revenues through 2022 after worldwide sales dropped 6% in 2016 because of a slowdown in MCU unit shipments. After drawing down MCU inventories in 2016, systems manufacturers stepped up purchases of microcontrollers in 2017 with unit shipments surging 22% and strong growth continuing in 2018.  In its Mid-Year Update to The 2018 McClean Report, IC insights raised its projection for MCU shipments to 18% in 2018 with the unit volume reaching nearly 30.6 billion. MCU revenues are now forecast to rise 11% in 2018 to an all-time high of $18.6 billion, followed by 9% growth in 2019 to about $20.4 billion (Figure 1).

Figure 1

The Mid-Year Update also raised the five-year growth projection of MCU sales to a CAGR of 7.2%, reaching nearly $23.9 billion in 2022, with unit shipments increasing by a compound annual growth rate of 11.1% to about 43.8 billion in the final forecast year.

The ASP for microcontrollers fell to the lowest point ever in 2017 and prices are continuing to drop at about the same rate in 2018. However, the annual rate of decline has eased in the last five years compared to earlier this decade.  IC Insights’ new forecast for MCU ASP shows the average selling price falling by a CAGR of -3.5% in the 2017-2022 period, much slower than the -5.8% decline seen during the 2012-2017 period and the 20-year CAGR of -6.3% between 1997 and 2017.

A key factor in the 2017 recovery of MCU sales from the decline in 2016 was a turnaround in the smartcard microcontroller segment. About 40% of total MCU shipments are currently for smartcard applications, but that is down from about half early in this decade. Excluding smartcard MCUs, sales of “general” microcontrollers for embedded systems, automated control, sensing applications, and IoT-connected things are forecast to grow 11% in 2018 to $16.4 billion after rising 14% in 2017.  Shipments of general MCUs are projected to climb 25% in 2018 to 18.9 billion units after rising 21% in 2017.   General microcontrollers now represent a little over 60% of MCU unit shipments and are forecast to reach 68% of the total in 2022.  Currently, general MCUs generate about 88% of total microcontroller revenues, and they are expected to reach 90% of the entire market value in 2022.

Across nearly all MCU applications, strong growth in 32-bit microcontrollers has reshaped the market as suppliers aggressively promote more powerful designs that are cost competitive with 8-bit and 16-bit devices, which have typically been used in consumer products and other high-volume systems.  In some cases new 32-bit MCUs are being priced below the cost of 8-bit microcontrollers.  On average, 32-bit MCUs were selling for about twice the amount of the ASP for all microcontrollers in 2012 ($1.76 for 32-bit versus $0.88 for total MCUs).  In 2018, the ASP for 32-bit MCUs is expected to be just $0.09 higher than the ASP for all MCUs, and by 2022, the difference is forecast to shrink to $0.05 ($0.60 for 32-bit versus an average of $0.55 for total MCUs).

By Michael Droeger

Over the past three decades, most of the world’s innovations have centered largely on business models and involved iterative advances of existing technologies, with none matching the global impact of the top 10 semiconductor industry discoveries and advances, Dr. Morris Chang, founder of TSMC and the IC foundry model, said at SEMICON Taiwan 2018 this week.

Few have as clear a perspective on the transformative power of semiconductors as Dr. Chang, founder of TSMC and father of the IC foundry model. Keynoting the IC60 Master Forum celebrating the 60th anniversary of the invention of the integrated circuit (IC), Dr. Chang listed what he considers the 10 key semiconductor industry innovation milestones since 1948:

1. Invention of the transistor by Shockley, Bardeen, and Brattain – 1948

2. Silicon transistor – 1954

3. Integrated circuit – 1958

4. Moore’s Law – 1965

5. MOS technology

  1. MOS FET – 1964
  2. Silicon gate – 1967
  3. CMOS  – 1970

6. Memory

  1. DRAM – 1966
  2. Flash – 1967

7. Outsourced assembly and test (OSAT) – 1960s

8. Microprocessor – 1970

9. VLSI systems design – 1970-1980

  1. IP and design tools – 1980-present

10. Foundry model – 1985

Among the most consequential semiconductor advances may be yet to come, Dr. Chang said, citing innovations including artificial intelligence (AI) and machine learning, new device architectures, Extreme Ultraviolet lithography (EUV), 2.5D/3D packaging, and new materials such as graphene and carbon nanotubes.

Dr. Chang argued that because bringing an innovation into production is immensely more expensive than proving a theory in a lab, innovators are not always the ones to implement and benefit from their novel ideas. Today, innovation costs are skyrocketing, driving more consolidation across the supply chain.

Michael Droeger is director of marketing at SEMI.

Originally published on the SEMI blog.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $39.5 billion for the month of July 2018, an increase of 17.4 percent compared to the July 2017 total of $33.6 billion. Global sales in July 2018were 0.4 percent higher than the June 2018 total of $39.3 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor industry posted its highest-ever monthly sales in July, easily outpacing last July and narrowly ahead of last month’s total,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales were up year-to-year across every major semiconductor product category and regional market, with the China and Americas markets leading the way with growth of greater than 20 percent.”

Regionally, sales increased compared to July 2017 in China (29.4 percent), the Americas (20.7 percent), Europe (11.7 percent), Japan (11.5 percent), and Asia Pacific/All Other (5.7 percent). Sales were up compared to last month in China (1.7 percent) and the Americas (0.4 percent), held flat in Asia Pacific/All Other, and decreased slightly in Japan (-0.1 percent), and Europe (-2.4 percent).

For comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, consider purchasing the WSTS Subscription Package. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2018 SIA Databook.

By Richard Allen

The arrival of Fan-Out Panel Level Packaging (FO-PLP) appears to be at a perfect time: This technology will leverage processes developed for Three Dimensional Stacked Integrated Circuits (3DS-IC) as well as panel processing technologies developed for industries such as solar panels and large-screen TVs.  In this combination, FO-PLP promised the improved performance of 3DS-IC, without the expense. There was just one problem…

That problem is the size of the panels to be processed. As different companies developed FO-PLP processes, they chose panels sized to meet certain technical or business goals, or chose a size based on familiarity. So, processes were being developed for more than ten sizes, each of which had one or more companies championing them.

For people in the wider semiconductor industry, the development of many processes, each with a unique panel size brought a feeling of déjà vu, reminding them of the 1970s, when each device manufacturer created their own specification for wafer size, forcing them to manufacture their own wafer processing equipment since no external manufacturer was willing to produce tools usable only by a single customer.

SEMI responded by developing an industry consensus silicon wafer standard – which described basic parameters, including diameter and thickness – to resolve the issue. Almost overnight the landscape changed, and new tool manufacturers sprung up, enabling the incredible growth that has persisted over more than 40 years.

Recently, Cristina Chu (TEL NEXX) presented the state of FO-PLP to the North America Chapter of the SEMI Three-Dimensional Packaging and Integration (3DP&I) Technical Committee, suggesting that the Committee develop a single standard dimension that would enable the technology to move into high-volume manufacturing.

The Committee began by surveying the industry to determine the interest level in such a standard as well as its contents.  A key finding came in response to the question “Would you support a standardized panel size?” Overwhelmingly, over 70 percent of the respondents supporting the idea for the standard, with less than 2 percent opposed. The survey also asked if other parameters should be standardized and, if so, which parameters. Majority responses pointed to edge profile, flatness, and warp, prompting the 3DP&I Committee to immediately form the FO-PLP Panel Task Force (TF) to develop such a standard. Chu and Richard Allen (NIST) agreed to chair the TF and respondents to the survey were asked to participate as TF members.

The TF initially decided to follow the model of SEMI M1, Specification for Polished Single Crystal Silicon Wafers, and write the document as a purchase specification. The purchase specification would indicate a limited number of mandatory parameters, identified as those that serve as bottlenecks to the development of a FO-PLP ecosystem. Parameters that were not perceived as bottlenecks but might be useful for implementing a FO-PLP process would be included as optional.

Working under the SEMI Standards umbrella allowed the TF to take advantage of work done in the development of other standards, without having to recreate it from scratch. In particular, Flatness and Shape were repurposed from SEMI M1, ensuring consistent definitions of these parameters.

The TF could not come to consensus on how the other parameters should be categorized, so the decision was made to move the ordering table to a new Appendix as optional.

The TF will be balloting its first specification for panel substrate in the upcoming cycle, which opens September 5, 2018 (Cycle 7). The voting is open to all industry experts. Based on the feedback, the task force will continue to refine and otherwise improve the specification by incorporating other parameters that are critical to making FO-PLP a reality.

SEMI Standards development activities take place throughout the year in all major manufacturing regions. To get involved, join the SEMI International Standards Program at: www.semi.org/standardsmembership.

For more information regarding FO-PLP Panel Task Force activities, please contact Laura Nguyen at [email protected].

Richard Allen is a physicist in the Nanoscale Metrology Group in the Engineering Physics Division of the Physical Measurement Laboratory (PML) at the National Institute of Standards and Technology (NIST). 

Originally published on the SEMI blog.

The China IC Ecosystem Report, a comprehensive report for the IC manufacturing supply chain, reveals that front-end fab capacity in China will grow to account for 16 percent of the world’s semiconductor fab capacity this year, a share that will increase to 20 percent by the end of 2020. With the rapid growth, China will top the rest of the world in fab investment in 2020 with more than $20 billion in spending, driven by memory and foundry projects funded by both multinational and domestic companies, according to the new report released today by SEMI.

The report also shows that IC Design remained the largest semiconductor sector in China for the second year in a row with $31.9 billion in revenue in 2017, widening its lead over the long-dominant IC Packaging and Test sector. The ascent of China’s IC Design sector comes as the region’s equipment market is expected to claim the top spot in 2020 for the first time on the strength of the continuing development of its domestic manufacturing capability. China’s maturing domestic fab sector is also benefiting domestic equipment and materials suppliers. Both groups continue to see gains in their product offerings and capabilities, particularly in silicon wafer production. The China IC Ecosystem Report is produced by SEMI, the global industry association and provider of independent electronics market research.

The more than RMB140 billion (US$21.5 billion) accumulated by the National IC Fund, a critical component of the 2014 National Guideline to address China’s semiconductor trade deficit, has spurred rapid gains throughout the region’s IC supply chain. Semiconductors are China’s largest import by revenue. Phase 2 of funding aims to raise another RMB150-200 billion ($23.0-$30.0 billion).

Encouraged by the National Guideline and favorable policies, skilled overseas talent is returning to China, triggering an explosion of domestic IC Design start-ups that are benefiting from access to investment and favorable policies, the report shows.

Other highlights from The China IC Ecosystem Report include:

  • Currently 25 new fab construction projects are underway or planned in China. 17 – 300 mm fabs are being tracked as part of this investment and expansion activity. Foundry, DRAM and 3D NAND are the leading segments for fab investment and new capacity in China.
  • China’s IC Packaging and Test industry is also moving up the value chain by enhancing its technology offerings through mergers and acquisitions and building advanced capabilities to entice international integrated device manufacturers.
  • China’s IC materials market, currently dominated by Packaging materials, became the second largest regional market for materials in 2016, a position it solidified in 2017. China’s materials market is expected to grow at a 10 percent CAGR from 2015 to 2019, driven primarily by the region’s new fab capacity ramp in the coming years. Fab capacity will expand at a 14 percent CAGR during that period.

The China IC Ecosystem Report covers the latest semiconductor supply chain and market developments including the rise of China’s IC industry, national and local government policies, public and private funding, and their implications for China’s IC supply chain. The report also compares key domestic companies and their international peers segment by segment. To learn more and get a sample of the report, visit http://www.semi.org/en/china-ic-ecosystem-report.

Eugenia is a Senior Product Marketing Manager at SEMI. 

Originally published on the SEMI blog.