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December 14, 2009 – At this year’s International Electron Devices Meeting (IEDM), IMEC and partners TNO (a Netherlands-based research group) and the Holst Center (IMEC–TNO joint center set up in 2005), disclosed their latest work in creating a MEMS-based piezoelectric energy harvesting device with record power generation, and a "world-first" organic transponder circuit with bit rate of 50kbits/s, nearing requirements for Electronic Product Coding (EPC) standards.

New mark in MEMS piezoelectric energy harvesting

Micromachined devices to harvest energy from vibrations typically operate in a range of 150-1000Hz, ideally used to convert energy from vibrations in machines, engines, and other industrial appliances. Their tiny size also makes them useful for powering miniaturized autonomous sensor nodes.

In work within the Holst Center’s program on micropower generation and storage, IMEC researchers created a temperature sensor that can wirelessly and autonomously transmit data — a wafer-level-packaged MEMS-based harvester, generating a record 85µW electrical power from vibrations. The harvester is a Si mass suspended on a beam, built used CMOS-compatible MEMS processes on 6" silicon wafers. Changing the dimensions of the beam and mass can modify the harvester’s resonance frequency for any value in the 150-1200Hz range.

Among the achievements IMEC noted in its work:

– Aluminum nitride is used instead of lead zirconate titanate as the piezoelectric material; AlN enables more favorable materials parameters and ease of processing, e.g. up to 3× faster deposition and better composition control due to AlN’s stoichiometric nature.
– A wafer-scale process was developed to protect the piezoelectric devices in a package: glass covers coated with an adhesive, vacuum-bonded on top and bottom of the process wafer, and diced. Power output was shown to increase significantly using a vacuum package vs. packaging in atmospheric pressure.

The harvester was connected to a wireless temperature sensor built from off-the-shelf components. After power optimization, the sensor’s energy consumption was reduced from 1.5mW to ~10µW, a three-orders-of-magnitude improvement. Subjected to vibrations at 353Hz at 0.64g (a realistic amplitude) the system generated sufficient power to measure and transmit environmental temperature to a base station with 15sec interval.


Fully autonomous wireless temperature sensor powered by a vibrational energy harvester. (Source: IMEC)

The achievement proves the feasibility of building fully autonomous energy harvesters for industrial applications, IMEC says. Once it is developed to maturity (by industry, not IMEC or Holst), the technology could power sensors for applications such as tire-pressure monitoring systems (TPMS) and predictive maintenance of moving or rotating machine parts.

 

"World’s first" 50kbit/s organic transponder

Another declaration at IEDM was the debut from IMEC, TNO, and Holst of the world’s first organic transponder circuit with 50kbits/sec bit rate, which approaches requirements for Electronic Product Coding (EPC) standards, which support the use of radio-frequency identification (RFID).

Flexible circuits are attractive for both manufacturing as well as final products in applications such as plastic RFID tags, but would need to adhere to EPC specs for item-level tagging, which requires 50kb/s bit rate. The Holst Center, wtih IMEC and TNO, have developed an 8-bit flexible transponder circuit on foil using pentacene as the semiconductor material and a high-k gate dielectric. The device’s current drive extends well beyond previous efforts with 1-2kbits/s bitrates, pushing all the way to >50kbits/s data rate, "which compares favorably" with such EPC specs.

RFID is already being used in high-volume logistics applications, e.g. pallet-level logistics; the next step is to use EPC tags at the package level, and eventually on individual items (item-level tagging). Organic electronic technology offers the promise of, and is being explored to be used for, high-volume and low-cost manufacturing of simple electronic circuits. "The new results demonstrate that the technology is now on the way to reach EPC compatibility," IMEC said in a statement.

December 14, 2009 – The Supervisory Council of the Russian Corporation of Nanotechnologies (RUSNANO) recently approved two new measures: one for producing concentrated photovoltaic technology, and participation in work to develop porous nanostructured nonmetallic coatings.

In the former, RUSNANO aims to commercialize research coming out of the Ioffe Physical Technical Institute involving scientific principles and technical basis for concentrated photovoltaic (CPV) technology. Work will involve developing photoconverters with targeted efficiency of 37%-45% utilizing "cascading solar cells" (based on a nano-heterostructure) sized 4mm×4mm onto which solar light is focused 900-fold by 50×50mm Fresnel lenses; "specially designed naturally cooling heat sinks" keep the solar modules from overheating. The CPV cells used in tandem with the concentrators will be produced via modified chemical vapor deposition (CVD) method for different semiconductor materials on germanium substrate. The work also will involve producing high-precision sun tracking systems.

A full production cycle, including cultivation of nano-heterostructures, chip manufacturing, module assembly, sun-tracking systems production, and solar PV plant assembly, will be created under the project. The resulting plants are expected to put out ~85MW/year, with anticipated revenue by 2015 exceeding €130 million. Module Solar AG and a startup around the Ioffe technology (dubbed "Solnechniy Potok," or "Solar flux") will be involved in the project. RUSNANO will invest 1.29B rubles (about US$42.6M/€29.1M) in cash, matched by the other members of the project in funding and IP; another 3.15B rubles ($104.1M/€71M) will be solicited from investors.

Nanocoatings for metal surfaces

RUSNANO also has given the greenlight to participation in development of porous nanostructured nonmetallic inorganic materials, leveraging microarc oxidation (MAO) technology developed at Tomsk State University (with equipment and engineering provided by Sibspark).

The main focus of this project will be processing lines for applying inorganic nonmetallic ceramic coatings on metal surfaces. The MAO technique, developed in the 1980s, required large amounts of energy and was more expensive than traditional treatments. The improved version developed by Tomsk researchers uses "intricately designed power sources" (no further description offered by RUSNANO) to make the process more cost-effective. MAO is said to provide better resistance against wear (up to 2&times-8×), corrosion, and heat, and improves "decorative properties" for metals including aluminum, magnesium, titanium, and zirconium, RUSNANO says. The technology is also deemed "environmentally safe" as it is produces no cyanide and nickel/chromium waste and "is less explosion hazardous."

Total budget for the project, to be housed at Tomsk, will be 105M rubles ($3.5M/€2.4M), with 50M rubles ($1.6M/€1.1M) financed by RUSNANO; EleSi, a developer of industrial automation systems, also will co-invest in the project and provide implementation support. Full capacity output starting with 20 MAO processing lines/year is expected in three years.

Opportunities are seen in applications for construction, engineering, consumer electronics, and automotive/aircraft, both in Russia and worldwide. RUSNANO pegged the metal processing market art $34.6B in 2008, of which ~$4.5B was accessories and consumables; from 2009-2015 the larger market is expected to grow 6% annually to exceed $52B.

"The energy efficiency of MAO can provide a large-scale replacement of traditional surface treatment technologies such as electroplating, anodizing, and many others, allowing for greater hardness together with low-cost production and environmental safety," said Constantine Demetriou, managing director of RUSNANO, in a statement.

December 11, 2009 – Researchers at the National Institute of Standards and Technology (NIST) and the Naval Research Laboratory have devised a technique to selectively and singularly implant atoms in a semiconductor crystal to better understand the material‘s electrical and magnetic properties, key knowledge needed to develop spintronics-based devices.

Their work, published in the journal Nano Letters, centers on introducing atomic impurities to make a semiconductor magnetic (dilute magnetic semiconductors, or DMS); to become "active" the impurities dislodge one of the structure’s original atoms. In DMS materials research, understanding how the impurity atoms actually get into the host crystal lattice sites, and thus ensuring that all the dopes magnetic impurity atoms are activated, is an essential step in achieving high operating temperatures, NIST notes.

Specifically, this new work involved depositing single manganese atoms onto an indium arsenide surface; to become active, the manganese atom must knock out an indium atoms by occupying an indium lattice site. They used an STM probe tip to apply enough voltage to dislodge an indium atom and switch places with the manganese atom — a process likened to "musical chairs" that enables selection of manganese atomic activation.

Such an exchange happens rapidly, though — so to determine the exact atomic pathway the atoms take, the Naval Research Labs made theoretical models and identified two possible avenues for the exchange; comparing those results with NIST’s experimental STM findings found the correct pathway.

The work was supported in part by the Korea Research Foundation grant program (MOEHRD), the Office of Naval Research and a cooperative agreement from the NIST-CNST/UMD-NanoCenter. Computations were performed at the Department of Defense Major Shared Resource Center at the Air Force Research Laboratory at the Wright-Patterson Air Force Base in Ohio.

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Left: An atomic-resolution scanning tunneling microscopy (STM) image of an indium arsenide crystal surface, where a manganese atom has been inserted in place of one of the indium atoms. The displaced indium atom appears as the bright yellow feature on the surface; the embedded manganese atom is only evident by its effect on the neighboring arsenic atoms (the dumbbell-shaped yellow feature).
Right: Theoretical simulation of the STM image after the atoms finish playing musical chairs, illustrating the origin of the features seen in the experiment. (Source: NIST/Steven Erwin, Naval Research Laboratory)

 

December 11, 2009–A recently published report from iRAP, Inc., Nanolithography Equipment for IT, Electronics and Photonics – A Technology, Industry and Global Market Analysis, the overall market for wafers and nanofabrication equipment is expected to grow at 11% a year for the next five years, from an estimated $65.8 billion in 2009 to $111 billion in 2014.

Researchers say the goal of the study was to determine the current and future financial and technological state of the nanofabrication equipment industry for the IT and electronics businesses, as well as the influence of related nanotechnologies. One of the objectives was to determine how many organizations in each nation were involved in different types of nanofabrication equipment. The study provides a review of the activities of the top organizations developing nanofabrication equipment and techniques for IT and electronics.

Nanofabrication equipment is the enabling technology for IT and electronic devices now being sold, says the report, and this will continue to be so.  iRAP researchers say "there is no other technology on the horizon that can compete with nanofabrication equipment in the ability to create the most powerful microprocessors and memory chips for computers, electronic devices and other applications. The industry is considered critical to continued economic development in the U.S. as well as Japan, China, Korea and the member states of the European Union."

Nanoscale lithographic apparatus are indispensible tools used to manufacture integrated circuits (ICs), flat panel displays, optoelectronic and photonic devices as well as micro-electromechanical systems (MEMS), all involving nanoscale structures. The advancement in photolithography technology has been the key to the rapid development of the semiconductor industry. "Countless innovations and progress in this field will continue to drive technological development in the semiconductor industry," says the report. "Nanofabrication equipment has been used to create integrated circuits in the 65nm to 45nm range, and companies are now moving to manufacturing computer chips and memory chips in the 32nm range."

In 2008, nanofabrication apparatus enabled semiconductor manufacturers to transform more than $11.4 billion worth of silicon wafer material into more than $425 billion worth of semiconductor, photonic, opto-electonic and MEMS material devices for use in computers and electronic devices, which in turn constituted a global market valued in excess of $1.38 trillion dollars, plus related services valued at $5 trillion dollars globally. Semiconductor and electronics manufacturers spent roughly $80 billion in 2007 and $74 billion in 2008 for silicon wafers, materials and equipment which allowed them to manufacture integrated circuits at scales to 45nm, and they are now beginning to buy equipment to manufacture integrated circuits at the scales of 32nm and 22nm.

The equipment for deposition of materials onto silicon wafers represented 19% of the nanofabrication market and was valued at $11.4 billion for 2008. Lithographic equipment was 20% of the market, valued at $12.4 billion. Beam technology and light sources associated with lithography and semiconductors represented 9% of the market and were valued at $5.594 billion. Testing of semiconductor components and processes represented 17% of the nanofabrication market with a value of $10.56 billion. Metrology was 11% of the 2008 market, with a value of $6.83 billion. Other processes were 6% of the 2008 market, with a value of $3.730 billion.

The iRAP study identified over 200 companies and institutions involved in as   manufacturers and developers as well as researchers. These companies, says iRAP, "are driving the technology to the next generation of nanofabrication in the semiconductor industry."


UCLA, IBM grow SiGe nanowires


December 10, 2009

December 10, 2009 – Researchers at UCLA and IBM say they have successfully grown silicon germanium semiconducting nanowires that take a step closer to using nanowires in next-generation electronic devices.

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Frames showing a ledge moving along the interface between a catalyst and a 21nm diameter Si wire during VSS growth at 490°C with 5×10-6 Torr Si2H6. (A-C) A ledge, arrowed, propagates along the interface; (D) the ledge reaches the end of the interface; (E) a new ledge appears. The images are labeled with the elapsed time since the appearance of the first ledge. The growth rate of the wire is 2.8nm/min. On average a new ledge forms every 12.7 seconds and crosses the interface at 1.5nm/sec; the next ledge forms after the previous one has crossed the interface. Note that ledge flow can not be clearly resolved in TEM if the ledge moves parallel to the viewing direction, so the incubation time for nucleation of a ledge could be shorter than the time between (D) and (E), 3.4 sec. (Source: Science)

Their work, published in the Nov. 27 issue of the journal Science, involved creating nanowires with layers of different materials (Si and Ge) that were defect-free and one-atom-thick sharpness at the junction, which they note are "critical requirements" for efficient transistors. The work also has application in thermoelectrics (converting heat to electricity); "the Jet Propulsion Laboratory uses bulk chunks of silicon-germanium to power their satellites, and now there is a lot of interest in using a similar technology in automobiles," according to Suneel Kodambaka, UCLA professor of materials science and engineering, in a statement.

In their work, they used tiny particles of a gold-aluminum alloy (instead of conventional liquid semiconductor-metal eutectic droplets), heated to >370°C and melted inside a vacuum chamber; a "silicon-containing gas" was then introduced to precipitate the silicon and form wires under the droplets. A germanium-containing gas was used to form the germanium wires. Cooling the liquid droplets into solid form enabled excess silicon to be removed from the alloy; then Ge wire segments could be grown on the silicon with introduction of germanium vapor, and sharp interfaces formed, explained Kodambaka.

From the journal paper abstract:

We demonstrated single interfaces that are defect-free and close to atomically abrupt, as well as quantum dots (i.e., Ge layers tens of atomic planes thick) embedded within Si wires. Real-time imaging of growth kinetics reveals that a low solubility of Si and Ge in the solid particle accounts for the interfacial abruptness. Solid catalysts that can form functional group IV nanowire-based structures may yield an extended range of electronic applications.

"This study is significant because it provides a solution to the problem of growing sharp interfaces in nanowires, thereby addressing an important limitation in the growth of nanowires," stated Frances Ross, manager of IBM’s nanoscale materials analysis department and corresponding author of the study.

Next phase of work will involve scaling up area of the nanowire growth in a conventional growth reactor, instead of under a microscope, and properties will need to be improved to be comparable to conventional nanowires. At that point work will shift to explore new devices and different metal alloys for making devices, Ross said.

December 9, 2009–SUSS MicroTec will join the Front End Processes (FEP) program of SEMATECH, collaborating with SEMATECH’s FEP device and reliability experts to investigate complex semiconductor probing and measurement solutions for next-generation semiconductor and emerging technologies.

To enable advances in conventional and emerging semiconductor devices, SEMATECH’s FEP program is researching cutting-edge new materials and device structures. The collaborative work between SUSS MicroTec and SEMATECH’s FEP research teams will aim to develop new characterization techniques to enable both CMOS scaling and emerging technologies beyond CMOS.

Additionally, as a part of this joint effort, advanced emerging memory and MEMS/NEMS technology characterization methods will also be addressed. SEMATECH will use SUSS MicroTec’s probe system and control software to characterize new device processes and designs.

“We are excited to be a part of the SEMATECH FEP program, working with the most advanced technologists to develop and characterize new materials and tools for the continued improvement of semiconductor technologies,” says Frank Averdung, president and CEO of SUSS MicroTec. Adds Raj Jammy, vice president of emerging technologies at SEMATECH, “This joint research initiative with SUSS MicroTec reinforces SEMATECH’s commitment to develop practical solutions for leading-edge technologies that are increasingly relying on new materials and structures for continued performance improvement.

December 8, 2009 – Researchers from Stanford U. have devised a way to turn ordinary paper into a battery: slather it with an inky concoction of carbon nanotubes and silver nanowires, and then cook it.

Coating a sheet of paper with ink containing carbon nanotubes and silver nanowires turns the paper into a "supercapacitor," which holds an electric charge like a battery but for a shorter period of time, and stores/discharges it much more rapidly. The particular version they came up with can last through 40,000 charge-discharge cycles, "at least an order of magnitude" better than conventional lithium-ion batteries, they claim. The thicker the coating, the greater the electrical storage/conductivity.

Yi Cui, assistant professor of materials science and engineering at Stanford, had previously done work on making such capacitive creations using plastics, but found the nanoink adheres better to the paper-based versions and makes them more durable; it can be folded and even soaked in acids or bases and performance does not degrade ("We haven’t tested what happens when you burn it," Cui quipped in a statement), and the CNTs resist peeling. No added adhesives also eliminates a factor that would otherwise decrease performance and increase production costs, the researchers note.

From their research, published this week by the Proceedings of the National Academy of Sciences:

Here, we show that commercially available paper can be made highly conductive with a sheet resistance as low as 1 ohm per square (Ω/sq) by using simple solution processes to achieve conformal coating of single-walled carbon nanotube (CNT) and silver nanowire films. […] When only CNT mass is considered, a specific capacitance of 200 F/g, a specific energy of 30-47 Watt-hour/kilogram (Wh/kg), a specific power of 200,000 W/kg, and a stable cycling life over 40,000 cycles are achieved. These values are much better than those of devices on other flat substrates, such as plastics. Even in a case in which the weight of all of the dead components is considered, a specific energy of 7.5 Wh/kg is achieved.

The main application for this work would be large-scale storage of electricity on the grid, in wind farms and solar energy systems. Other potential applications range from serving as the nonmetallic current collector in Li-ion batteries, to brushing onto a wall to create a conductive energy storage device to which LEDs could be connected, to use in electric or hybrid cars. "Society really needs a low-cost, high-performance energy storage device, such as batteries and simple supercapacitors," Cui said. "I don’t think it will be limited to just energy storage devices," noted Peidong Yang, professor of chemistry at the U. of California-Berkeley, quoted by Stanford. "This is potentially a very nice, low-cost, flexible electrode for any electrical device."

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SEM images of: (A) interface between carbon nanotubes and silver nanowires on Xerox paper, (B) Ag NW film, and (C) CNT film. (D) The resistance scaling with the Ag NW electrode distance. (Inset) Contact resistance measurement scheme. (Source: PNAS)

 

December 8, 2009 – How does he do it? How does Santa whisk himself all over the globe in just a matter of hours? One researcher from North Carolina State offers some "clues" which show that the jolly old man is far ahead of the rest of us in understanding materials science, thermodynamics, and relativity.

First of all, Santa’s sleigh is a marvel of aerodynamics, far surpassing any conventional air transportation. The entire truss is made from a honeycombed titanium alloy, making it very lightweight and 10×-20× stronger than anything existing today — and it can morph its shape to slice through the air, e.g. by tucking its runners during flight and spreading them to land on various surfaces like pitched roofs, according to NCSU’s Larry Silverberg, prof. of mechanical and aerospace engineering, who claims to have completed a six-month "visiting scholar program" at Santa’s Worshop labs in the North Pole. Moreover, the entire sleigh has a nanostructured porous "skin" that creates a surrounding low-pressure region, reducing drag by as much as 90%.

Powering the sleigh is the well-known team of reindeer — but now understood to be in precise alignment, wearing cold-fusion-powered jetpacks. The driver’s reins not only turn the reindeers’ heads but also direct the orientation of the jetpacks. (The principles of cold fusion remain a closely guarded secret, he notes.)

Having a firm grasp on the theory of relativity and its implications in our physical world (i.e., stretching time, squeezing space, and bending light), Santa steers his sleigh to utilize controllable domains of time-modification called "relativity clouds" to zip around the ~200M sq. mi. of earth seemingly in the blink of an eye. Thus, the ~100mph speeds his CF-enabled steeds achieve in his frame of reference appears to the rest of us as wink-of-an-eye travel.

Inside the sleigh is a veritable treasure-trove of electronic gadgetry, including laser sensors to detect upcoming thermals and wind conditions (for optimizing navigation); and Santa’s "magic sack" — i.e., a reversible thermodynamic processor, powered by carbon-based chimney soot and "local materials," that applies high-precision electromagnetic fields to create toys on-site (eliminating gift transportation and dramatically reducing the vehicle’s overall weight).

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December 3, 2009 – Researchers at the California Institute of Technology (Caltech) have combined the self-assembly ability of DNA with electronic properties of carbon nanotubes (CNT) to address the problem of organizing CNTs into nanoscale electronic circuits.

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(a) Single-wall carbon nanotubes labeled with "red" and "blue" DNA sequences attach to anti-red and anti-blue strands on a DNA origami, resulting in a self-assembled electronic switch. (b) An AFM image of one such structure. The blue nanotube appear brighter because it is on top of the origami; the red nanotube sits below. Scale bar is 50nm. (c) A diagrammatic view of the structure shown in b. The gray rectangle is the DNA origami. A self-assembled DNA ribbon attached to the origami improves structural stability and ease of handling. (Credit: Paul W.K. Rothemund, Hareem Maune, and Si-ping Han/Caltech/Nature Nanotechnology)

DNA origami is a type of self-assembled structure that can be programmed to form various shapes and patterns (e.g. smiley-faces, maps, even electrical diagrams). The structures are created from long single strands of viral DNA mixed with shorter synthetic DNA strands that bind them into desired shapes, generally 100nm on a side. Meanwhile, single-wall CNTs have intriguing electrical, strength, and heat conductive properties, but are problematic to arrange into desired patterns.

The solution they came up with was to soak the CNTs and DNA molecules in salt water, allowing the DNA to stick to the CNTs (protecting portions of them, to create a "handle" for recognition). Two batches were made ("blue" and "red"), and observed that single-strand DNA molecules with complementary sequences (e.g., "blue" and "antiblue") wrapped around to form a double helix. Next was building 100nm × 100nm "breadboards" in which DNA origami sequences are designed so that specific nanotubes will attach in preassigned positions — e.g., red-labeled CNTs crossing perpendicular to blue CNTs, to build a field-effect transistor (FET).

The systems were removed from solution and placed on a surface, and leads attached to measure electrical properties — and it indeed behaved like a FET, they claim. "One carbon, nanotube can switch the conductivity of the other due only to the electric field that forms when a voltage is applied to it," explained Paul W. K. Rothemund, Caltech senior research associate, in a statement. It didn’t work perfectly, noted Erik Winfree, Caltech associate professor of computer science, computation and neural systems, and bioengineering, but "it was sufficient to demonstrate the controlled construction of a simple device, a cross-junction of a pair of carbon nanotubes."

From their paper abstract:

We synthesize rectangular origami templates (75nm × 95nm) that display two lines of single-stranded DNA ‘hooks’ in a cross pattern with 6nm resolution. The perpendicular lines of hooks serve as sequence-specific binding sites for two types of nanotubes, each functionalized non-covalently with a distinct DNA linker molecule. The hook-binding domain of each linker is protected to ensure efficient hybridization. When origami templates and DNA-functionalized nanotubes are mixed, strand displacement-mediated deprotection and binding aligns the nanotubes into cross-junctions. Of several cross-junctions synthesized by this method, one demonstrated stable field-effect transistor-like behavior. In such organizations of electronic components, DNA origami serves as a programmable nanobreadboard; thus, DNA origami may allow the rapid prototyping of complex nanotube-based structures.

The group expects to improve their approach to more reliably build complex circuits involving not only CNTs but also other elements including electrodes and wiring. And the self-assembly approach is scalable to make multiple devices at a time, they note — e.g., enabling design of logic units for millions or billions of units self-assembling in parallel.

December 3, 2009 – Researchers at Cornell say they’ve come up with a way to make graphene devices more simply, by growing the material directly onto a silicon wafer.

Their work, published in the journal Nano Letters, aims to solve a key challenge with utilizing graphene and its unique properties (strength even with atomic thinness, and excellent electrical capabilities): figuring out a reproducible large-scale way to manufacture and integrate it into device circuitry, compatible with current processes. (Some efforts have involved methods as crude as stripping a layer of graphene away from graphite with scotch tape, they note.)

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A conceptual illustration of an array of single atom-thick graphene transistors. (Source: Shivank Garg/Cornell)

Drawing from previous efforts to grow graphene on copper foil, they deposited evaporated copper film onto a silicon wafer and then grew graphene on top of the wafer (the journal paper’s supplemental info more precisely describes the processes). The graphene films could then be cut using standard methods (e.g., photolithography) and the underlying copper removed via chemical solution, leaving just the graphene film draped over the silicon wafer. At that point, "you can apply any thin-film processing technique," notes lead researcher Jiwoong Park, Cornell assistant professor of chemistry and chemical biology, in a statement. To build the devices, a 100nm SiO2 layer was deposited followed by litho steps, and deposition of Cr and Au to define gate electrodes; to facilitate electrical contacts with the graphene/Ci/Ni electrode pads, windows in the SiO2 layer were opened using litho and wet etch.

From the journal paper abstract:

A novel fabrication method was used to directly pattern these graphene sheets into devices by simply removing the underlying copper film. Raman and conductance measurements show that the mechanical and electrical properties of our single layer graphene are uniform over a large area […] which leads to a high device yield and successful fabrication of ultra long (>0.5 mm) graphene channels. Our graphene based devices present excellent electrical properties including a promising carrier mobility of 700 cm2/V*s and current saturation characteristics similar to devices based on exfoliated graphene.

The researchers say they have moved on to working with full-scale 4-in. graphene wafers, as a demo for manufacturing potential. Their work is supported by DARPA and the school’s Center for Materials Research.

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Side-by-side comparison of growths on a Cu foil (left) and an evaporated Cu thin film (right). Feature sizes appear to be much larger for Cu foils than for Cu thin films. (Source: Nano Letters)