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(December 30, 2010 – BUSINESS WIRE) — ActaCell Inc. was awarded up to $3 million over a 3-year period in funding from the U.S. Department of Commerce’s National Institute of Standards and Technology (NIST). The funding will focus on production scale up of nanocomposite alloy anode materials for lithium-ion batteries to be used in electric vehicles and other demanding applications.

ActaCell won one of nine awards from NIST and is the only energy storage company recognized. The funding will come through NIST’s Technology Innovation Program (TIP). The competition focused on technologies that could scale up advanced materials and significantly improve critical manufacturing processes. TIP promotes technological innovation by providing funding support for transformative, high-risk, high-reward research projects that address critical national needs.

Actacell recently exclusively licensed the nanomaterial from the Material Sciences and Engineering Program at the University of Texas at Austin, said Bill Ott, president and CEO of ActaCell. In regards to the award, Ott noted that "the challenge with all cutting-edge technologies is the ability to scale up production. We are very confident that, through this project, we will be able to bring a whole new approach to batteries to the emerging pure electric vehicle industry."

This new electric vehicle technology is in addition to the company’s initial lithium-ion technology targeted at the Hybrid Electric Vehicle Market. Recently, ActaCell identified the medium-to-heavy duty hybrid truck market as the initial best fit for its technology based on a set of rigorous tests run in conjunction with AVL Powertrain, an engineering, solution and testing company for the automotive industry. Additionally, ActaCell was awarded a $179, 015, 16-month technology assessment of high-power cells to meet requirements specified by USABC for power-assist hybrid-electric vehicle (PAHEV) applications. The primary purpose of the USABC contract will be to assess the performance, cycle life and accelerated calendar life of ActaCell’s HEV batteries.

ActaCell is commercializing this new lithium-ion anode technology based on its ability to deliver substantially lower cost and improved safety for materials used in pure electric vehicles. ActaCell continues to leverage the work done by Professor Arumugam Manthiram and his team in the Materials Science Lab at the University of Texas at Austin. Professor Manthiram is a world-renowned scientist with more than 20 years of experience in lithium-ion battery technology. To date, ActaCell has received nearly $7 million in funding.

ActaCell develops Li-Ion technologies for motive applications. Learn more at http://www.actacell.com/

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(December 30, 2010 – BUSINESS WIRE) — ActaCell Inc. was awarded up to $3 million over a 3-year period in funding from the U.S. Department of Commerce’s National Institute of Standards and Technology (NIST). The funding will focus on production scale up of nanocomposite alloy anode materials for lithium-ion batteries to be used in electric vehicles and other demanding applications.

ActaCell won one of nine awards from NIST and is the only energy storage company recognized. The funding will come through NIST’s Technology Innovation Program (TIP). The competition focused on technologies that could scale up advanced materials and significantly improve critical manufacturing processes. TIP promotes technological innovation by providing funding support for transformative, high-risk, high-reward research projects that address critical national needs.

Actacell recently exclusively licensed the nanomaterial from the Material Sciences and Engineering Program at the University of Texas at Austin, said Bill Ott, president and CEO of ActaCell. In regards to the award, Ott noted that "the challenge with all cutting-edge technologies is the ability to scale up production. We are very confident that, through this project, we will be able to bring a whole new approach to batteries to the emerging pure electric vehicle industry."

This new electric vehicle technology is in addition to the company’s initial lithium-ion technology targeted at the Hybrid Electric Vehicle Market. Recently, ActaCell identified the medium-to-heavy duty hybrid truck market as the initial best fit for its technology based on a set of rigorous tests run in conjunction with AVL Powertrain, an engineering, solution and testing company for the automotive industry. Additionally, ActaCell was awarded a $179, 015, 16-month technology assessment of high-power cells to meet requirements specified by USABC for power-assist hybrid-electric vehicle (PAHEV) applications. The primary purpose of the USABC contract will be to assess the performance, cycle life and accelerated calendar life of ActaCell’s HEV batteries.

ActaCell is commercializing this new lithium-ion anode technology based on its ability to deliver substantially lower cost and improved safety for materials used in pure electric vehicles. ActaCell continues to leverage the work done by Professor Arumugam Manthiram and his team in the Materials Science Lab at the University of Texas at Austin. Professor Manthiram is a world-renowned scientist with more than 20 years of experience in lithium-ion battery technology. To date, ActaCell has received nearly $7 million in funding.

ActaCell develops Li-Ion technologies for motive applications. Learn more at http://www.actacell.com/

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(December 29, 2010) — SPP Process Technology Systems (SPTS), a supplier of advanced capital equipment and process technologies for the global semiconductor industry and related markets, has shipped an APS etch system to Fraunhofer ISIT (FhG-ISIT). The system will add new process capability to ISIT’s MEMS manufacturing line to fuel next generation development of devices such as actuators, sensors, and energy harvesters.
 
"We have chosen to add APS to extend our offerings to the full range of deep etch processing for all MEMS and related technologies. We are now capable of not only high-performance deep silicon etching, but also for challenging etches in hard materials, such as piezoelectric films, oxide films, glass and Pyrex," explained Christian Schroeder, MEMS technology manager at FhG-ISIT.
 
Kevin T. Crofton, EVP and managing director of Single Wafer Division at SPTS said, "We are pleased to strengthen our existing relationship with this important R&D customer. The APS source offers unique processing capabilities with its patent-protected source design, proving to be extremely effective for customers who work with a variety of materials that are difficult to etch using conventional Inductively Coupled Plasma (ICP) tools."

Learn more at http://www.spp-pts.com/ 

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(December 29, 2010 – PR.com) — Nanotechnology and nanoengineered materials are being developed rapidly for a large number of applications in all kind of sectors and products. The ability to determine nano-sized materials’ performance parameters is made possible, in part, through characterization by x-ray diffraction (XRD). From particle size paremeters to phase identification and confirmation, XRD is playing a vital role in this emerging industry.

inXitu Inc. provides benchtop and portable XRD-based instrumentation specializing in developing the technologies required to enable the next generation of scientific instruments used for materials analysis including a recently introduced variant of its popular benchtop instrument, BTX II. The technology used in its portable rock and mineral analyzer is used with specific application to nanoengineered materials. This new line of instruments offers performance comparable to laboratory XRD systems with the benefit of ease of use, significantly reduced sample preparation and reduced cost of acquisition and operation, the company reports.

The powder handling methods can improve the quality of XRD data while reducing the requirements for sample preparation. inXitu’s patented technique enables quality XRD data collection regardless of the grain size of the sample. Grain sizes up to 400um have been tested producing data normally obtained with micron-size particles.

Incorporating key technologies from its portable XRD instrument and advanced sample handling techniques, inXitu has developed solutions targeted for identification and analysis in the areas of material analysis, pharmaceuticals, forensics, art and archaeological materials. Learn more at www.inxitu.com

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(December 28, 2010) — The University of Michigan College of Engineering will present Packaging for MEMS March 31 to April 1, 2011, in Boston, MA. MEMS packaging is a significant part of product cost. This program highlights what to consider in developing application-specific packaging that will meet your goals for product performance, durability, and total cost.

Using the right MEMS packaging is critical for product sucess, point out the conference organizers. MEMS packaging is a significant part of product cost. This program highlights what to consider in developing application-specific packaging that will meet goals for product performance, durability, and total cost. Learn about extension of existing technology, exciting new technologies coming up, how to make MEMS packaging more specific to applications, and what’s going on in research. Examples of strengths and shortcomings of various packaging schemes are included.

The conference invites product design engineers and engineering managers of MEMS device manufacturers to attend, as well as engineers, managers, and system designers who use MEMS devices in their products.

This program is a joint presentation by U-M Electrical Engineering and Computer Science, The Center for Wireless Integrated MicroSystems (WIMS), and The Center for Professional Development.

Register online at www.InterPro.engin.umich.edu

The Center for Wireless Integrated Micro Systems (WIMS) is a world leader in developing packaging technology for a variety of MEMS systems. For more information about WIMS including education, research highlights, patents, and publications, see www.wimserc.org

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(December 28, 2010) — The University of Michigan College of Engineering will present Packaging for MEMS March 31 to April 1, 2011, in Boston, MA. MEMS packaging is a significant part of product cost. This program highlights what to consider in developing application-specific packaging that will meet your goals for product performance, durability, and total cost.

Using the right MEMS packaging is critical for product sucess, point out the conference organizers. MEMS packaging is a significant part of product cost. This program highlights what to consider in developing application-specific packaging that will meet goals for product performance, durability, and total cost. Learn about extension of existing technology, exciting new technologies coming up, how to make MEMS packaging more specific to applications, and what’s going on in research. Examples of strengths and shortcomings of various packaging schemes are included.

The conference invites product design engineers and engineering managers of MEMS device manufacturers to attend, as well as engineers, managers, and system designers who use MEMS devices in their products.

This program is a joint presentation by U-M Electrical Engineering and Computer Science, The Center for Wireless Integrated MicroSystems (WIMS), and The Center for Professional Development.

Register online at www.InterPro.engin.umich.edu

The Center for Wireless Integrated Micro Systems (WIMS) is a world leader in developing packaging technology for a variety of MEMS systems. For more information about WIMS including education, research highlights, patents, and publications, see www.wimserc.org

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(December 28, 2010) — The IEEE International Electron Devices Meeting (IEDM) 2010, which took place early in December in San Francisco, included papers on all aspects of advanced semiconductor manufacturing. Techcet’s Michael A. Fury reviews several papers he saw at IEDM covering Nobel-Prize-garnering nanomaterial graphene.

(Additional information can be found online at 2010 IEDM Technical Program, using paper numbers provided here as a guide. All figures are reproduced with permission of IEDM.)

9.6: In a late news paper, Y.Q. Wu of IBM Research described the RF performance of a short (70nm) channel graphene FET on SiC. With careful control to minimize the contact resistance to the graphene, a cutoff frequency of 170GHz was obtained at a drain voltage of 2.2V. With further optimization and use of a self-aligned gate structure, a cutoff of 350GHz is believed to be achievable at 90nm channel length.

Figure 1. SEM image of a finished RF device (a, b); schematic view of a top-gated RF graphene FET (c). Source: Paper 9.6

23.1: An invited paper on graphene-based fast electronics and optoelectronics was presented by P. Avouris at IBM Research. Wafer-scale graphene was fabricated by desorbing Si at 1450°C from the Si face of a SiC wafer. Devices were then fabricated on a single crystal terrace. Although graphene is a zero bandgap material, bandgap devices can be fabricated using dual- or multi-gate structures. A 240nm gate device fabricated on a single terrace showed an fT of 230GHz. Graphene’s properties suggest that photodetector applications are an appropriate fit. A fast photodetector using alternating Pd and Ti electrodes was shown to work well at 10Gb/sec.

Figure 2. Schematic and SEM of the multifinger, two-different metal graphene photodetector and its utilization to detect optical data streams at 19Gbit/s. Bottom: Open eye test indicating error-free detection of optical data at 10GBits/s. Source: Paper 23.1

23.2: I. Meric of Columbia U fabricated a graphene FET using h-BN (hexagonal) as the gate dielectric, which has a lattice mismatch to graphene of only 2% but a thermal conductivity 600× greater than SiO2. The device configured with a Cr/AuPd ohmic contact had a mobility of 10,700 cm2/Vsec and good saturation behavior at gate lengths of 3μm, 1μm and 0.5μm, but high contact resistance remains to be reduced.

Figure 3. Optical image of GFET (left); schematic of the back-gated device structure (right). Source: Paper 23.2

32.4: K. Majumdar of the Indian Institute of Science simulated a dual-gated device with doped semiconductor source & drain and a bilayer graphene (BLG) channel. The bandgap-free nature of graphene is overcome by inducing a bandgap with the dual gates. Objective of the modeling is to obtain complementary unipolar BLG FETs for logic devices. The simulated device characteristics compare well with state-of-the-art Si technology, with IOn /IOff >104 and a subthreshold slope of ~110mV/decade for a 20nm gate length.

Figure 4. (a) Schematic of a d with source (S) and drain (D). (b) Bandstructure of an unbiased infinite BLG film with zero bandgap. (c) Bandgap opening in a "Mexican hat" shape under applied external vertical field. (d) Typical experimental transfer characteristics of a metal S/D BLG FET with on-off ratio of ~100 at Vdd=1mV and T=295K. Source: Paper 32.4.

Michael A. Fury, Ph.D., is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail [email protected]

Read Fury’s other observations from IEDM Day 1, Day 2 AM and PM, and Day 3.

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(December 27, 2010) — Nanoscience Instruments, a distributor of nanotechnology instrumentation and supplies, announced a new benchtop carbon nanotube (CNT) synthesis device. The Nanotech Innovations SSP-354 is a low-cost system for producing high-quality, multi-walled carbon nanotubes. The device uses an injection CVD process developed at NASA and is integrated into an instrument small enough to fit in a fume hood. The system can produce research-quality, multi-wall carbon nanotubes within a few hours.

The SSP-354 CNT system was designed for affordability and ease of use. The user injects Nanotech Innovations’ organometallic precursor solution into a two-zone furnace where iron catalyst particles are formed. Once growth is catalyzed, the nanotubes form on the surface of a quartz process tube, which is later removed to collect the material. The nanotubes average 50nm in diameter and can be anywhere from several micrometers to a few hundred micrometers in length, depending on operating parameters.

Because the design eliminates many of the steps normally required in producing CNTs, the system suits educational environments where students may be trained to both produce and characterize CNTs. "The SSP-354 CNT system is a great complement to our easy to use AFMs," says Mark Flowers, director at Nanoscience Instruments. "We can now provide simple and cost-effective nanomaterial fabrication along with our line of characterization tools."

Nanoscience Instruments Inc. provides products and services for nanoscience and supports research and engineering at universities, government laboratories, and industrial R&D facilities around the world. More information can be found at www.nanoscience.com

Nanotech Innovations LLC was formed in 2005 to commercialize the NASA technology that is at the heart of the SSP-354 system and process. The company received the patent in July 2010 and continues to produce systems for sale to the educational and research markets as well as investigate the production of new nanomaterials.

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(December 27, 2010 – Business Wire) — Analog Devices Inc . (NYSE: ADI), high-performance semiconductor maker for signal-processing applications, announced that the U.S. International Trade Commission (ITC) ruled decisively in favor of Analog Devices in its lawsuit against Knowles Electronics. Administrative Law Judge Robert K. Rogers, Jr. concluded that Knowles infringes valid claims from one of ADI’s Wafer Anti-Stiction Application (WASA) patents.

Specifically, Judge Rogers ruled that Knowles infringes claims 2, 3, 4, 5, 6 and 8 from ADI’s U.S. Pat. No. 7,364,942. As a result, ADI expects the ITC to issue an exclusion order prohibiting Knowles and its U.S. distributor from importing or selling all infringing microphones in the United States. Additionally, ADI expects to recover damages on all past sales of Knowles’ microphones through its pending lawsuit against Knowles in Delaware.

"Analog Devices began investing in MEMS in 1989 and has developed an extensive and innovative MEMS IP portfolio," commented Mark Martin, VP, MEMS/Sensor Technology Group, Analog Devices. "We have leveraged this investment to create the highest performance MEMS microphones available. We are very pleased that Judge Rogers ruled in our favor confirming the strength of our MEMS IP portfolio."

This recent ruling follows ITC Judge Rogers’ ruling on November 22nd when he found Knowles Electronics’ MEMS microphone packaging patents were invalid, a ruling consistent with the position taken by the U.S. Patent and Trademark Office, where all of Knowles’ asserted claims were rejected in separate reexaminations.

ADI’s iMEMS are used in motion sensors and MEMS microphones. iMEMS microphones integrate a MEMS transducer with an audio ASIC. iMEMS microphones and their many performance advantages will differentiate and radically change acoustic input designs in future electronics devices. iMEMS is a registered trademark of Analog Devices Inc. For more information, visit www.analog.com/mic.

Analog Devices (ADI) manufactures high-performance integrated circuits used in analog and digital signal processing applications. Analog Devices’ common stock is listed on the New York Stock Exchange under the ticker "ADI" and is included in the S&P 500 Index. Learn more at http://www.analog.com.

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(December 27, 2010 – PRNewswire) — IBM (NYSE: IBM) Research is the first to measure the movement and processing of digital data as a magnetic pattern on nanowires 1,000 times finer than a human hair. Racetrack Memory uses the spin of electrons to move data at hundreds of miles per hour to atomically precise positions along the nanowire "racetrack."

IBM Researchers revealed a previously unknown aspect of key physics inside Racetrack memory — a new technology design which stands to improve memory capabilities within mobile phones, laptop computers and business-class servers. This new class of memory could enable devices to store 100x more data while using much less energy than today’s designs.

The Racetrack memory project — which started in IBM’s Research labs 6 years ago — automatically moves data to where it can be used, sliding magnetic bits back and forth along nanowire "racetracks." This technique would allow electronic manufacturers to design a portable device capable of storing all the movies produced worldwide in a given year with room to spare.

Digital data is typically stored in magnetic hard disk drives, which are low-cost but slow due to their moving parts, or in solid state memory such as Flash memory, which are faster but more expensive. Racetrack memory aims to combine the best attributes of these two types of memory devices by storing data as magnetic regions, called domains, in racetracks a few tens of nanometers wide.

The new understanding, revealed in the journal Science, allows the precise control of the placement of these domains, which the IBM team has proven can act as nano-sized data keepers that can not only store at least 100 times more memory than today’s techniques, but can be accessed at much greater speeds. By controlling electrical pulses in the device, the scientists can move these domain walls at speeds of hundreds of miles per hour and then stop them precisely at the position needed — allowing massive amounts of stored information to be accessed in less than a billionth of a second.

IBM scientists were the first to measure the time and distance of domain wall acceleration and deceleration in response to electric current pulses, which is how digital information is moved and processed in Racetrack memory. This not only gives scientists an unprecedented understanding and control over the magnetic movements inside these devices but also advances IBM’s Racetrack memory — driving it closer to marketplace viability.

"We discovered that domain walls don’t hit peak acceleration as soon as the current is turned on, and that it takes them exactly the same time and distance to hit peak acceleration as it does to decelerate and eventually come to a stop," said Dr. Stuart Parkin, an IBM Fellow at IBM Research – Almaden. "This was previously undiscovered in part because it was not clear whether the domain walls actually had mass, and how the effects of acceleration and deceleration could exactly compensate one another. Now we know domain walls can be positioned precisely along the racetracks simply by varying the length of the current pulses even though the walls have mass".

To achieve the densest and fastest possible memory, the domain walls inside the device must be moved at speeds of hundreds of miles per hour to atomically precise positions along the tracks. These timescales (tens of nanoseconds) and distances (micrometers) are surprisingly long, especially since previous experiments had shown no evidence for acceleration and deceleration for domain walls driven along smooth racetracks with current.

For nearly fifty years, scientists have explored the possibility of storing information in magnetic domain walls, which are the boundaries between magnetic regions or "domains" in magnetic materials. Until now, manipulating domain walls was expensive, complex and used significant power to generate the fields necessary to do so. In a proof of concept paper in 2008 (1), IBM researchers were the first to demonstrate the potential of Racetrack memory, showing how the use of spin momentum considerably simplifies the memory device.

The details and results of this research effort were reported in the December 24, 2010 issue of Science. The paper is titled, "Dynamics of magnetic domain walls under their own inertia," and is authored by Luc Thomas, Rai Moriya, Charles Rettner and Stuart Parkin of IBM Research – Almaden.

For more information about Racetrack Memory, please visit: http://www.almaden.ibm.com/spinaps/research/sd/?racetrack

(1) Hayashi, M., Thomas, L., Moriya, R., Rettner, C. & Parkin, S. S. P. Current-Controlled Magnetic Domain-Wall Nanowire Shift Register. Science 320, 209-211 (2008)

SOURCE IBM 

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