Tag Archives: SPICE

The need for high sigma yield

February 24, 2014

By Dr. Bruce McGaughy, Chief Technology Officer and Senior Vice President of Engineering, ProPlus Design Solutions, Inc.

In the mid-1990s, the former head of General Electric Jack Welch and Six Sigma were all but synonymous. Many a corporation implemented Six Sigma to improve process quality, based on Welch’s outspoken endorsement of the program.

Today, the semiconductor industry is using similar terminology to refer to high sigma yield prediction, a means to statistically determine the impact of process variations on parametric yield for integrated circuits such as SRAM that require extremely low failure rate.

No one needs to be Jack Welch to know why. In fact, it’s a huge challenge for the industry and it has been getting the attention it deserves of late –– the move to state-of-the-art 28nm/20nm planar CMOS and 16nm FinFET technologies present greater challenges to yield than any previous generation.

The key challenge is high sigma yield analysis that covers yield from roughly the 4 to 7+ σ range –– the range where traditional Monte Carlo simulation methods break down due to the requirement of high-sample numbers with associated long run times. For 3 σ designs, Monte Carlo continues to be a viable solution.

Foundries now require SRAM memory verification to 7 σ in 16nm FinFET technology, a technical impossibility without deploying a special high sigma yield prediction tool. The reason memory bit cell yield targets are being set so high is due to large process variations and shrinking design margins at advanced nodes and larger memory sizes. Most commercially available tools are unable to address 7+σ reliably or accurately.

Multiple methods are available to tackle the high sigma challenge, discussed at length in a recent ProPlus whitepaper. The key is an accurate and reliable estimate of yield out to very high sigma values with a reasonable number of simulations.

High Sigma methods that utilize Monte Carlo as the foundation are able to take advantage of its robustness but overcome its inability to scale to high sigma analysis. Designers are further pushing the high sigma boundary running the analysis on larger and larger blocks, such as an SRAM array. The requirement to analyze large designs with tens of thousands of variables creates a compounding effect on the high sigma problem.

This gives a glimpse into the scope of the high sigma challenge. On the one hand, there is a need to validate yield out to 7+ σ ranges. On the other, there is pressure to run high sigma analysis on large designs.

Yes, challenges abound. More than one industry expert is calling for an integrated design for yield (DFY) flow to answer the challenge. That’s because the conventional design flow is outmoded and struggling under the weight of these weighty requirements. An integrated DFY flow, advise the experts, needs accurate statistical device modeling and a powerful SPICE simulator. Most important, the new flow needs yield prediction, analysis and fixing capabilities that can cover requirements from 3 to 7+ σ yield.

Few tool providers today offer all three in an integrated DFY flow. In fact, most electronic design automation (EDA) tool providers in this space offer one product that may or may not be “best in class.” While “best in class” may suggest a company focused on its core competence, it’s a mistake to think that not providing an integrated DFY flow is an acceptable practice in the era of FinFET.

Anyone in charge of developing or managing a complete DFY flow should employ the principals of Six Sigma consistently through all three stages of the whole flow. The checklist should start with an integrated DFY methodology that neatly packages statistical device modeling and a powerful SPICE simulator with yield prediction, analysis and fixing capabilities up to and beyond 7 σ.  A designer should be able to tick off on the checklist the key points of accuracy, productivity improvement, scalability, high s yield, high σ optimization, and cost effectiveness.  That’s the recommendation for EDA teams and designers in the FinFET era. And, one that Jack Welch would endorse.

Long live FinFET

February 3, 2014

By Zhihong Liu, Executive Chairman, ProPlus Design Solutions, Inc., San Jose, Calif.


FinFET technology, with its multi-gate architecture for superior scalability, is gaining momentum with foundries, EDA vendors and fabless design companies, a welcome trend that began in 2013 and will continue into 2014.

Enormous effort has been expended already by leading manufactures such as GLOBALFOUNDRIES, Intel, Samsung and TSMC and their EDA partners to support the new technology node that offers so much promise. The move to FinFET portends good things for the semiconductor industry as it enables continuous Moore’s Law scaling down to sub-10nm and delivers higher performance and lower power consumptions. The revolutionary device architecture also brings challenges to designers and EDA companies developing FinFET design tools and methodologies. The achievement of FinFET solution readiness across the design flow is a significant accomplishment, especially considering the PDK itself was migrating in parallel from v0.1 and v0.5 toward v1.0.

The industry-standard BSIM-CMG model, developed by the BSIM group at the University of California at Berkeley, uses complicated surface-potential based equations to model FinFET devices, which also require complex parasitic resistance and capacitance models. As a result, SPICE simulation performance is known to be a few times slower than bulk technology with BSIM4 models. In addition, netlist sizes for FinFET designs are large, especially for post-layout extracted simulations, the norm given the impact of process variations, including layout effects on a design. Lower Vdd, increased parasitic capacitance coupling and noise sensitivity create a need for high accuracy circuit SPICE simulation where convergence of currents and charges is carefully controlled. These issues significantly impact the type of circuit simulation solution that will be viable for FinFETs.

FinFET poses many other design challenges that both EDA vendors and designers have to respond to. For example, “width quantization” puts new requirements on analog and standard cell designers. They can only use quantized widths instead of arbitrary width values in their designs.

The FinFET harvest is just beginning. As production tapeout activity ramps up, more emphasis will be placed on improving the performance of design flows, such as accelerating simulation and better sampling methods for corners or high sigma Monte Carlo analysis. Parametric yield will continue to be a key requirement as design houses attempt to maximize ROI from an existing node or to maximize the investment into a new node. The days of “margining” to safeguard a design are over. At the newer nodes, designers will invest more time figuring out where the yield cliff actually is and making sure their design is robust and will yield in production.

As a result, designers will have to seek out new tools and methodologies to overcome FinFET design challenges. One example is the adoption of giga-scale parallel SPICE simulators to harness circuit simulation challenges in FinFET designs. Traditional SPICE simulators don’t have the capacity and lack sufficient performance to support FinFET designs, while FastSPICE simulators likely will not meet accuracy requirements. Another example is where FinFETs have created increased interest in high sigma analysis of library designs such as SRAMs, standard cells and I/Os. Designers are working hard to fulfill a foundry requirement to verify bitcell designs to 7 sigma. That requirement can only be achieved by proven variation analysis tools that can support large capacity and high sigma yield analysis out to high sigma values.

Yes, FinFET could be the technology to give the semiconductor and EDA industry a major boost. I say long live FinFET.

Read more from ProPlus Design Solutions’ Blog:

Memory design challenges require giga-scale SPICE simulation

DAC panels tackle giga-scale design challenges, semiconductor market in China

SPICEing up circuit design