Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES


Cadence selected as primary EDA tool vendor by GLOBALFOUNDRIES

02/15/2019  Cadence Design Systems, Inc. today announced that GLOBALFOUNDRIES (GF) has chosen Cadence as the primary EDA tool vendor for use in Avera Semi, a GF subsidiary, for advanced node chip design projects.
Intel names Robert Swan CEO

01/31/2019  Intel Corporation today announced that its board of directors has named Robert (Bob) Swan as chief executive officer.
ZEISS launches new high-resolution 3D X-ray imaging solutions

01/23/2019  ZEISS today unveiled a new suite of high-resolution 3D X-ray imaging solutions for failure analysis (FA) of advanced semiconductor packages, including 2.5/3D and fan-out wafer-level packages.
Value of semiconductor mergers and acquisitions falls considerably

01/17/2019  2018 semiconductor M&A valued at $23.2 billion, down from the record $107.3 billion in 2015.
FO-WLP panel production becomes a reality

12/13/2018  Panel FO-WLP is in production at Powertech Technology, Inc. (PTI) for MediaTek’s power management integrated circuit (PMIC) for smartphone applications.
SEMI launches new semiconductor manufacturing workforce development campaign

12/05/2018  The semiconductor manufacturing industry is fighting to attract, educate, and retain the necessary talent for its continued growth.
Micron President and CEO Sanjay Mehrotra elected chair of Semiconductor Industry Association

11/30/2018  Keith Jackson, President, CEO, and Director of ON Semiconductor, elected SIA Vice Chair.
Mentor adds DECA Technologies to growing Mentor OSAT Alliance for high density advanced package (HDAP) designs

11/20/2018  Mentor, a Siemens business, today announced that DECA Technologies has become the latest member of Mentor's (outsourced assembly and test) OSAT Alliance.
MEMS and sensors in autonomous and electric vehicles: Key takeaways from IHS Markit at MSEC

11/15/2018  IHS Markit’s Jérémie Bouchaud provided a closer look at and outlook for this key market at the MEMS and Sensors Executive Congress in late October in Napa. Following are key takeaways from his presentation.
IHP cooperates with EV Group on low-temperature covalent wafer bonding

11/12/2018  EVG ComBond enables wafer-level packaging and heterogeneous integration for advanced MEMS, high-performance logic, power and "Beyond CMOS" devices with micron-level alignment accuracy.
Unlocking the secrets of metal-insulator transitions

11/09/2018  X-ray photon correlation spectroscopy at NSLS-II's CSX beamline used to understand electrical conductivity transitions in magnetite.
MRSI announces HVM3 die bonding demonstration capability in Shenzhen China

11/09/2018  MRSI Systems (Mycronic Group) announces new demonstration capability at its sister company, Shenzhen Axxon Automation (Mycronic Group) facility in the Longhua district, Shenzhen, China.

Semiconductor Research Corporation welcomes SK hynix to its acclaimed GRC and NST research programs

11/08/2018  SRC research focused on next-generation semiconductor technology continues to attract the world's leading semiconductor design and manufacturing companies.
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Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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