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WEBCASTS
 Environment, Safety & Health Date and time TBD The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.
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Wafer Processing Date and time TBD As the industry moves to 10nm and 7nm nodes, advances in wafer processing etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.
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VectorGuard 3D stencils are designed for specialist applications requiring multiple level printing. Facilitating printing on different levels with upward or downward steps, VectorGuard 3D enables a uniform stencil thickness.
Rudolph Technologies Inc. (RTEC) is partnering with a major outsourced semiconductor assembly and test (OSAT) services manufacturer to provide its inspection and metrology capability in the development of stacked packaging processes. The process uses silicon interposer technology, sometimes referred to as 2.5D IC, as an intermediate step toward full blown 3D ICs.
The phoenix nanotom m, from GE´s Inspection Technologies business, has been developed for high resolution and high precision X-ray computed tomography (CT) in non-destructive 3D analysis and 3D metrology.
Jae-Woong Nah, researcher at IBM's Thomas J. Watson Research Center, briefed ElectroIQ on his IMAPS conference paper: "Mask and mask-less injection molded solder (IMS) technology for fine-pitch substrate bumping." IMS is a variation of C4NP for solder deposition on fine-pitch laminates. Nah explains how the researchers injected 100% pure molten solder instead of solder paste with a reusable film mask for forming high-volume solder on fine-pitch substrates.
Package-on-package, implemented with flip chip package assembly, is meeting requirements for next-gen mobile devices. Challenges remain: fine pitch underfill, brittleness of ultra low-k (ULK) dielectrics, and shorting between adjacent bumps. Craig Mitchell, Tessera, examines the lucrative 3D packaging step and how to face these challenges.