11/20/2007  The Body Worlds exhibit at The Tech Innovation Museum, where real cadavers are preserved to expose the makeup of the human body, provided a fitting backdrop to a half-day session on "Biomedical Materials, Devices, and Packaging" at IMAPS 2007, the International Microelectronics And Packaging Society's 40th annual international symposium on microelectronics.

11/19/2007  November 19, 2007 - The MEMS Industry Group, a trade association representing MEMS and microstructure industries, and the MicroElectronics Packaging and Test Engineering Council (MEPTEC) have formed a strategic alliance to support each other's goals and industry events, through a variety of marketing programs.

11/19/2007  ; Amkor Technology Inc. has announced that Joanne Solomon has been appointed Corporate VP and CFO, succeeding Ken Joyce in that position. Solomon will continue to report to Joyce, who has been named to the new position of Chief Administrative Officer.

11/19/2007  Meredith Courtemanche in sunny San Jose, covering the 40th International IMAPS symposium, and Gail Flower, first in San Diego at the MEMS Congress, and then at Productronica in Munich, braving the cold, snow, and Deutsche Bahn strike. It was my turn to stoke the fires of Advanced Packaging from home base, with the help of Julie MacShane, our web news editor.

11/19/2007  The 880 series of clamshell burn-in sockets accommodates standard QFN packages down to 0.35mm pitch. The compression-mount clamshell is designed to allow chipmakers to remove or replace the sockets and retain production capacity if, for whatever reason, they were to damage them.

11/16/2007  By Umut Tosun, ZESTRON America; and Stefan Strixner, ZESTRON Europe

Flip chip technology was introduced in the early 1960s and used in the computer manufacturing process. Development for automotive applications followed in the 1970s. Since then, the importance of the flip chip technology has increased due to size, performance, flexibility, and cost compared to other packaging methods.

11/15/2007  November 15, 2007 - SET, the former SUSS MicroTec device bonder division spun off earlier this year, says that a partnership with CEA Leti has resulted in a new high-accuracy (0.5-micron), high-force (4000 N) device bonder for processing up to 300mm wafers.

11/15/2007  ; S.E.T., the former SUSS MicroTec Device Bonder Division, has announced that the partnership between S.E.T. and CEA Leti has resulted in a radically new-generation, high-accuracy (0.5 µm), high-force (4000 N) device bonder for wafer diameters up to 300 mm. The FC300 bonder includes a built-in chamber for collective reflow in a gas or vacuum environment and also features nanoimprinting capabilities.

11/14/2007  ; FlipChip International has introduced its new Embeddable Die Customization (EDC) technology targeted at readying integrated circuits and other devices for integration into emerging 3D packaging solutions. EDC enables the embedding of semiconductor devices within printed circuit boards or other interconnection schemes, thereby enabling lower profile, more reliable packaging schemes for applications including next generation cell phones.

11/13/2007  ; Advanced Semiconductor Engineering Inc. (ASE) and Infineon Technologies have developed a new packaging technology using embedded wafer-level ball grid arrays (eWLB) that reportedly offer an almost infinite number of contact elements in a 30% smaller package form vs. conventional lead-frame laminate packages.

11/12/2007  November 12, 2007 - Infineon Technologies says it has developed a new packaging technology in collaboration with Advanced Semiconductor Engineering Inc. (ASE) that offers "an almost infinite number of contact elements" in a 30% smaller package form vs. conventional lead-frame laminate packages.

11/09/2007  ; StratEdge, a designer and producer of semiconductor packages for microwave, millimeter wave, and high-speed digital devices, has moved its headquarters to new, state-of-the-art facilities. Still located in San Diego, the new site enables StratEdge to increase capabilities and space for package design, manufacturing, assembly, and test.

11/05/2007  Things just keep getting smaller. Two years ago at Productronica 2005, MicroNanoWorld was launched to address the increasing importance of micro-electronics production. It was continued at Electronica 2006, which alternates bi-annually with Productronica. This year, micro-electronics production is set to take center stage, as "Productronica 2007: Micro-Production in the Limelight" gets under way from November 13-16, 2007 at New Munich Trade Fair Center, Munich, Germany.

11/01/2007  ; Ultratech Inc., a supplier of lithography and laser-processing systems used to manufacture semiconductor devices, has received an order from Advanced Semiconductor Engineering Inc. (ASE) for its 300mm, advanced-packaging lithography system.

11/01/2007  Significant inroads to integrate surface-acoustic-wave- (SAW-) based electronics with sensors are producing more high-demand areas for packaging applications.

11/01/2007 

10/30/2007  October 30, 2007 - A new public/private R&D initiative is being laid out to replace the MEDEA+ program for cooperative R&D in microelectronics that is set to expire in 2008, which over the past seven years has watched over three generations of CMOS technology, and spearheaded work on fields ranging from smart cards, image sensors, and automotive electronics.

10/26/2007  ; MEPTEC, the MicroElectronics Packaging and Test Engineering Council, has finalized the program for its upcoming technical symposium titled, "Substrates: The Foundation of Semiconductor Packaging," at the Holiday Inn San Jose in San Jose, CA on Thursday, Nov 8th.

10/23/2007  ; STATS ChipPAC Ltd., an independent semiconductor test and advanced packaging service provider, today announced the grand opening of a second 371,000 sq. ft. manufacturing facility in Shanghai, China.

10/16/2007  ; IMEC and the Packaging Research Center (PRC) at Georgia Tech have put out the call for interested parties to join in their advanced research program on next-generation flip chip and substrate technology. The program addresses key IC-to-package-to-board packaging interconnect issues for 32nm ICs and beyond.