Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES



RIO Design Automation Releases Next-generation EDA Tool

06/06/2006  Santa Clara, CA — Rio Design Automation Inc, an electronic design automation (EDA) company, announced that RioMagic, their chip design software tool, now includes full support for wire bonding and flip chip designs. This next-generation release reportedly has added rules-driven I/O sequencing, prototyping, and redistribution routing (RDL) support to its capabilities.

FlipChip International and Engent Form Strategic Alliance

05/26/2006  Phoenix, AZ — Aiming to speed up development and deployment of 3-D wafer-level chip-scale packages(WLCSP) for integrated stack-die packages, FlipChip International (FCI) and Engent have formed a strategic alliance. FCI specializes in wafer-level bumping, while Engent's focus is 3-D flip chip assembly.

Freescale Orders SUSS Production Wafer-bonding System

05/25/2006  Munich, Germany — Freescale Semiconductor recently ordered one of SUSS MicroTec's ABC200 automated production wafer-bonding systems. Silicon wafer bonding is a critical wafer-level packaging technology and an enabling technology for the mass production of cost-effective MEMS accelerometers for Freescale, so SUSS' automated production wafer bonders ideally suit their needs.

Underfill Epoxy

05/16/2006  123-38A/B-187 thermally conductive underfill epoxy is designed specifically for flip chip assembly. It is a nitride-filled, 2-component compound designed to release entrapped air rapidly during cure, resulting in a smooth, pinhole-free surface.

Platform-based Pick-and-Place

05/16/2006  AdVantis XS mixes semiconductor and standard surface mount assembly in one machine with proprietary VRM linear motors for accuracy and repeatability at ±9 µm at ±3 sigma. AdVantis XS provides a low-cost alternative for placing flip chips and other advanced packages with high accuracy.

SEMI tips details about SEMICON West backend pavilion

05/08/2006  May 8, 2006 - SEMI has announced additional details about its backend technology-themed content pavilion at this year's SEMICON West, developed in conjunction with leading industry associations and companies including FSA, the International Electronic Manufacturing Initiative (iNEMI), the Microelectronics Packaging and Test Engineering Council (MEPTEC), and TechSearch International.

Focus on Flip Chips

05/01/2006  Don’t you just love being right? It took a long time for flip chips to go mainstream, but now that they have made it, it’s very satisfying.

Advanced Packaging Hits the Road

05/01/2006  Advanced Packaging thought it was time for a fresh look at what’s really happening in the semiconductor packaging industry, so we’ve hit the road.

Taiwan Relaxing Chip Packaging Export Restrictions to China

04/28/2006  Taiwan has announced it is removing restrictions on export of low-end semiconductor packaging and testing technology to mainland China, according to an Associated Press report. The news suggests significant progress in revision of Taiwan policies regarding semiconductor manufacturing technology transfers between the island and mainland China, which expired at the end of 2005.
By James Montgomery, News Editor, Solid State Technology Magazine

Report: Taiwan relaxing chip packaging export restrictions to China

04/27/2006  April 27, 2006 - Taiwan reportedly has removed restrictions on export of low-end semiconductor packaging and testing technology toChina, perhaps signaling a rethinking of broader restrictions on semiconductor manufacturing technology transfers to the mainland.

Japan firm boosting packaging output

04/21/2006  April 21, 2006 - Ibiden Co. reportedly plans to invest 8.5 billion yen (about US $72 million) to build a new semiconductor packaging facility in Ogaki, Gifu Prefecture, to tap demand for chip packaging used in PCs and mobile phones.

Photoresist Coating/Spray Nozzle

04/17/2006  Nano Spray technology achieves conformal coating of extreme surface topographies, demonstrating conformal coatings of vertical via walls 300-µm deep and 100-µm in diameter. This enables further lithography steps in the bottom of the via to create through-wafer interconnects.

IC Packaging Market Hits $23.1B in '05

04/07/2006  San Jose, CA — In 2005, a reported 116 billion ICs were produced worldwide in 2005, bringing the IC packaging market's value to $23.1 billion, claims Electronic Trend Publications (ETP) in its latest report, The Worldwide IC Packaging Market — 2006 Edition. ETP reports that out of the 116 billion ICs, 37 billion were assembled by contract packaging companies, totaling $9 billion.

DuPont, Fraunhofer Join Forces in Applications Development

04/06/2006  Research Triangle Park, NC — DuPont Semiconductor Packaging & Circuit Materials and the Fraunhofer Institute for Reliability and Microintegration IZM recently joined together in an applications development agreement, in which Fraunhofer will help to refine and optimize the processes of DuPont's expanding wafer-level and chip scale packaging (CSP) materials portfolio.

Keynote Explains 3-D Stacking

04/03/2006  The main purpose of 3-D stacking of semiconductor die is not to save space — it is to save time. "To bring cells closer together by stacking them vertically, so that they are connected through only the thickness of the silicon," explained Philip Garrou, Ph.D., of RTI International. "Die stacking is not bringing more integration into the IC, but disassembling it."
By George Riley, Ph.D., contributing editor

Breaking Down the Barriers for True Innovation

04/01/2006  Senior executives at semiconductor companies worldwide have an innovation crisis on their hands.

Device Packaging Conference Takes Off

03/31/2006  Phoenix, AZ — The second annual IMAPS Device Packaging Conference, March 20–23, drew double the audience of last year. Sessions were crowded, exhibit space was sold out, and excitement was high. The conference, which this year incorporated the former IMAPS Flip Chip Workshop, offered three keynote speakers and five parallel tracks, with 26 sessions totaling about 100 papers.
By George Riley, Ph.D., contributing editor

SUSS Installs Probe Systems in IMEC Research Center

03/30/2006  Munich, Germany — SUSS MicroTec AG has installed PA300PS ProbeShield semiautomatic probe systems with ReAlign and ContactView technology and PA300 probe systems for RF-noise and S-parameter measurements at IMEC, a Leuven, Belgium-based nanoelectronics research center. The two companies will also collaborate on enhancing 300-mm probe systems in the future.

Registration Closing for iNEMI Roadmap Workshop

03/22/2006  Herndon, VA — Registration for the International Electronics Manufacturing Initiative (iNEMI)'s 2007 Roadmap workshop, to be held together with SEMICON Europa in Munich, Germany, on April 5th, closes on March 28, 2006, barring full capacity prior to the date. The full-day meeting will give attendees a first-look at draft chapters of the 2007 Roadmap, including two key market segments and eight technology and infrastructure areas the Roadmap covers.

Intel gives nod to top suppliers

03/22/2006  March 22, 2006 - Intel Corp. has handed out its annual awards to more than three dozen suppliers from its roster of thousands of supply-chain partners, ranging from capital equipment manufacturers to materials, components, and service providers.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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