Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES



The back-end process: Step 7 - X-ray inspection

07/01/2002  Flip chip challenges

die products

07/01/2002  Standards provide key to progress

Flexible flip chip

07/01/2002  Solutions for high-performance applications

10th Anniversary Insights
New (?) and emerging (?) technologies


07/01/2002  Today, packaging and assembly of integrated circuits (ICs) can be characterized as an aggressive ongoing development effort

Database for die products

07/01/2002  To assist design engineers working with bare die, the Die Products Consortium (DPC) has created a database of information on available die products

UTAC establishes US design center

07/01/2002  United Test and Assembly Center (UTAC) is setting up a package design center in Pleasanton, Calif., to support the design needs of customers in North America

CSPs, stacked packaging proliferate

07/01/2002  Several announcements by major semiconductor manufacturers indicate the extent to which advanced packaging technologies have permeated mainstream products

Advanced Packaging added to Chemical Abstracts Service

07/01/2002  The American Chemical Society has selected Advanced Packaging for inclusion in its Chemical Abstracts Service (CAS)

SEMICON West San Jose - Program Highlights

06/21/2002  (June 24, 2002) San Jose, Calif. -- Held here July 17 through 19, 2002, at the San Jose Convention Center, SEMICON West (Final Manufacturing) is packed with courses, classes and networking opportunities.

Phoenix Precision, Intel co-establish new-generation flip chip line

06/10/2002  June 10, 2002 - Taipei, Taiwan - Packaging-substrate maker Phoenix Precision Technology Corp. of Taiwan will team up with Intel Corp. to set up an NT$4 billion (US$117.64 million) line to make 3G flip-chip substrates.

BGA, CSP and flip chip

06/01/2002  When to use which process, and why

Special needs of large flip chip being addressed

06/01/2002  ASE Test Limited and MTBSolutions (MTBS) announced that they are jointly developing packaging technology for large flip chip devices

ADVANCED PACKAGING NEWS

05/24/2002  Demmin to Speak at IMAPS Chapter Meeting Tonight
Jeffrey C. Demmin, editor-in-chief of Advanced Packaging magazine, will discuss "The Packaging Landscape -- Business and Technology" today at the IMAPS New England chapter meeting. (June 18)

MEETING REPORT

05/14/2002  Updates on folded flex and thin packaging at ICAPS
RENO, NEV.
The International Microelectronics and Packaging Society held its first International Conference on Advanced Packaging and Systems (ICAPS) in March in Reno. The event featured sessions on most critical areas of advanced packaging technology, including design and test, 3-D packaging, MEMS packaging, and thermal management. Tabletop exhibits accompanied the two parallel technical sessions.

New opto packages announced at OFC

05/01/2002  The Optical Fiber Conference (OFC) in Anaheim in March included announcements of many new packaging technologies and products

The back-end process: Step 5 - Flip chip attach
Process and material options


05/01/2002  Flip chip is a technology where semiconductor devices are mounted and electrically connected face-down directly onto substrates

10th Anniversary Insights
The evolution of the subcontractor


05/01/2002  The role and status of the packaging, assembly and test subcontractor has steadily increased over time

10 years ago in Advanced Packaging

05/01/2002  In the very first issue of Advanced Packaging, thermal management was probably the biggest topic

Updates on folded flex and thin packaging at ICAPS

05/01/2002  IMAPS held its first International Conference on Advanced Packaging and Systems (ICAPS) in March in Reno

IEEE's CPMT announces winners

05/01/2002  Pisctaway, N.J. - The Components, Packaging and Manufacturing Technology Society (CPMT) of the IEEE recently announced the winners of its annual awards for technical excellence, achievement, leadership and service.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

Sponsored By:

Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

Sponsored By:

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