03/01/2000  In the short time I have worked for Advanced Packaging magazine, I have received many phone calls from potential authors who want to write for the magazine. Wonderful! Our best articles tend to come directly from those immersed in the industry, so these inquiries are always welcome. We are always looking for insightful articles that will help our readers better understand this industry - in effect, helping people connect the dots so everyone can excel in their jobs.

03/01/2000  Flip Chip Technologies (FCT) LLC, a joint venture of Kulicke & Soffa Industries and Delphi Delco Electronics Systems, has signed a 10-year technology transfer agreement with Siliconware Precision Industries Co. Ltd. (SPIL). SPIL will use FCT`s proprietary flex-on-cap wafer bumping and redistribution technologies to manufacture advanced flip chip packages at its Taichung, Taiwan, assembly facility.

03/01/2000  Fluoroware has launched the patent-pending JEDEC Style Waffle Pack Tray-in-Tray for chip scale packaging and wafer level packaging applications. This transport and handling solution allows waffle packs of varying pocket sizes to be used in conjunction with a JEDEC-compliant tray during assembly and test, which eliminates the need for tray retooling. The tray-in-tray solution consists of the company`s waffle pack trays, which are placed inside a JEDEC-compliant tray, allowing for interface with e

02/01/2000  Loctite 3567 is an epoxy-based liquid underfill compatible with polyimide-passivated flip chip, CSP and BGA assemblies. The product allows a flip chip to be replaced after testing determines that the chip is defective; packages can be removed by heating the package and the underfill for one minute at 210 to 220∞C, where the epoxy will begin to decompose. The adhesive cures in 5 to 15 minutes when exposed to temperatures of 150 to 165∞C, is easy to dispense and quickly penetrates gaps

02/01/2000  The 3500-II is a fully automatic, high-accuracy die bonder capable of performing automated eutectic die attach using backside metalized die or preforms, and enables bonding of thin die with air bridges using 2 or 4-sided perimeter collets. Using look-up and look-down cameras for flip chip applications and "relative-to" referencing for linear micro-strip line placement, the 3500-II yields accuracies of ±0.5 mil.

02/01/2000  The M-2000 dispensing system is suited for high-volume, production-critical packaging applications, including flip chip underfill, cavity fill, and dam and fill. The product features a DP-3000 series linear pump for increased closed loop control and better than 1 percent, 3 sigma dispensing accuracy. The platform includes mass flow calibration, software-managed temperature control, advanced lighting systems, and operating software for easy set-up and system control.

02/01/2000  During the past few months, there has been a spirit of regeneration throughout the world, as many eagerly anticipated the calendar year rolling over to 2000. Regardless of which stance you took regarding the true start of the third millennium, the result of last New Year`s still tends to be the same: From individuals to entire companies, everyone is talking about doing something new. Many tackled weighty resolutions this year like none other, while others just analyzed how to better accomplish t

02/01/2000  LIBERTYVILLE, ILL. - PennWell, a diversified media company with magazines, trade shows and conferences in more than 40 markets worldwide, has acquired Advanced Packaging and four other magazine titles (SMT, Connector Specifier, Vacuum & Thinfilm and SMT International) from Libertyville, Ill.-based IHS Publishing Group.

02/01/2000  Flip chip underfill is the enabling process for flip chip interconnect survival on printed circuit boards (PCB). Its function: to distribute shear stress normally placed on the solder bumps. Stress is a product of the dissimilar coefficients of thermal expansion between the silicon integrated circuit and the laminate. Also, underfill enables the use of larger flip chip die on ceramic substrates, which historically feature smaller flip chips assembled with only compliant solder bumps to absorb co

01/01/2000  Looking for the perfect package? For the semiconductor manufacturer, selecting the optimal packaging solution can be tough. To make the "right" choice, it is important to comprehend both the technical and business requirements of their product.

01/01/2000  Amicon E 1158 flip chip underfill encapsulant is said to cure in five minutes at 135°C and can sustain more than 3,000 thermal shocks from -55°C to 125°C with no delamination. The product is highly flowable, non-anhydride-based and designed to fill gaps of 50 or more microns. It reportedly exhibits good adhesion to common die passivations.

01/01/2000  Flip chip assembly technology is gaining increased acceptance in the electronics industry. Annual growth rates projected through the next decade are 40 percent or higher. While flip chip technology was developed more than 30 years ago and has been in production on ceramic substrates for decades, it has yet to achieve cost competitiveness with low-cost surface mount technology (SMT). In order to achieve cost competitiveness, new and innovative material systems and process technologies are require

01/01/2000  ME-525 is a high Tg, low CTE, high-purity underfill encapsulant designed for use with small-gap flip chip devices. The product is said to penetrate gaps as small as 2 mils and cure in 30 minutes at 150°C. Easy to dispense and with high chemical and moisture resistance, the product has low viscosity, high flow for capillary chip underfill and is capable of flowing under a 1/4" die in less than 60 seconds.

01/01/2000  The "No Flow-Fluxing" underfill is designed to help manufacturers and assemblers of area-array devices, such as flip chip, CSP and BGA, reduce the overall cost of device assembly. This technology reportedly eliminates separate fluxing, flux cleaning, underfill capillary flow and post-cure operations using underfill in area-array device assembly because the underfill performs the dual role of fluxing the interconnects and curing to become the underfill layer.

01/01/2000  Recently, two distinguished colleagues were presented the First Annual MicroElectronics Packaging Technologist Award for their significant contributions in the advancement of packaging technology. The award was co-sponsored by Advanced Packaging magazine and MEPTEC and was presented at the recent MEPTEC 1999 Symposium in San Jose, California. While you undoubtedly know Advanced Packaging magazine, some readers may not be familiar with MEPTEC - a Silicon Valley organization dedicated to semicondu

01/01/2000  The following is a commentary on the article "Moiré Interferometer: Assist in Electronic Packaging Development," which was published in the September 1999 issue of Advanced Packaging (pp. 44-50).

01/01/2000  The article in your October issue, "True Cost of Outsourcing" by Randie Reed, is written from the perspective of a controller. I have found through my experiences that the "make or buy" decision is a very important one that is often quite complex. This article simplifies the complexity. The true cost of buying outside may be far higher than the production costs, overhead costs and delivery costs. Most companies making a tangible product have to buy some things and make some things. What to make

01/01/2000  Now that we have crossed the millennium threshold, what`s the state of semiconductor chip packaging? Actually, that question has preoccupied the editorial team at Advanced Packaging for the past six months now, and while we may not have the answers yet, we have the mechanisms in place to track both old and new trends that will shape our industry in 2000. Although each issue of Advanced Packaging is set to explore late-breaking technology in a broad sense, the primary editorial focus will remain

01/01/2000  Although wire bond technology continues to dominate the integrated circuit (IC) packaging market from a volume standpoint, over the past few years most of the industry "buzz" has focused on the increasing use of leading-edge packaging techniques, such as chip scale packaging (CSP) and flip chip. Despite that they represent a small portion of the overall packaging volume, most industry analysts have been predicting very rapid growth rates for CSP and flip chip because, ultimately, they represent

01/01/2000  Montara, Calif. - The CSP, BGA and WLP Technology 2000 Report covers all the active U.S. patents relating to these packages, including wafer-level technologies, by summarizing and cross-referencing their characteristics. Suitable for use by companies actively involved in these packaging areas, it is said to be a valuable tool in searching for and understanding the covered ideas.