Wafer Processing

WAFER PROCESSING ARTICLES



OSAT places $3m order for Camtek wafer inspection systems

10/06/2010 

Camtek Ltd. (NASDAQ and TASE: CAMT) received an order for multiple wafer inspection systems from a major outsourced semiconductor assembly and test (OSAT) company in southeast Asia.

Mattson Suprema photoresist strip systems ordered for FEOL and BEOL logic fab

10/06/2010 

Mattson Suprema photoresist strip systems ordered for FEOL and BEOL logic fabMattson Technology Inc. (NASDAQ: MTSN), advanced wafer fab process equipment supplier, received orders for multiple Suprema photoresist strip systems from a new Asian customer. The Supremas will be used in both front-end-of-line (FEOL) and back-end-of-line (BEOL) applications for advanced logic device production.

Camtek enters front-end macro wafer inspection with 2 orders

10/04/2010 

Camtek Ltd. (NASDAQ and TASE: CAMT) received two orders for its, new automatic optical inspection (AOI) system for the front-end semiconductor industry, the Gannet. Front-End Macro Inspection is a new market for Camtek.

Paste print tool uses embedded electronics for finer pitches

10/01/2010 

DEK has launched ProActiv process technology to enable electronics manufacturers to print pastes with high-density heterogeneous PCBs and ultra fine pitch assemblies such as advanced package assembly. DEK has launched ProActiv process technology to enable electronics manufacturers to print pastes with high-density heterogeneous PCBs and ultra fine pitch assemblies such as advanced package assembly.

Cost-effective advanced copper metallization using ECPR

10/01/2010  Electrochemical pattern replication enables fine pitch, >2:1 aspect ratio plating of near vertical sidewall copper metal features without advanced lithography; its uniformity will prove to be very attractive for both front-end of line and back-end of line metallization processes. M. Thompson, P. Möller, M Fredenberg, D. Hays, W. Van den Hoek, D. Carl, Replisaurus, Kista, Sweden

Production metrology of advanced metallization structures using XRR and WA-XRD

10/01/2010  A new interconnect metrology technique enables the monitoring of the thickness and the density of the copper and barrier layers while also obtaining valuable microstructure information in terms of phase, grain-size, and texture. Asaf Kay, Alex Tokar, Jordan Valley Semiconductors, Ltd., Migdal Ha'Emek, Israel; Matthew Wormington, Jordan Valley Semiconductors, Ltd., Austin, TX USA

Keithley semiconductor and package test software update

09/29/2010 

Keithley Instruments ACS Basic test and measurement softwareKeithley Instruments Inc. (NYSE:KEI) updated its ACS Basic Edition Semiconductor Parametric Test Software for semiconductor test and measurement applications. ACS Basic Edition Version 1.2 performs characterization of component or discrete (packaged) semiconductor devices.

Probe cards for combo wireless package test get boost from Cascade Microtech S-Technology

09/29/2010 

Cascade Microtech Inc. (NASDAQ: CSCD), supplier of production probe cards with signal integrity for multi-site die testing, released S-Technology for improved contact physics. S-Technology provides a unique mechanical architecture for Pyramid probe cards designed to consistently deliver evenly distributed contact force for solder bump technologies.Cascade Microtech (NASDAQ: CSCD), supplier of production probe cards with signal integrity for multi-site die testing, released S-Technology, which provides a unique mechanical architecture for Pyramid probe cards to consistently deliver evenly distributed contact force for solder bump technologies in die tests.

IWLPC speaker Mackie will cover low-alpha assembly materials for wafer-level packaging

09/28/2010 

Indium Corporation’s global product manager, Andy C. Mackie, Ph. D., MSc, is presenting at the International Wafer-Level Packaging Conference (IWLPC) October 11-14, 2010 in Santa Clara, CA.

Simple wet cleaning improvements can meet new silicon surface preparation criteria

09/28/2010 

Robert Pagliaro, RP Innovative Engineering Solutions, demonstrates that simple but effective enhancements to wet clean steps can help achieve more stringent surface preparation and reduce complexity, cost of ownership (COO), and environmental concerns associated with existing methods. Contamination left or caused by cleaning and drying steps can adversely affect wafer yields.Robert Pagliaro, RP Innovative Engineering Solutions, demonstrates that simple but effective enhancements to wet clean steps can help achieve more stringent surface preparation and reduce complexity, cost of ownership (COO), and environmental concerns associated with existing methods. Contamination left or caused by cleaning and drying steps can adversely affect wafer yields.

SEMICON Europa lithography session preview with speakers

09/27/2010 

In a series of podcasts, 3 of the presenters at the SEMICON Europa Lithography session speak with senior technical editor Debra Vogler. Interviewees include consultant Wolfgang Arden, Rolf Seltmann of Globalfoundries, and IMEC's Roel Gronheid.

LVx voltage imaging and probing tech debuts, gains 10 orders

09/24/2010 

DCG Systems sees strong adoption in the design debug and failure analysis market for the LVx capabilities, which include continuous wave laser voltage probing (CW-LVP) and laser voltage imaging (LVI) through a combination of hardware and software.

Thin wafer handling: Analysis of wafer-support tooling for stencil-print coating of thinned wafers

09/20/2010 

Jeff Schake, et al, DEK Printing Machines, discuss the flatness characteristics of available wafer pallets, and use them in an experiment with thinned wafers in automated printing. With thin wafers, and the requirement for low coating thickness, the wafer-support tooling surface metrology should have an appreciable impact on coating thickness control.Jeff Schake, et al, DEK Printing Machines, discuss the flatness characteristics of available wafer pallets, and use them in an experiment with thinned wafers in automated printing. With thin wafers, and the requirement for low coating thickness, the wafer-support tooling surface metrology should have an appreciable impact on coating thickness control.

Proteus Biomed chooses IC test house Integra for new designs

09/20/2010 

Integra Technologies, IC test and evaluation services provider, was selected by Proteus Biomedical for development and production test of their new integrated circuit (IC) designs for future medical electronics products.

NCCAVS CMPUG: Trends and technologies for CMP in hard-disk drives

09/17/2010 

Techcet's Michael A. Fury reports from SEMI's NCCAVS CMP Users Group meeting in San Jose, CA. Highlights included a market growth overview, and talks ranging from market growth to consumables challenges to new technologies for chromatography, noncontact probe, 3D topography, polishing, and HDD substrate slurry.

TSV wafer measurement tool selected by 2 semiconductor equipment makers

09/16/2010 

Tamar Technology received orders from major semiconductor equipment manufacturers for its TSV measurement technology. Tamar’s proprietary Wafer Thickness Sensor can measure etch depth for TSVs as well as wafer thickness for single or bonded wafers.

STATS ChipPAC opens 300mm embedded WLP BGA (eWLB) manufacturing fab

09/15/2010 

STATS ChipPAC Ltd. opened a new 300mm embedded Wafer-Level Ball Grid Array (eWLB) manufacturing facility, switching over from 200mm technology. The official inauguration was held at STATS ChipPAC's Yishun facility in Singapore with more than 150 local dignitaries, customer representatives, business partners and management participating.

FormFactor drops Singapore manufacturing, keeps Japan and CA

09/14/2010 

FormFactor Inc. (NASDAQ: FORM) is ceasing its transition of manufacturing operations to Singapore. The wafer probe company's decision will result in a reduction of approximately 70 employees at its Singapore facility. Manufacturing that was planned for Singapore will stay in Livermore, CA.

ON Semi wafer fab gets $15.78m expansion: Belgium 150mm fab will grow 40%

09/10/2010 

ON Semiconductor's 6" (150mm) wafer manufacturing facility in Oudenaarde, Belgium specializes in application specific high-voltage technologies for the automotive and industrial industry, and integrated and discrete standard products for a wide range of market segments.

Low-k dielectric family introduced by SBA Materials

09/07/2010 

The IC community has been searching for a manufacturable low-k dielectric which could scale to below K = 2.0, says Dr. Phil Garrou. Microindent photos of uLK 124, released by SBA Materials show a clean ductile indent. SBA reports that their uLK materials can be integrated into existing fab lines using equipment and process flows already in place.The IC community has been searching for a manufacturable low-k dielectric which could scale to below K = 2.0, says Dr. Phil Garrou. Microindent photos of uLK 124, released by SBA Materials show a clean ductile indent. SBA reports that their uLK materials can be integrated into existing fab lines using equipment and process flows already in place.




WEBCASTS



Environment, Safety & Health

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The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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