Wafer Processing

WAFER PROCESSING ARTICLES



Improving etch performance using in situ gas flow monitoring and control

07/01/2010  Improve etch equipment performance through in situ gas flow monitoring and control. Mukund Venkatesh, et al, Pivotal Systems; Kevin Boyd, IBM.

Holistic substrate inspection for defects at the 32nm node and beyond

07/01/2010  A holistic strategy can help to find and correct process-induced defects. Philippe Gastaldo, Altatech Semiconductor S.A.

Nanoporous silicon for diagnostics

06/30/2010 

Proteomics is important for drug discovery, vaccine development, and drug manufacturing, but prevalent methods require fluorescent labeling and 2D evaluation through electrophoresis or mass spectrometry. Hus Tigli, CEO of Silicon Kinetics, shared an alternative approach that leverages nanotechnology at the San Francisco Bay Area IEEE Nanotechnology's Sixth Annual Symposium.

Highlights from the 2010 ECTC

06/15/2010 

At the Electronic Components & Technology  Conference (ECTC)  this month in Las Vegas the CPMT (Components, Packaging and Manufacturing Technology) Society of IEEE bought out their long time partners ECA (formerly EIA). Other news: STATSChipPAC expanded its presence in eWLB, copper-copper bonding in 3D was reviewed, and Doublecheck Semiconductors, working with Disco and the Fraunhoffer IZM claims to have developed technology that enables standard silicon wafers to be thinned down to less than 100µm.

IITC Day 3: Sub-30nm SoG gapfill, 22nm airgaps...and enforcing Zafiropoulo's Law

06/15/2010 

Techcet's Michael A. Fury concludes his observations from this year's IEEE International Interconnect Technology Conference (IITC) meeting near San Francisco. From Day 3: Intel's airgaps for 32-22nm, Si nanowires, more on 3D bonding and TSV schemes, electromigration in Au nano-junctions -- and enforcing "Zafiropoulo's Law."

Analysts' take: Samsung incites "foundry wars" with 32nm HKMG volley

06/14/2010 

Samsung's announcement that it has completed testing of its 32nm high-k/metal gate architecture, ramping to volume possibly by year's end -- and following quickly with a 28nm version -- has the industry buzzing about a possible reshaping of leading-edge semiconductor foundry manufacturing.

450mm wafers: More at stake than just a new wafer size

06/04/2010 

The ongoing debate over the next wafer-size transition to 450mm, with discussions about pros and cons in costs and technology gains, misses the point -- it's the message we send about the semiconductor industry's mindset and future, argues Semico's Joanne Itow.

Demand for chip tools, wafers still strong

05/24/2010 

New data from North America and Japan points to still growing demand for suppliers of semiconductor makers.

ConFab video: Consensus, collab are key to industry progress

05/20/2010 

SEMATECH's Dan Armbrust underscores the need to determine up-front what areas are truly important to keep pushing scaling and cost-effectiveness in the semiconductor industry.

Getting costs out, standards in for high-volume TSS

05/20/2010 

High-density through-silicon stacking (TSS) shows promise for very high-volume applications, but work still needs to be done to "tame" key issues in manufacturing, improve costs, and smooth out the supply-chain, said Matt Nowak, director of engineering in Qualcomm's VLSI technology group, in a presentation at The ConFab in Las Vegas.

SEMATECH outlines maskless issues, proposes consortium

05/17/2010 

Among key takeaways from SEMATECH's Litho Forum last week in NYC was a proposal to create a consortium to support multibeam mask writing efforts, similar to what's being done for EUV.

Sonoscan demos MEMS cavity seal integrity inspection

05/13/2010 

Defects most frequently take the form of voids within the MEMS cavity seal. In some locations on a wafer, the seal may be breached.

TSMC approves $1.6B for new fabs, upgrades

05/11/2010 

Chip foundry giant Taiwan Semiconductor Manufacturing Co. (TSMC) has greenlighted investments in fab infrastructure, including a new 300mm gigafab -- but there may not be any immediate capex adjustment for it, and that may be a good thing.

Asys plucks DynTest for LED singulation tech

05/10/2010 

The Asys Group say it has acquired the IP and patents of fellow German firm DynTest Technologies, seeking to apply the company's wafer singulation technology to high-brightness LEDs.

Combinatorial tooling for cost-effective, efficient ALD

05/06/2010 

Researchers from Intermolecular describe an atomic-layer deposition (ALD) process development chamber that allows multiple site-isolated depositions on different quadrants of a 300mm wafer, with data from a case study of ZrO2 film development.

Improving 22nm design space with source/design optimization

05/04/2010 

Execs from Texas Instruments and Luminescent Technologies describe a "source/design optimization" technique that blends source/mask optimization (SMO) techniques with design rules, and realizes significant improvements in overall die area.

MHI ships first 200mm MEMS bonder

04/21/2010 

Mitsubishi Heavy Industries says it has delivered its first automated room-temperature bonding system for 200mm wafers for production use, to a MEMS manufacturer in Japan.

MRS Day 4: TSVs and CMOS+MEMS, wafer bonding, CNT interfaces, ALD for rare-earth HK, graphene redux

04/19/2010 

Highlights from Day 4 of the 2010 MRS Spring meeting, reported by Techcet's Michael A. Fury: TSVs and flexible interconnects for 3D CMOS/MEMS; 300mm BCB wafer bonding; carbon nanotube interfaces for interconnects and vias; phase-change memory devices; interfaces during ALD of rare earth-based high-k dielectrics; and graphene's use in on-chip interconnects and transparent conductor electrodes.

Singapore launches MEMS consortium

04/09/2010 

A group of eight global companies, supported by local research and government, have formed a consortium to facilitate and grow Singapore's expertise in microelectromechanical systems (MEMS).

Analyst: Why TSMC will stay tops in 40nm

04/05/2010 

Updating outlooks for foundry rivals TSMC and UMC, FBR Research analyst Mehdi Hosseini suggests that business will stay brisk through year's end -- and that the leading-edge horizon is clear of trouble for the top foundry.




WEBCASTS



Environment, Safety & Health

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The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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