Monthly Archives: September 2004

EAST HILLS, N.Y.—A series of protein purification kits has been unveiled by Pall Corp. (www.pall.com) to aid proteomic researchers in the development of new drug therapies. The kits are designed to remove unwanted abundant proteins from human and animal-derived serum and plasma samples, helping researchers to unmask low abundant, low molecular weight protein biomarkers that offer hope for new drug discoveries, as well as the diagnosis, treatment and prevention of diseases.

Proteomics is the large-scale study of proteins, their structures, functions, and particularly their interactions with genes in forming other proteins—a key to unlocking discovery of new drug treatments and illness diagnosis/ prevention. The demand for proteomic-based technologies is increasing (the market is expected to reach $3.3 billion by 2006) as scientists seek all-inclusive sample preparation kits to speed their work in protein analyses and drug discoveries.


Pall Corp.’s recently introduced protein purification kits are designed to offer biomedical researchers an all-inclusive sample preparation to help speed their work in protein analyses and drug discovery.
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Albumin and immunoglobulin G (igG) make up approximately 80 percent of the total protein content in human serum, necessitating a technology to deplete these abundant proteins so that critical protein analysis can be made. Pall's Enchant Life

Sciences Kit for Ablumin Depletion and two for igG purification are designed to provide researchers with needed protocol, purification columns and buffers for protein analysis. The albumin kit helps remove the abundant protein from samples in five steps that Pall says take about 10 minutes to complete. (The kit also includes a platform that eliminates the need to handle and pipette slurries.)

The two immunoglobulin G kits feature Protein A and Protein G affinity resins—bacterial cell wall proteins that have specificity to the igG antibody and that provide purification/removal of igG in serum samples. The need to isolate igG from a serum sample is critical given the propensity of small proteins to be masked by the abundant protein. The igG purification kits, which can be used for purifying a variety of immunoglobulin molecules and isotypes, are reusable, gravity-based columns designed to offer high binding capacities for effective purification or depletion.

“We plan on launching additional purification kits that selectively target the unique, low-abundant proteins that researchers want to isolate,” says Pall BioSciences President Ken Harris.

BY HANK HOGAN

Indianapolis, Ind.—Lonny Wolgemuth, medical market manager for Specialty Coating Systems (www.scscookson.com), cites the movie Field of Dreams when he talks about his company's recently finished 1,700 square-foot cleanroom. The facility features a concentric layout, with an ISO Class 7 area enclosing an ISO Class 6 ring that surrounds a final ISO Class 5 core. It's a cleanroom, complete with controlled entrances, gowning areas, HEPA filters, and pressure differentials.

Wolgemuth likens the new facility, the most state-of-the-art of SCS' four cleanrooms, to the baseball field in the film. If the facility was built, the customers would come. Unlike the baseball field in the movie, however, this cleanroom is intended for parylene coating services and has more behind its construction than a whisper that only a few can hear.

“We saw the need to more precisely control the environment in which these fine wire geometry devices would be coated,” says Wolgemuth. “So, in order to provide the control that we felt necessary to exceed the customer's expectations, we needed to have this particular facility.”

Driven by miniaturization?

SCS is already coating customers' products in its new cleanroom. The move toward cleanrooms and contamination-controlled environments is something those in the parylene coating industry see as inevitable due to ongoing miniaturization, particularly of medical devices and hybrid electronics. But there's disagreement about the timing.

“Do I think there is a trend towards smaller and smaller circuitry, miniaturization of this technology that's going to drive parylene coaters toward cleanroom environments? Yes, I think there is some of that, but I think that we're not being driven to that by the end user at this point,” says Bill Gleason, general manager of Para Tech Coating Inc. (Aliso Viejo, Calif.; www.parylene.com).

The Para Tech facility is an ISO Class 8 cleanroom, with some specialized laminar flow hood areas within it that are ISO Class 7. The company also takes steps to control contamination during surface cleaning through the circulation and filtering of an aqueous-based cleaning solution used to prep parts before deposition. Care is also taken during other processing and masking steps to minimize the addition of contaminants to products being coated.

SCS, Para Tech and others make and sell coater systems. The companies also provide parylene coating services. The technology involves depositing layers of parylene that range in thickness from tens or hundreds of angstroms, or fractions of a micron (µm), all the way up to 25 µm—or about a thousandth of an inch. The thickness of the deposited layer is determined by the applications, which include hybrid electronics, implantable medical devices such as pacemakers and stents, and microelectricalmechanical systems (MEMS).

In the medical field, parylene is sometimes used to serve as a bridge material. For example, a parylene coating may offer a way to create a drug-eluting stent, which combines a structure—often made of some kind of metal—with a measured drug release mechanism. The structure props open arteries while the drug prevents clogs and other problems. The drug delivery method can involve materials that don't bond well to metal. So, an intermediate layer, such as parylene, may be required to bridge the two dissimilar materials.

Drug-eluting stents can be tricky to manufacture but are proving popular nonetheless. According to Kalorama Information, a publishing division of MarketResearch.com, the market in the United States for drug-eluting stents was $683 million in 2003 and is forecast to grow to $1.23 billion by 2008 (see Figure 1). It's partly because of this surge in sales that medical device coatings are generating additional interest.


Figure 1: Forecast of U.S. market for drug-eluting stents (2001?2010)
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Parylene is also used in medical devices because it's biocompatible and thus protects devices from the body—and vice versa. For that reason, parylene may be found in various implants, such as pacemakers.

“We use parylene coating at times, but only on an as-needed basis with patients who for some reason cannot tolerate the standard titanium shield,” says Scott Papillon, a spokesman for implantable medical device maker Medtronic Inc. (Minneapolis, Minn.; www.medtronic.com). The use of such a coating, he adds, is fairly rare.

Papillon notes, however, that implantable devices are shrinking in size. Implantable cardioverter defibrillators, for example, were more than 100 cubic centimeters when they were introduced in the mid-1990s. Five years ago, Medtronic's products were about 50 cubic centimeters. Today, the company's latest offerings come in at about 36 cubic centimeters. Pacemakers haven't gone through as drastic a volume reduction, but they, too, have slimmed down over the years.

As a result, device dimensions are smaller and associated coating challenges bigger.

Uniformity matters

The need to uniformly coat small structures is another reason why parylene and other conformal coatings are increasingly used. The parylene deposition process begins when a powder is sublimated under vacuum. The resulting vapor is then converted into individual units (monomers) thanks to a 680°C vacuum treatment. In the next step of the process, the monomer accumulates one molecule at a time on surfaces in the deposition chamber, which is at room temperature and a moderate vacuum. Thanks to the nature of the process, the resulting parylene polymer build-up doesn't discriminate in its deposition.

“I've casually referred to parylene as an equal opportunity coating,” says SCS' Wolgemuth. “That is to say, it coats all surfaces equally. Unless you actively mask something to keep the parylene off, it will be coated.”

Thus, parylene coating will handle deep holes and tall structures. There's no need to worry about voids appearing in the film due to gravity and related effects. On the other hand, the process is slower than a simple dip in a liquid. Such a dousing can take a few seconds. Wolgemuth estimates that putting down a parylene layer can take several hours, with the actual time dependent on the layer thickness. If film uniformity is important, however, Wolgemuth says the wait will be worthwhile.

According to Wolgemuth, SCS has developed a parylene coating that can withstand temperatures as high as 450°C in the short term and 350°C for long-term applications. That's in contrast with other forms of the coating, which typically have problems when much above 100°C.

Being able to survive an elevated temperature is important in implantable medical devices, which have to be sterilized before going into a patient.

As for other contamination concerns, SCS contends there's a need to make sure that the various masking and processing steps taken before deposition don't generate particulate and other problems that can be trapped by the parylene film. That's one reason why SCS has pursued a cleanroom approach. Much of the fixturing of a product to be coated in the new cleanroom will be done in the ISO Class 5 and 6 areas.

But some in the industry say that parylene's ability to produce a conformal film actually works somewhat against this cleanroom need. As Para Tech's Gleason notes, it only takes a thin polymer layer to trap any particles. Those particles are then encapsulated and effectively rendered harmless.

Thus, Gleason points out, depositing a film after system maintenance ensures that any contaminants left over from the cleaning process can't come into contact with product during subsequent deposition cycles. That's one reason he doesn't see a big need at present to surround parylene deposition systems with high-quality cleanrooms. Such precautionary coatings along with the use of a vacuum, Gleason contends, mean that the chamber “… is very, very clean.”

BY CHRIS ANDERSON

FREMONT, Calif.—For years, engineers at SensArray (www.sensarray.com), a maker of process optimization tools for the semiconductor industry, heard from their customers how much they wanted a wireless temperature measuring device that could run within a lithotrack to measure the real-time temperatures of the hotplates and heating elements—without having to manually access the wafer.

The wait is over. In July, SensArray released its Integrated Wafer wireless temperature metrology system, a robotic analysis product that reduces contamination-control risks, could impact the way process managers collect critical data from their lithotracks, and impact how planned maintenance of fab production machines is managed.

Integrated Wafer is designed with a temperature metrology system within the wafer, gathering data through the entire semiconductor manufacturing process without disruption. It provides static and dynamic temperature measurement for critical processes for routine monitoring, assessing the effect of robotic positioning on temperature, diagnosing thermal problems, detecting variations in temperatures between brake plates, and quantifying the role of air-cooling and ventilation mechanisms.

“This technology allows users to gather [temperature] data without ever having to open up the equipment chambers,” says SensArray spokesperson Heather Reed.


SensArray’s Integrated Wafer technology with 0.5-mm profile enables fab technicians to gather static and dynamic temperature data during production surveys that range from 15 degrees C to 145 degrees C, without equipment modification or production disruption, thereby greatly reducing risk of contamination.
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Before the Integrated Wafer technology, Reed explains, “each time users opened them [chambers], they risked wafer contamination. They also had to run a clean cycle after removing the wire measurement wafers. With this product, none of that is required.”

The development of the Integrated Wafer took nearly two years, incorporating disparate technologies. The patented design is less than 0.5-mm thick, with the temperature sensors, power source and data collection system embedded in either a 300-mm or 200-mm silicon wafer.

Integrated Wafer produces a thermal mass and dynamic response equivalent to that of a product wafer. The 0.5-mm profile enables users to gather static and dynamic temperature data during production surveys that range from 15° C to 145° C, without equipment modification or production disruption.

“What we had before is a just a wafer that was thermal coupled,” says Earl Jensen, who heads the Integrated Wafer development team. “The problem is if you have 29 sensors you'd have more than 60 wires coming out of the thing.”

That meant in order to use the old measurement equipment, the track would need to be taken off line, the machine opened up, and the wafer placed on the hot plate. “Then they [engineers] would put the skins back on and wait half an hour to stabilize and get 'back to normal' to make the measurements, then reverse the whole thing and take it all apart again,” Jensen notes. “So, to do a quick measurement was an hour or two minimum, and could take as much as a half day.”

SensArray says the Integrated Wafer is deployed robotically from a base station that provides for communications and battery charging. The base station for the 300-mm version is built into a FOUP, and the 200-mm base station is located within a standard wafer cassette. Once the survey process is complete, the base station manages the downloading and communication of wafer data.

Being able to collect data without shutting the production track down is critical, SensArray claims, not just for clean productivity and the money saved by keeping the equipment running, but for being able to collect temperature information that reflects actual operating conditions during production rather than the simple snapshot that was provided from older metrology methods.

Now, where a planned maintenance measurement might once have occurred every couple of weeks with the old measurement system, manufacturers can collect temperature data on their lithotrack when they wish.

“We have heard from some customers that they are running the Integrated Wafer through every day and some are even doing it once per shift,” says Reed.

Because the Integrated Wafer is a silicon wafer with the instrumentation machined into the surface, it has comparable heating properties as the other wafers moving through production and can give manufacturers a clear view of how each of the hotplates within the track is heating the wafers. But creating a wireless product that carries a power source, sensors and microprocessors, all capable of withstanding temperatures of up to 150° C, involved numerous design challenges.

Jensen and his team sourced technologies that were being used for disparate applications ranging from reading and transmitting tire pressure in real time, to processors that required extremely low power consumption. “We took the parts that we needed and used them out of context,” Jensen says. “And we also had to take these parts beyond their spec limits, since they would need to perform at high temperatures.”

For the power source, Jensen chose an ultra-thin battery that was developed to power a tire pressure sensor for automobiles and transmit warnings if the pressure falls outside a predetermined range. “We thought this battery would be good since it was designed to be inside the tire, and tires get hot when they are used,” Jensen says. But the battery also needed to be thin, and this one—at just 10 mils thick—fit the bill.

Also important were processors that could both take the heat and use very little power. For this, SensArray turned to Texas Instruments and processor technology it developed in the 1970s but shelved. “There wasn't a need for a low-power application back then, but now it is a growing market for them with handheld devices,” he says.

The 300-mm Integrated Wafer has 64 temperature sensors and the 200-mm size has 52 sensors; data from the wafer is compatible with SensArray's Thermal MAP Analysis software. In all, the company claims the Integrated Wafer can provide comprehensive temperature surveys lasting as long as 20 minutes and collecting up to 52 KB of data before needing to be recharged or have the data downloaded.

The company plans to introduce similar products for stepper, prober and etch processes. Reed says the company hopes to have beta sites set up for a prober version during the fourth quarter of this year.

SensArray also has its sights set on collecting more than just temperature data. “Temperature is just the most commonly measured thing, but it is not the only thing we can measure,” says Jensen. “There is humidity and how much the wafer is tilting, calibration and wafer handling—the list is endless and will be expanded as customers decide that there is a need for measuring other parameters.”

New Products


September 1, 2004

Hybrid Module Assembly System

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APS 1-H is a versatile hybrid module assembly system that combines a solid foundation and advanced technology to handle complex hybrid assembly at high throughput rates. The solid foundation enables the system to attain ±0.0005″ (0.012 mm) 3-sigma placement repeatability. It also meets hybrid module production challenges with highly repeatable performance and configuration flexibility. To complement its accuracy, the hybrid module assembly system supports various die presentation formats, including wafer, gel-pak, surftape and waffle packs. It features a large, flexible tabletop that accepts up to 108 2-in. waffle packs or a custom configuration to meet unique application requirements. The system provides multiple methods for component alignment and upward vision. Components are optically aligned during travel from pick-up to placement, maximizing throughput and utilization. The upward vision system provides a secondary means to align devices such as flip chips, BGAs and QFPs. Tyco Electronics Automation Group, Willow Grove, Pa., www.tycoelectronics.com.

Multichip Die Bonder

Model 4501 is the most flexible and versatile die bonder on the market. Starting with a 25 × 6″ die bond placement area, the system offers numerous technologies in one chassis, including epoxy-stamping, two reservoirs; epoxy-dispensing; eutectic die bonding with fully programmable oven; dual magnification optics; auto changer for stamping and pick-up tools (18 different tools possible); auto changer for wafer/waffle/gel-pak (up to 200 different die in the chassis); flip chip; look-up camera; and tape-and-reel. This material flexibility combines with the linear motor control design to offer a high-speed, accurate (±5 µm) die bonder capable of handling 6-mil-square die down to 15-µm thicknesses. F&K Delvotec, Foothill Ranch, Calif., www.fkdelvotecusa.com.

Advanced Packaging Dispense System

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DispenseJet DJ-9000 is fast, easy to clean and delivers capabilities for advanced packaging. The dispenser jets underfill, silver epoxy, UV-cure adhesives, encapsulants and conformal coatings. Ideal for stacked-die and densely packed boards, the system jets in spaces as tight as 200 µm. Small underfill fillets, wet-out areas, dot diameters and shot volumes are achieved with the new jet. Jetting overcomes limitations of needle dispensing to deliver the following benefits: speed — high flow rates up to 50 mg/sec; high shot rate up to 200 dots per second; no Z-axis motion; jets “on the fly” with no stopping between dots; less height sensing; and no needle backtracking to prevent fluid stringing. Quality — high accuracy; smaller wet-out areas; round, uniform dots; and improved line quality. Low cost-of-ownership — small, wetted path means less fluid waste; cleaning in 10 min. without tools; reasonably priced consumable parts; no under-board support required; and one jet handles multiple fluid types. Asymtek, Carlsbad, Calif., www.asymtek.com.

Mass Imaging Technologies

This company's mass imaging technologies allow virtually any semiconductor packaging material typically deposited by a dedicated dispensing system to be imaged using a screen printing platform. Advantages to this technology include faster throughput compared to dispensing; reduced factory floor space; better control of material deposition; lower control of material usage; and more. Notable innovations have addressed the needs for precise alignment of singulated substrates within a carrier, and the challenge of depositing materials onto partially populated substrates: New edge referenced virtual panel tooling (ERVPT) independently aligns any number of singulated substrates before lifting to the printing position, effectively panelizing the substrates with speed and precision; PumpPrinting stencils and ProFlow technology solve the challenge of partially populated substrates and material management, and the stencil underside can be CNC-machined to clear obstructions without impairing process control or repeatability. DEK International GmbH, Zurich, Switzerland, www.dek.com.

Flip Chip Capillary Underfill

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Hysol FP4547FC is the first capillary flip chip underfill designed to be compatible with clean and no-clean flux residues. This underfill protects lead-free flip chip devices, and allows them to meet JEDEC Level 3/260°C moisture test requirements. By incorporating two patented additives that remove and neutralize flux residues from between the flip chip die and substrate, the material delivers results on high-performance assemblies. This underfill meets the new JEDEC requirements for lead-free flip chip assembly, while providing good thermal cycle performance and simplifying the assembly process. In most cases, post-assembly flip chip cleaning processes may be eliminated, saving manufacturing time and capital resources. Ideal for OEMs and subcontractors assembling lead-free flip chip packages, the underfill is qualified on build-up laminate flip chip packages at JEDEC L3/260°C and on ceramic flip chip packages at JEDEC L1/260°C. Henkel Corp., Industry, Calif., www.loctite.com.

Assembly Workcell

Newport MRSI-605 AP is an ultra-precise, high-speed assembly workcell for epoxy die attach, eutectic bonding and flip chip. Closed-loop force control enables the handling of delicate components such as GaAs die. Linear motors with glass-scale encoder feedback provide high precision. One throughput improvement offered by the system is a six-tool turret for automatic tool on-the-fly changes. Each tool features closed-loop, independent force control and rotates over a full 360°, valuable for high-power RF applications. Some machine features include 10-µm placement accuracy, epoxy stamping, two dispense pumps, eutectic bonding and direct pick from multiple wafers. The workcell can be configured for standalone production, cassette-to-cassette material handling or in-line with other process equipment. Ease of use is a major advantage due to the Windows software with an intuitive design that reduces operator training and improves programming efficiencies. The software is complemented by the advanced vision system that can locate and align complex die over a 360°. Newport, Corp., North Billerica, Mass., www.newport.com.

High-performance Reflow Oven

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ELECTROVERT OmniExcel 7 is a high-performance reflow oven that delivers reflow and curing processes while focusing on reduced lifecycle costs. An innovative chamber design ensures uniform heat transfer, zone-to-zone segregation and up to 50% reduction in energy consumption. The combination of heat on intake and closed-loop blower control ensures a stable environment for various production requirements or product mass. Nitrogen consumption is reduced by 30 to 40% by balancing airflow patterns within the full system and the integration of curtain modules to control incoming air. The system also meets numerous processing needs including curing, lead-free and hybrid package processing. It also can be configured with 7 or 10 heating zones. With a 24″ process width, it is capable of handling large boards and pallets. Speedline Technologies, Franklin, Mass., www.speedline.com.

Wafer Bumping Paste

SE-CURE 7501 paste is formulated for in-situ stencil wafer bumping applications, and provides superior printing performance in the bumping process, even with bump pitches below 125 µm. The paste features a viscosity that remains stable over a minimum of a manufacturing shift, providing a stable and consistent printing operation. Removal of all organic residues or cleanliness is vital to the performance and acceptance within the semiconductor packaging industry. The bumping paste was engineered to be a drop-in solution with all the other process modules of the patented bumping process such that further current chemicals would not be modified or changed. The paste is available with Sn/Pb, and optimized formulations are available for lead-free and other solder alloys. Kester Inc., Des Plaines, Ill., www.kester.com.

Lead-free Kit

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SlimKIC 2000 Lead-free Kit handles the higher process temperatures required by lead-free assemblies. The kit includes a stainless steel thermal barrier that offers heat protection up to 350°C and medium-temperature thermocouples rated up to 400°C. The kit's optional KIC Auto-Focus provides the best “first guess” and automatic optimized oven setup for lead-free applications. There is no product wastage from improper formulas and product yields are greater. The user-friendly software uses patent-protected technology to automate most of the time-consuming tasks associated with profiling. It also maintains a library of hundreds of the most popular solder pastes and adhesives to quickly define the appropriate process window. The powerful user interface guides the operator through the profiling process, minimizing the potential for improper oven setup and yield-reducing defects. KIC, San Diego, Calif., www.kicthermal.com.

In-line AOI System

The high-speed AutoInspector Series Ultra II identifies assembly defects on PCBs and enables in-line process control. Inspections include paste, pre-solder, and post-solder SMT and mixed-technology boards as well as solder balls on BGAs, wafer bumps and substrates. The inspector is a true multi-application platform and can be deployed anywhere in the assembly process, from post-print to post-wave inspection. With the company's quad-angle lighting, no hardware adjustments are necessary when changing the inspection application. These SMEMA-compatible inspection systems can be operated in- or off-line. To save time and for ease of use, the programs can be done 90% off-line. Programs can be transferred with no additional tuning requirements. A solid unibody frame, three-point-suspension design, ultra-high precision linear stage, quad speed digital cameras and high-resolution optics provide a copy-exact hardware platform that offers maximum program transferability and maximum equipment reliability. Comprehensive off-line tools enable centralized engineering support and multi-part program rollout. Machine Vision Products (MVP), Carlsbad, Calif., www.machinevisionpro.com.

All-temperature Cleaner

AQUANOX A4520 is for enhanced cleaning of a spectrum of pastes, fluxes and uncured adhesives used in the electronics and semiconductor industries, and featuers low VOC. The cleaner has less waste and emmisions than other cleaning products, and has proven effective on cleaning more than 95% of lead-free pastes. The low-foaming concentrated cleaner is effective at temperatures ranging from ambient to 160°F for removal of no-clean, rosin, tacky, and lead-free flux, pastes and uncured adhesives via spray, immersion or manual applications. The cleaner offers greater than 50% throughput increases for lead-free and no-clean materials. Because the material operates at lower temperatures and concentrations, fewer chemicals are used. For spray applications, the product will work in a concentration range of 5 to 30% diluted with de-ionized water. Kyzen Corp., Nashville, Tenn., www.kyzen.com.

Dual-row Quad Leadless Package

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QLP-DR is a low-cost, leadframe-based, near chip scale package that offers good electrical and thermal performance for wireless applications. The significance of the package is in the leadframe design that features two rows of staggered I/O terminal pads with an exposed die pad for die grounding and improved thermal performance. The package provides the advantages of a single row quad flat no-lead (QFN) package, including performance, reliability and manufacturability, with the added benefit of up to 50% more I/O terminal pads for the same body size. By using the same materials set and manufacturing process as a standard quad leadless package, QLP-DR offers a high-performance solution with high yield and reliability at a lower cost than many laminate- or tape substrate-based chip scale packages and wafer-level chip scale packages. STATS, Boise, Idaho, www.statsus.com.

Digital X-ray System

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Dage XD6600 offers magnification of up to 5,800X and acquires images with a resolution of 1,300 × 1,000 pixels and more than 65,000 levels of grayscale over the 16 × 18″ inspection area. An improvement over existing technology with >4× the number of pixels and 4× the grayscale level, the X-ray system inspects and analyzes larger images at increased levels of detail of the subtle grayscale differences needed for quality control. Inspection analysis is controlled by the ImageWizard, Rev10, which is an easy-to-use and intuitive operating software system enabling procedures to be taught simply, and providing the user with more time for analysis without effecting throughput. The inspection system comes standard with the following: A 19″ digital LCD monitor providing a large and clear field of view; <600nm minimum feature recognition; oblique angle view from 0° to 45° for any view 360° around any position over the inspection area; and up to 5,450X magnification (1,400×, geometric). Dage Precision Industries, Fremont, Calif., www.dageinc.com.

Leadframe-based Technology

AmKard is the first fully molded, leadframe-based multimedia card technology, extendable to other memory card standards including SD, RS-MMC, miniSD, MemoryStick/DUO, xD, etc. Compared to existing lidded laminate packaging technology, AmKard's overmolded die assembly of multiple components reduces the cost of memory cards up to 50%. The leadframe integrates die pads, seven-pin connector and internal connectivity, eliminating the need for higher cost laminate substrates. Connector integration is achieved through a combination of half-etching and reverse downset technology, which also enables die stacking. The fully molded leadframe fits into existing leadframe manufacturing infrastructure because of design simplicity. Memory capacity expansion can be supported without changes to the leadframe design using die stacking. Amkor Technology, Chandler, Ariz., www.amkor.com.

Shieldless High-speed Connector

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AirMax VS connector system is for use in the design of high-speed computing and network systems, from 2.5 to 6.25 Gb/s with built-in scalability to greater than 12 Gb/s. Using air as a dielectric, the design eliminates the requirement for interleaving shields to significantly reduce size, weight and cost over alternative connector systems. The connector is a scaleable, inverse two-piece backplane connector system with a common insert molded leadframe assembly (IMLA) for both differential pair signal and single-ended signal designs. Options for both connections are provided in the same IMLA. The system allows for mix-and-match IMLAs or signals within an IMLA, which reduces cost by providing the flexibility to stock and use the same connector for various design options rather than requiring distinct parts for separate design projects. FCI Electronics, Etters, Pa., www.fciconnect.com.

Solderable Polymer Thick Film

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PI-1000 Solderable Polymer Thick Film is a screen printable, directly solderable conductor, designed to reduce manufacturing time and improve electrical and thermal performance of circuit interconnects vs. existing polymer thick films. The formulation develops true, robust metallurgical joints. Instead of relying on passive point-to-point contact, its active combination of continuous micro-soldered metallic chains and interfaces is interwoven with a tough, thermosetting polymer, yielding high electrical, thermal and mechanical stability. The thick film can be screen printed or dispensed; the cured material requires no etching or post-bake. A new additive manufacturing process allows rapid cycle times, with no toxic wet chemicals and virtually no unusable waste. The technique eliminates typical copper-bearing acidic by-products generated during conventional subtractive manufacturing. By replacing the copper-etch technique with direct printing of a solderable interconnect, the simplified process helps lower capital equipment costs and improve throughput in PCB fabrication. Dow Corning Corp., Midland, Mich., www.dowcorning.com.

Aluminum Substrate Material

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Giving automotive lighting system designers a lighter, cooler and less expensive method of mounting visible LEDs, this company developed Anotherm substrate, an economical anodized aluminum substrate material with high thermal conductivity. High-power LEDs and other components can mount directly onto the thermally-conductive aluminum alloy material so that the heat produced by the LED is conducted away from the circuitry, thus eliminating the need for attached heatsinks. In effect, the PCB becomes the heatsink, which lowers assembly and material costs by eliminating external heatsinks, mounting clips and other hardware. Solderable thick film conductors can be screen-printed directly to the substrate to connect surface mount packaged components or wire-bonded die. Its rugged construction gives the substrate material the ability to operate in temperatures up to 400°C, or up to 175°C, using high-temperature solder. TT electronics IRC Advanced Film Division, Corpus Christi, Texas, www.irctt.com.

Off-line Device Programmer

The 4700 is designed for high-density devices and longer programming times, including Flash. It achieves this by combining 64 Mb in 15 sec. with the company's FX4socket modules. FX4 socket modules program up to four devices simultaneously. With 11 programming sites, up to 44 devices can be programmed simultaneously, allowing customers to take advantage of 4× the throughput of any competitive machine on the market today. This combination means higher throughput, reduced cost per device and faster turnaround, resulting in higher profits. The programmer, however, is not limited to FX4 socket modules and can use any of the more than 400 proprietary automated socket modules available. Support includes the latest FPGAs, MCUs, PLDs and memories including flash in packages from the smallest microBGAs to the largest QFPs. While other systems require entire sites to be changed out when programming different device technologies, the programmer requires only a socket module change. Because the system is an off-line programmer, production lines are never slowed down, resulting in more product production and higher profit margins. BP Microsystems, Houston, Texas, www.bpmicro.com.

Phase Change Materials

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Honeywell PCM45 phase change thermal interface materials are among a suite of products designed to address thermal management challenges. Unlike traditional phase change materials or thermal greases, these materials maintain their form under continuous pressure. This avoids the tendency of other products to “pump-out” of interfacial gaps within the package and, thus, impair thermal performance. These materials exhibit excellent surface wetting characteristics resulting in low contact resistance, but do not degrade with use because of pump-out. Using a proprietary filler material provides the same high thermal conductivity of more costly boron nitride-filled systems at a cost of ownership comparable to standard phase change materials. Also, these materials offer ease of use in roll format and are available in pad form, bulk and screen printable. They offer reworkability higher than other materials and can be introduced in various stages of the supply chain without impact to form or material performance. Honeywell Electronic Materials, Sunnyvale, Calif., www.honeywell.com.

X-ray Inspection System

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WBI-FOX features automatic wafer die inspection and analysis, as well as full results documentation. The inspector's wafer mapping, fiducial marking, automatic handling and preconfigured inspection recipe capabilities result in a cost-effective system that improves process analysis and defect reduction. The system achieves its best throughput based on selected die inspection. Operators can predefined inspection recipes and a configuration wizard enables users to set up new recipes. The automated wafer handling system with transport FOUP and robotic arm ensures efficient handling and process time. Generally, a single image can be taken and analyzed in 2 sec., including selection, movement to the respective position, imaging, and void calculation/analysis. The precision and thorough documentation (reporting) capabilities of the system make it a reliable tool for an enhanced QA process. Proprietary True X-ray Intensity (TXI) controls output X-ray intensity, ensuring consistent quality images — a critical feature for an inspection system that is providing real-time images and defect analysis. The automated handling system ensures that the integrity of the wafers is maintained throughout the inspection process. FEINFOCUS, Stamford, Conn., www.feinfocus.com.

Stacked-package Module

Package-in-Package (PiP) is a new family of 3-D packages that stack packaged and bare chips into one JEDEC standard CSP. A pre-tested LGA, and a BGA or KGD are stacked and interconnected with wire bonding and are molded into a CSP that is indistinguishable from a one-chip package. The module enables a new function in the shortest time-to-market and with minimum risk by stacking packages and KGD sourced from the established supply chain. A lower PiP packaging cost, compared to the equivalent cost of separately packaged chips, and a significantly reduced final test complexity both result in a module with lower cost of ownership. A typical stacked-package module integrating an ASIC and two to three memory chips has a 13 × 13-mm footprint, 1.4-mm profile, 341 ball count at 0.5-mm pitch. ChipPAC Inc., Fremont, Calif., www.chippac.com.

Flip Chip Bonder

A high-speed flip chip bonder, FCX501 is suited to the mass production of various compact high-frequency electronics devices. The system is capable of ultrasonic and thermosonic flip chip bonding processes that create a nonmetallic bond with high thermal and electrical conductivity. The system can handle various interconnect technologies and die/substrate combinations. Panasonic Factory Automation, Elgin, Ill., www.panasonic.com.

2004 Advanced Packaging Awards


September 1, 2004

Die Attach Equipment & Materials

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Automatic Die/Glass Bonder
AD/GA898CC is an automatic die and glass bonder with dominant foreign material (FM) protection. FM particles as small as 5 µm can block the microlens of CMOS sensors, leading to device rejects. FM protection is important for the assembly process of image sensors despite the fact that the equipment already is located in a Class 100 cleanroom. Having achieved stringent cleanliness control, the bonder incorporates features from mechanical design to material selection, including clean bath and clean cells that serve as small clean rooms along with workholders that supply controlled laminar flow of ionizing air; a die picking sequence that prevents FM particles from falling on wafer surfaces; and more. The machine's design can increase assembly yield 60 to 95%. The bonder is capable of handling different types of devices, cavity or non-cavity, with high-quality bonding. ASM Pacific Technology Ltd., Hong Kong, SAR, www.asmpt.com.

Dispensing Equipment/Molding/Underfill Equipment and Materials

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Mold Bleed Flash Removal System
Current trends for encapsulating packages expose certain surfaces of the package, including leads and die pads. However, exposed surfaces lead to issues such as mold bleed and flash (MBF) on die leads and die pads. Current technologies to remove such packaging issues include media deflashing, mechanical buffing and wet chemical deflash, which have their own set of problems. Phoenix removes MBF for pre-plate lead frames and does not involve mechanical contact during the deflashing process. It is a hybrid system that uses plasma technology from the front-end of semiconductors for wafer fabrication and assembly for cleaning substrates for die attach, wire bond and molding processes. The system includes a gas chemistry formulation to capture waste and diffuse plasma energy to be channeled to the target. The key technology is in optimizing plasma energy density and optimum arrangement of the target and the various ground and power planes. ASM Technology Singapore, Singapore, www.asmpt.com.

Environmentally Friendly Materials

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Paste/Adhesive Removal System
SonicOne is a fully automatic, ultrasonic, non-hazardous, environmentally safe, paste/adhesive removal system. This is an advanced stencil cleaning/misprint system — insert the stencil into the transport shuttle and the system automatically provides wash, rinse and dry functions in less than four minutes. The system removes all paste types including rosin, water soluble and no-clean pastes as well as all SMT adhesives. It also is compatible with all chemistries on the market today. Misprinted boards are a challenge, and most systems only clean stencils and not actual product. However, the system can take a misprinted board that is populated on one side and clean the misprinted side ultrasonically with sound waves without damaging the fully populated side. The system also offers an internal wash-solution recycler. Wash solution is automatically filtered and reused, providing maximum chemical life and low chemical costs. Aqueous Technologies Inc., Rancho Cucamonga, Calif., www.aqueoustech.com.

Flip Chip Attach Equipment & Materials

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Flip Chip Platform
8800 FC Quantum platform allows high throughput in a single machine for various flip chip applications. The system's dual bonding system (DBS) executes individual bonding steps in parallel. It consists of two flip modules, two gantries — each fitted with a bond head and substrate camera, two slide fluxers and two upward-looking cameras. From one eject position, the tools of two flip units pick up the die from a wafer. After the flip process, the die is picked, dipped in the slide fluxer and measured relative to the tool by the upward-looking camera before being bonded onto the substrate. DBS also enables the platform to achieve up to 10,000 UPH throughput (dry cycle), and simultaneously maintain constant, secure process times and 10 µm at 3 sigma placement accuracy. Datacon Technology AG, Trevose, Pa., www.datacon.at.

Handling Equipment/Fixtures

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Final Test Handler
Electroglas Sidewinder is a test handler that enables final test handling of the latest geometries of packaged ICs while lowering the cost of test. The handler's basic concept considers packages in assembly arrays rather than individual devices, allowing for handling of large matrixes of parts in final test. This same approach is used during wafer probe, so the new concept treats packaged devices in assembly strips similar to the way wafers are considered for probe. The system uses machine vision alignment and handling methods that differ from those used in existing wafer probers, as well as from methods used in existing test handlers. The handler's high speed and highly precise machine vision combine with multiple handling methodologies to allow the handler to triple the throughput of currently available test handlers, and also makes testing possible for any current or planned geometry of a packaged device. Electroglas Inc., San Jose, Calif., www.electroglas.com.

Inspection/Imaging Equipment

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Wafer Inspection System
Until now, automated wafer inspection has required a fragmented approach: one system performs surface defect inspection while another performs bump metrology, where required 3-D metrology typically operates at a fraction of the speed of surface defect inspection, negating the benefits of combining platforms. However, the WS-3500 provides proven defect detection with the flexibility to include 3-D metrology as required. ShapScan proprietary 2-D machine vision technology offers high overkill control compared to competitive systems, providing high possible yields while limiting defect review. MicroMap 3-D is the only technology available that sufficiently minimizes the “speed vs. measurement stability” compromise that neutralizes the viability of all competitive 3-D technology for production. RVSI, Hauppauge, N.Y., www.rvsi.com.

Novel Package Design

Direct Chip-to-chip Signal Transmission Technology
Off The Top (OTT) IC packaging technology improves the performance and signal integrity of high-speed chip I/Os by modifying existing semiconductor packaging solutions and allowing board-level designers to integrate ICs to achieve MCM performance without the cost. This solution offers uninterrupted high-speed signal channels between chips. The result is that these ICs can communicate at full silicon speed without resorting to exotic PCB materials, costly SERDES or complex electronic I/O structures. Currently qualified IC package structures can be adapted to use technology and can be designed, produced and assembled using existing infrastructure technology. The only difference is that high-speed signals are segregated and accessed on top while I/Os on the package's bottom are used for power, ground and slower speed signals. SiliconPipe, San Jose, Calif., www.sipipe.com.

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Package Design Software & Equipment

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CAD/CAM Software
X-CAM is a CAD/CAM product for the company's line of Xise products. The system defines CAD for wafers, configures wafer-specific parameters for machines, creates operations to process wafers, sequences operations and generates process programs. It features both on- and off-line capabilities and provides customers with the tools to control and evolve their products and processes. This is performed is an easy-to-use environment that provides for simulation of possibilities before machine validation, ensuring that non-variable process variants are eliminated at the virtual stage. Enabling most of the product and process development off-line means that the machining systems are not burdened with excessive product trials and are dedicated to production. Xsil Ltd., Dublin, Ireland, www.xsil.com.

Specialized Advanced Packaging Equipment & Materials

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Single Process Co-planar Gold Bumper
Model 8000 Single Process Co-planar Gold Bumper produces planarized gold bumps in one step. The bumper uses its bond-head motion to form precise gold bumps by repeatedly shearing the wire off the top of the bump without leaving a tail. This forms flat bumps, eliminating the need for a secondary coining process. “Soft tooling,” achieved with Windows-based software, which enables changes in ball array, minimizes setup time and fixturing, position and shapes to match the desired attach xprocess. A finished bond height consistency of 2 µm (at 3 sigma) is achieved with better than 5-µm placement accuracy. Gold wire is used for a lead-free process. The process runs automatically at a cyclical rate of >10 bumps per second. Palomar Technologies, Vista, Calif., www.palomartechnologies.com.

Substrate and Submount Materials & Technologies

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Probe Chip
By exploiting the same advanced tools used to design and manufacture modern semiconductors, the Celerity Probe Chip card circumvents the cost per pin penalty associated with conventional probe cards. Using “chips to test chips” revolutionizes the test tooling cost model and also technologically enables the ITRS roadmap. The probe chip leverages EDA and simulation infrastructure to provide more accurate and predictable test tooling performance. It is a fully scalable solution with the repeatability and reproducibility of semiconductor fab technology. Celerity Research, San Jose, Calif., www.celerityresearch.com.

Quality Assurance/Management Tools

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Design and Content Software
SymXpert Pro automatically extracts PCB library content from suppliers' component datasheets and checks for accuracy. It then saves symbol content in an EDA-neutral format, allowing OEMs and ODMs to create standardized design libraries without displacing current design tools. The Intelligent design content can be leveraged and shared across multiple design locations, specifications and EDA tools. The application allows engineering organizations to reduce the cost of building and maintaining symbol libraries, create 99.78% error-free symbols 24X faster than doing it manually, and validate the correctness and consistency of symbols to meet specifications. ChipData Inc., Richardson, Texas, www. chipdata.com.

Reflow Equipment

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Selective Soldering Station
Version Pro-8 T and B, 60 W Diode Laser Cell with Vision Guidance is an in-line soldering station that combines performance, software and precision movement to selectively solder most top- or bottom-side applications. A special lens configuration automatically adjusts to keep the laser at full power output, and the solder feed tube also dynamically adjusts, allowing it to reach the proper height for soldering. Because the laser can be precisely controlled, is highly repeatable and provides a focused heating zone, it results in better control to and around the component. Changeover from tin/lead to lead-free soldering also can be accomplished within minutes. Pro-mation Inc., Kenosha, Wis., www.pro-mation-inc.com.

Surface Treatment Equipment & Materials

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Plasma Treatment System
FlexTRAK is a configurable, high-throughput plasma system. Its universal architecture accommodates numerous material handling configurations to support an assortment of variable-size form factors. Configurations include magazine-to-magazine processing for single and multiple strips or lead frames, reel-to-reel, wafer processing, and standalone for island-based production environments. The system features application flexibility for direct, downstream and ion-free (patent-pending) plasma that allows treatment without exposure to the direct plasma glow discharge; a compact, three-axis symmetrical chamber and proprietary process control for unmatched process uniformity; and short cycle times with throughputs up to 480 substrates or 800 strips/hour. March Plasma Systems, Concord, Calif., www.marchplasma.com.

Testing Equipment

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Test Socket Web Tool
For today's semiconductor test engineers, the time span between notification of a requirement and first silicon has been reduced to weeks. A challenge in meeting this expectation is the development of the customized test socket. SocketBuilder.com transforms the way test sockets are purchased. Through proprietary Web technologies, the site has accelerated test socket design to approximately five minutes. Step-by-step, the user specs out their application, chip, electrical performance criteria, handler type, etc. In minutes, SocketBuilder.com e-mails a hyperlink to a detailed manufacturing drawing and a preliminary estimate. Currently, the site automates design for QFN and area-array packages. It also specs the appropriate sprint contact probes. Synergetix, Kansas City, Kan., www. synergetix.com.

Wafer Dicing/Thinning Equipment

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In-line Grinding System
DGP8760 and DFM2700 in-line system provide a 300-mm solution for ultra-thin grinding, stress relief, DAF lamination and post-grinding tape functions. DGP8760 uses a 3-spindle, 4-chuck, 1-turntable configuration to process three wafers simultaneously: rough grinding, fine grinding and dry polishing. Because it uses no chemicals or slurry, it is cost effective and environmentally friendly. Also, DFM2700 provides advanced DAF lamination and post-grinding tape functions: mounting of wafers in dicing frames followed by UV irradiation and protective tape removal. Because each wafer remains on the same chuck table throughout processing on the DFM2700, wafer handling and associated risks are reduced. Disco Hi-Tec America Inc., Santa Clara, Calif., www.discousa.com.

3-D Packaging Technology

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Drilling Production System
Xise 300V is a high-volume production system that allows for laser drilling of clean vias through silicon and other materials. Targeted at stacked-die applications, the high-volume production system creates clean vias through silicon and other materials. With a platform designed for drilling vias and machining wafers up to 300 mm, the system allows for high-volume manufacturing of clean vias through silicon at rates up to hundreds of vias per second. Complete with bare wafer handling and top- and bottom-side vision, the system offers wafer inversion capabilities. The process also allows for clean drilling through various, individual material layers in wafer thicknesses from microns up to more than 1 mm. Xsil Ltd., Dublin, Ireland, www.xsil.com.

Thermal Management Technology

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Leadless Plastic Package
Thin Array Plastic Package (TAPP) is a leadless package that features high I/O capability, single and multiple rows, 0.4-mm thicknesses for some applications, and an exposed die-attach pad, allowing for optimum thermal performance. The exposed die pad (when soldered to a PCB) provides a direct thermal path from the chip to the copper plane on the PCB, the latter acting as a heat sink. This reduces the thermal resistance of the package by as much as 50%. Environmentally friendly, the package is available in lead-free and green options. It also offers 99.8% yields because of its simple process flow and chemically milled processing. The package features low test cost because it is strip-test compatible without any additional preparation steps. ASAT Inc., Pleasanton, Calif., www.asat.com.

Wafer-level Packaging Equipment & Materials

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Wafer Printing/Bumping System
SemiTouch Wafer Printer system (STW-1) is capable of wafer stencil printing and bumping within a single system — by pressing a button, the system converts from a wafer bumper to stencil printer in seconds. The patented vibration squeegee technology uses vibration to both spread the paste uniformly and to remove air that becomes trapped in the apertures with the vibration movements, which allows for a uniform print. Paste scavenging is eliminated and less paste is required to print. The printer uses a bottom-side stencil cleaning system with ultrasonic vibration and cleans six strokes back and forth in less than six seconds. The blades are fully cleaned during operation by ultrasonic cleaning. Milara Inc., Medfield, Mass., www.milarasmt.com.

Wire Bonding Equipment

Automatic Ball Bonder
Offering bond placement accuracy of 2.5 µm, the Maxµmplus High Performance Automatic Ball Bonder excels when advanced looping capabilities are required, such as forward folded low loops, CSP long inboard loops, advanced BGA loops, ultra low, and J-wire loops. Improving on the Maxµm X-Y-Z servo control system, the bonder reduces wire cycle times to 63.0 msec, and optimizes the most frequently occurring short X-Y motions, increasing productivity. This performance is maintained over a single pass bonding area of 56 × 66 mm (2.2 × 2.6″). Kulicke & Soffa Industries Inc., Willow Grove, Pa., www.kns.com.

It is once again with great pleasure that Advanced Packaging Magazine congratulates the winners and participants of the 2004 Advanced Packaging Awards. This was our 4th annual event in an awards program that has fast become a very prestigious and sought-after recognition. Four years ago, PennWell and SEMI developed a partnership to develop an awards program to recognize the product innovation and ingenuity of companies making leading-edge contributions to the final assembly process of semiconductor manufacturing

This year, we had winners in 19 categories from a record-breaking number of submissions in categories ranging from 3-D package design, test and inspection, to wafer thinning. The winners were chosen by a distinguished panel of judges composed of industry experts and members of academia. An Advanced Packaging crystal was presented to the winning companies at our ceremony held during Semicon West in San Jose in July. A capacity crowd applauded the companies as they were honored for their innovative contributions.

The Advanced Packaging Awards program was created to recognize the positive advancement of semiconductor packaging technology. As such, both small and large companies compete on an even playing field for the award. Each submission is judged based on its ability to meet a significant industry challenge; to creatively apply a new or existing technology; to show overall quality and consistency in performance; and to offer economic merits. All submissions are judged on innovativeness; cost effectiveness; speed and throughput improvements; quality contributions; ease of use; maintainability or reparability; and environmental responsibility.

In the following pages, you will find a presentation honoring those companies who were this year's recipients of an Advanced Packaging Award. I ask you to take a moment to learn more about these amazing products and the companies behind the innovations. These are the types of companies that continue to lead the expansion of technology within the final assembly of the semiconductor market.

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Again, congratulations to this year's winners!

John Bubello
Advanced Packaging Publisher

BY CEMAL BASARAN

The Electronic Packaging Lab at the University at Buffalo has earned a reputation for its cutting-edge work in developing computational and experimental measurement tools for facilitating the development of the next-generation microelectronics packaging. While we continue to focus on that area, we are turning our attention to power electronics and nanoelectronics, applying our capabilities in computational modeling and reliability testing to critical problems associated with nanoscale electronics and operating power electronics in harsh environments.

Douglas C. Hopkins, Ph.D., an expert on power electronics system integration, currently is leading our efforts to develop a power electronics package with a silicon carbide semiconductor mounted on a silicon carbide composite structure, compared to a silicon semiconductor mounted on Al203. This device can be pushed to operate at 400°C and above. Our mission is to perform a complete virtual product development to test the reliability of the device and certify materials that can be used to attach the device for high-temperature operations. The final product is a 60-kW power converter for the U.S. Navy that can operate at extremely high temperatures and vibration levels.

Working with a power electronics company, we are designing a dense system to be contained within a 1 × 1″ package. Our team is investigating methods to mount the SiC device in a way that will enable running the device at extremely high temperatures and getting 10× the amount of power out of it. A challenge is how to maximize and manage heat gradients within such a small package. In our lab, we measure the reliability of devices and materials under very high temperatures, vibrations and very high current density levels. Our team has developed a computer modeling system that can test the reliability of the packages under extremely harsh conditions — accurately simulating various conditions of heat, high current density and vibration at the same time. Such modeling can provide huge savings for companies in terms of development costs, product testing and time-to-market. Using the micromechanical properties of materials, computer modeling can construct mathematical models of their thermomechancial behavior and fatigue life in a unified manner.


Figure 1. These images show flip chip solder joint failure under high current density.
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When a package is able to manage very high current density and high temperature, obviously, devices can be made lighter and smaller. But just as important, they can be placed much closer to the point of load. For example, in a related project with the Navy, our lab is developing power devices that can be mounted close to a ship's propulsion system and its weaponry — areas where temperature and vibration are a major concern. Developing reliable power electronics under these conditions is complex because when you combine thermal cycling and vibration at high temperatures, materials become liquid.

Our lab is also developing flip chip and BGA packaging technologies for power electronics and nanoelectronics, where high current density and high temperature gradient are the major obstacles to further miniaturization. We have been able to measure the deformation field in a solder joint under very high current density levels and also develop a constitutive model to predict the strain and damage evolution due to high current density (Figure 1). When our Navy- funded project is complete, it will be possible to design a solder joint small enough to carry 106 Amp/cm2.

Not all of our testing is done via computer simulation, however. Alexander Cartwright, Ph.D., an expert in lasers and photonics, is leading efforts to develop ways to detect and measure solder strain at the nano level. We have developed a technique to measure solder strain at 27.5 nm. The technique uses continuous wavelet image processing to improve the sensitivity of moiré interferometry, which uses He-Ne laser beams to measure the displacement field of a package as it is exposed to simulated service conditions. Phase shifting controls where the light is on the material, and we measure its movement and take images of the material's fringes. Wavelet transform processing then removes the noise from the image — providing a much clearer image that now can be read by a computer, as well as very accurate stress and strain measurements. This technique brings you down to the nano level, where small changes in deformations can be measured.

In the future, we hope to apply our technologies to help design packages in sensors used for environmental and chemical sensing within fuel cells, and also for use in the automotive and aerospace industries.

CEMAL BASARAN, Ph.D, director of the University at Buffalo's Electronic Packaging Lab and an associate professor of engineering in the School of Engineering and Applied Sciences, may be contacted at the University at Buffalo, The State University of New York, 102 Ketter Hall, North Campus, Amherst, NY 14260; (716) 645-2114; e-mail: [email protected].

BY HARRY R. ROZAKIS

Although the proliferation of semiconductor packages has been a part of the industry for the past 20 years, the last several years have seen the rate of proliferation accelerate. Several factors are behind this phenomenon, including but not limited to: the requirement for higher-performing and more reliable packages; lower-cost packaging solutions; environmentally friendly devices; the push by both IDMs and SATS companies to differentiate themselves from their peers; and thinner/smaller form factors required by OEMs. One need only look at a list of JEDEC standardized packages to affirm this ongoing proliferation. What is the business and financial impact of package proliferation on semiconductor manufacturers, SATS companies and end users?

To date, we have yet to see a definitive study that includes the cost impact of package proliferation. We suspect that an in-depth analysis would be daunting and probably reveal the ugly truth about the cost of new packages. The introduction of a new package or incrementally enhanced package is not only expensive to the developer of the package, but it also accounts for increased costs throughout the supply chain. These costs include the actual development of the package, qualification of the package (both internal and external), initial tooling by the semiconductor manufacturer and/or SATS company, qualification and tooling at the EMS company or end user, etc. With new packages, there are often material set changes that also contribute to the overall cost.

Historically semiconductor packages were designed by IDMs who had large package development organizations. These were principally reactive engineering groups that were addressing “die in search of a package.” Although there are still some IDMs who engage in package development, the majority of this work is now handled by SATS companies, with the real driver being the needs of the OEMs. There is also the emergence of package development IP companies, such as Tessera. Clearly, for many IDMs the elimination of their package development organizations meant a reduction in workforce and lower cost; in actuality, the cost was simply passed on to SATS companies.

SATS companies such as ASAT, Amkor and ChipPAC became proficient in the area of new package development. These same companies developed their own intellectual property (IP). They began to see package development as a vehicle to differentiate themselves from their peers. In many cases the differences were subtle, yet they were present. These differences, however, carried and still carry with them many added costs for all parts of the supply chain. The tooling costs alone for changes in package technology are enormous.

Differentiating themselves from their peers is not the key driver for SATS companies to develop new packages. The fact is that the dynamics of the end markets have dramatically changed during the past 12 years, driving the need for packages with added performance characteristics and alternative form factors. Cell phones, GPS systems, Internet applications, wireless, etc. and the “green” movement continue to contribute to the development of new package technologies. The need for greater functionality has driven technologies such as SiPs, stacked die, wafer-level packages and high-thermal-performance packages.

We operate in an industry that is cost driven. Our business constantly demands higher value at lower cost. SATS companies and IDMs alike are being pushed toward lower-cost package solutions, but the act of developing lower-cost solutions is responsible for added costs throughout the supply chain. Whether it is the material supplier developing a “green” molding compound; the series of quality and reliability testing that is executed by the SATs provider, semiconductor manufacturer, EMS company, or OEM; or the related tooling required to bring up a new package, each adds cost.

Unfortunately, there is always a cost associated with change and we are in an ever-changing business. The challenge is for all of us, no matter what discipline we support, to manage package proliferation. Managing the situation means having to quantify across the supply chain the true cost of a new package. It also has to be comprehended by the OEMs, who have become the driving force behind new package development. We should never lose sight, however, of the fact that standardizing packages also has associated risks. Old packages never die; they simply become a part of a growing portfolio of packages. The challenge to our business is how we manage package proliferation and still manage the cost of new package development and implementation.

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HARRY R. ROZAKIS, CEO, may be contacted at ASAT Holdings Ltd., QPL Industrial Bldg., 138 Texaco Road, Tsuen Wan N.T., Hong Kong; 852 2408 7811.

In the News


September 1, 2004

It's Official: STATS/ChipPAC Merger is Complete

SINGAPORE AND FREMONT, CALIF. — Following a successful governmental review and shareholder vote, STATS and ChipPAC have officially merged and are now operating as “STATS ChipPAC Ltd.” ChipPAC is continuing operations as a wholly owned subsidiary of STATS ChipPAC Ltd. The pair merged in a stock-for-stock transaction, creating one of the world's largest independent semiconductor assembly and test solutions companies – with a global manufacturing footprint spanning China, Korea, Malaysia, Singapore, Taiwan and the U.S.

Under the terms of the merger agreement, Charles Wofford, chairman of STATS, is the chairman of STATS ChipPAC Ltd. Dennis McKenna, chairman and CEO of ChipPAC, is now the vice chairman. Tan Lay Koon, president and CEO of STATS, is serving as the president and CEO of the combined company.

“With the merger of STATS and ChipPAC now completed, we are moving forward in our vision of creating one of the world's premier independent providers of fully integrated test and assembly solutions,” says Koon. “STATS ChipPAC now offers customers end-to-end assembly and testing solutions by combining STATS' testing and ChipPAC's assembly expertise. This is a powerful differentiating factor and a compelling value proposition for our customers, employees and investors. STATS and ChipPAC each had impressive customer lists prior to the merger. Combined, STATS ChipPAC has one of the strongest customer bases in the industry, including nearly every major semiconductor company in the world.”

STATS ChipPAC Ltd. expects to have more than $1 billion in pro forma revenues for full year 2004, according to the company, assuming that merger had closed on January 1, 2004. “Financially, we have created one of the industry's strongest players, capable of supporting our customers' ongoing program ramps, while continuing to invest in advanced technologies essential to our own new business development,” says Michael H. Potter, CFO of STATS ChipPAC. “Due to the complementary nature of this merger, we believe that the integration will be straightforward and have minimal impact on employees and operations of our existing plants.”

The combined company's headquarters are located in Singapore.

Carsem's China Facility Ships Production Volumes

SCOTTS VALLEY, CALIF. — Carsem's Suzhou factory has completed its initial customer qualifications and is now shipping production volumes of micro-leadframe package products. The first production parts were recently shipped to Sematech Corp.

“Sematech has been an excellent partner in helping us reach another major step toward meeting the tremendous growth potential of the China market, as well as the rapidly increasing demand for the MLP package family,” explains David Comley, Carsem's group managing director.”

Construction of the new factory was completed back in January, and since then more than 100 of the current staff of 180 employees has received extensive training in Carsem's existing Malaysian factories, according to the company. The current installed assembly and test is focused on the production of the entire range of MLPQ (quad) and MLPD (dual) packages, which is a saw-singulated version of QFN- and SON-compliant packages per JEDEC's MO220 and MO229 standards. These packages are available in a wide range of body sizes, as well as a lead-free version.

Chip Sales Are Up, But SIA Cautions of Slower Growth Ahead

SAN JOSE, CALIF. — Worldwide sales of semiconductors reached $17.8 billion in June, a sequential boost of 2.8% from the $17.3 billion reported by the Semiconductor Industry Association (SIA) back in May, and a 40.3% increase from last year's $12.7 billion. During the second quarter of 2004, global sales reached $53.45 billion — an increase of 9.5% from first quarter sales of $48.8 billion.

Microchip sales remain on pace to reach a record of more than $214 billion this year, according to the SIA. While sales in the second half of the year are expected to remain strong, a slowing of the growth rate is expected for the rest of the year. Third quarter sales are expected to be 4 to 6% higher than the second quarter based on the SIA's analysis of inventories, product capacity and end-market demand.

Strong sales of DRAMs, which were up more than 100% year-on-year, are cited by the SIA as the leading driver of second quarter growth. “Sales of personal computers have remained strong, with year-on-year growth of around 13% in the second quarter,” says SIA President George Scalise.

Wireless communications was another strong driver of demand for semiconductors in the first half of 2004. Sales of chips for wireless communications, including digital signal processors (DSPs) and application specific standard products for wireless applications, rose by 86.5% from the same period a year ago. Reflecting strong sales of digital cameras and cell phones with picture capability, sales of optoelectronics devices were up 52.4% year-on-year.

The Asia-Pacific market again slowed the strongest year-on-year growth at 61%, followed by the Americas at 30%, and Japan at 26%.

Impressions from Semicon West

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BY JULIA GOLDSTEIN
SAN JOSE, CALIF. — Many companies deciding this was the year to unveil new products. Here are a few of the companies who enthusiastically shared their latest news with Advanced Packaging…

Nextest introduced their Magnum tester, based on their line of low-cost testers but designed for high-volume applications in the consumer digital appliance market. It uses a scalable architecture, combining many 128-pin systems to provide up to 5,120 pins in a single test head for parallel test of memory, logic or mixed-signal chips. Each 128-pin test system, which required five PCBs in Nextest's earlier products, includes its own PC and has been integrated onto a single board.

FEI has been doing circuit edit using focused ion beam (FIB) systems for many years, but they have added new features to their 5th generation tool, including 65-nm capability and copper deposition. Pattern recognition software has been integrated to provide “machine intelligence” and automate the alignment process, and endpoint techniques for z-direction navigation have been improved to accommodate higher aspect vias.

Unitive is excited about their turnkey wafer-level CSP capabilities at their new die- level processing facility. In addition to bumping and multilayer redistribution, they also perform backgrinding, dicing, package marking, test and inspection.

GE Advanced Materials announced three new silicone-based materials at the show. Their new thermal interface material is designed for low thermal resistance to quickly dissipate heat generated by high-power devices, and it can be used for both first- and second-level applications. New die attach adhesives are aimed at large or thin dies, where the low stress and low modulus of the material can improve reliability, and for lead-free processing, since silicones are stable at high temperatures. Their third product is a transparent encapsulant for high-power LEDs with a high refractive index that resists yellowing, bubbling and delamination over time, enabling long-term reliability. GE has been increasing R&D spending recently, with a new technology center opened in Japan and more new product introductions expected in the near future.

There are lots of reasons why companies buy other companies. Purchasing a competitor, for instance, then folding that company is one way to control a market. Purchasing a company with expertise in an area that your firm would like to expand into is another method for investing in R&D without starting from scratch. Simple investment for healthy returns, much like purchasing stock, is yet another reason for the process.

On July 21, 2004, publicly traded Amkor Technology Inc. of Chandler, Ariz., reported that it signed an agreement to acquire privately held, Morrisville, N.C.-based Unitive Inc. and to obtain a majority interest of approximately 60% in Taiwan-based Unitive Semiconductor Taiwan Corp., a joint venture between Unitive and various Taiwanese investors.

It didn't come as a big surprise. Just 2 years ago, Advanced Packaging reported that Amkor and Unitive had formed a 2-year manufacturing alliance for the Asian supply chain Under the agreement, Unitive became Amkor's primary source of wafer-level packaging solutions in Taiwan, providing wafer-level design, repassivation, redistribution and bumping services. Amkor provided a broad range of packaging and test services including probe, wafer thinning, substrate design and procurement, assembly, and final project management and support services.

Bruce Freyman, Amkor's president, says, “Unitive is a premier electroplated and wafer bumping, wafer-scale packaging company, and our acquisition of them gives us a significant advantage in the marketplace in next-generation flip chip packaging.” The synergy between Amkor, a contract semiconductor assembly and test services (SATS) provider, and wafer-level packaging from Unitive has grown from an existing long-term partnership.

It was a smart move. Flip chip unit growth is expected to triple between 2003 and 2007, according to TechSearch International. This is much larger than predicted growth for the semiconductor industry overall. As the industry increases its adoption of flip chip and wafer-level packaging, the ability to provide subcontract services in integrated wafer bumping, wafer-level processing and chip packaging should be a way for Amkor to differentiate itself from other SATS providers.

At SEMICON West this year, Unitive made lots of announcements. First, they developed and qualified an electroplated lead-free bumping technology using a SnAg approach, thus meeting global requirements to remove lead from electronics. Unitive also announced a die-level processing capability that integrates services such as design, wafer bumping, multiplayer redistribution, backgrinding, dicing, tape-and-reel, backside laminate, backside metallization and laser marking. The company's latest process of applying a new spun-on polymer coating permits further reductions in the size of ICs.

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From any angle, Amkor's decision to acquire Unitive is an insightful reach into the future.

Gail Flower
Editor-in-Chief