Step 2: Stud Bump Bonding

Flip Chip Enabling Technology


Stud bump bonding is a modified wire bonding process. Like wire bonding, there is bonding of the ball to the die pad. Unlike wire bonding, there is no second wire bond to a lead. The wire is terminated after the first bond, so there is only a bump on the die pad. To complete the interconnect, the die is flip-chipped onto a substrate using a thermosonic or thermocompression process.

The stud bump process is mainly performed at the wafer level for volume production applications. This process can be used for singulated die, but is less attractive for volume production because of the additional handling time and the risk of damaging bare die.

With stud bumping, unlike other wafer bumping processes such as solder deposition, the wafer does not require pre-treatment such as under bump metallization (UBM) or redistribution layers (RDL). The perimeter of the pads of the die can be bumped so that rerouting the circuitry to an area array is not needed. For centerline memory die pad layout, redistribution can be avoided. This provides cost savings of as much as $1/die, depending on die size, wafer size, and yields.

Stud bumping’s similarity to wire bonding allows it to be performed on a wire bonder platform, provided that the bondable area can accommodate the entire wafer. Single-die bumping can be accomplished on a standard IC ball bonder, as long as there is a mechanism to handle bare die. However, whole wafer bumping is the desired approach. Not only does whole wafer bumping reduce handling during the bumping process, it also allows the bumped die to be presented for die attach as a diced wafer on film frame, which is the preferred presentation method for the downstream die attach process. Die bonders typically can pick-and-place a die faster from a film frame than when it is loose inside a waffle pack, because there is less probability for theta rotation.

Depending on the capabilities of the stud bump bonder, a range of wafer materials can be bumped. Some stud bump bonders can accommodate a 300-mm silicon wafer. More exotic wafer materials, such as lithium niobate (LiNiO3) used for SAW filters, can be bumped if the bonder platform has the ability to ramp temperatures up and down. As these wafers typically come in 100-mm sizes, two wafer chucks can be positioned on the bonder to allow one wafer to be bumped while the other is ramping the temperature up or down.

Avoiding Yield Issues

To avoid yield issues when wafer bumping, it is preferable to use an automatic wafer handler that can take the wafer from an industry-standard carrier, automatically orient it, place it on the wafer chuck on the bonder and, after bumping, in an output carrier.

Process engineering involving the bonder’s process program and choosing the right materials can yield low-temperature bumping. This is desirable for bumping temperature-sensitive devices such as SAW filters, or when bumping a wafer that has been thinned and is handled on a film frame.

Figure 1. Standard stud bumps.
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To create the stud bump, a ball is formed using a standard ball bumping process. After the ball is bonded to the die pad, the wire clamps are closed and the bondhead moves to tear the wire. If the move is purely vertical, a “tail” can be left on top of the bump (Figure 1). The height and repeatability of this tail is largely dependent on the composition of the wire. When the bumped die is subsequently flip-chipped, this tail may or may not be a problem. If the tail is too long, it may be pushed to one side when the die is flip-chipped and cause a short to the adjacent bond. Repeatability of tail length control is critical.

Overcoming Bump Height Planarity Inconsistencies

To overcome inconsistencies in bump height planarity, two methods can be used. The first method involves using a sequential process in which the bump is “coined” by pressing it with a flat tool. The second method is to move the bondhead horizontally after closing wire clamps to effectively shear the top of the bump. This “self-coining” process is slightly slower than the pure vertical move, but results in a bump that is virtually planar.

The size of the bonded bump is dependent on the wire size and type, as well as the bonding tool and the bonding process. Special wires have been formulated to better control the heat-affected zone (HAZ) to provide a repeatable bump height and shape. Today, most stud bumping uses gold wire, although there is increasing interest in using copper. Contrary to solder bumping, stud bumping is lead-free.

Figure 2. Stacked bumps.
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Due to the nature of the wire bonding process, there is a relationship between the wire diameter and ultimate height of the bump. For applications in which more of a standoff is desirable to help compensate for thermal mismatch, stud bumping provides the flexibility to stack more than one bump on top of each other (Figure 2). Whether it is one bump or more, gold stud bumping offers superior reliability compared to solder bumping, because it is not subject to solder fatigue.

The bond pitch of the substrate must be the same as the pad pitch of the die. These fine-pitch substrates are readily available today. Stud bumping can provide significantly finer pitch than solder deposition processes. Leading-edge solder bumping in production today achieves 160 µm, with 200-µm pitch being more the norm, whereas stud bumping can achieve pitches similar to IC ball bonder processes of ≤50 µm.

Figure 3. Cost comparison of different bump types, stud bump bonders, and applications.
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The flip chip attachment process for stud bumps differs from the solder bump flip chip process. With a solder bump, the flip chip die bonder is used to pick-and-place the die, often with flux, onto the substrate. The die remains in place because of the tacky adhesion until it is reflowed in an oven, provided it is carefully handled and reflowed in a timely manner. With a stud bump process, the flip chip bonder is used to pick, place, and interconnect the die to the substrate right on the bonder. There is wide choice in materials and methods. Thermocompression bonding uses heat and force, usually with an intermediate material such as anisotropically conductive adhesive or epoxy, to form a mechanical bond. Thermosonic bonding uses heat, force, and ultrasonic energy to make an intermetallic connection referred to as gold-gold interconnect (GGI).

Calculating the Cost of Stud Bumping

Unlike other bumping processes, stud bumping is performed serially, one bump at a time. To compare its cost effectiveness, it is necessary to calculate the cost to bump an entire wafer. With mass bumping processes, it is easy to get a quote for the wafer bumping service or calculate the cost to set up and run an in-house process. To calculate the cost of stud bumping, it is necessary to know the cost per bump, which is determined by factors such as equipment cost, number of bumps/sec. produced by the bonder, cost of materials, etc. It can then be determined where the “cross-over point” is in cost/number of bumps/wafer. Figure 3 shows how the cross-over point can vary, depending on the border platform used. The major cost factors are the gold wire and the number of bumps/sec. the machine can produce. Cost is a compelling reason to use stud bumping, but pitch and volume also may drive this decision.


Due to the serial nature of the stud bumping process, it is most suitable for lower I/O devices (400 I/O or less, depending on the number of die/wafer). High-volume applications in production today include SAW filters and hearing aids. In the case of SAW filters, the “active” face of the die that is not passivated makes the stud bump and GGI process a suitable choice.

More recently, stud bumping is being used for image sensors in digital phones, memory devices, smart cards, and digital signal processors. It has unique attributes that make it attractive for stacked die applications. For example, a bottom die can be stud bumped, then flip-chipped with a second die directly attached to the first die. This results in an overall thinner package than if both die were wire bonded. The silicon-to-silicon interface reduces any CTE mismatch. Increasingly, stud bumping is being used as part of the flip chip process onto flex substrates to achieve thinner packages. Stud bumping is proving to be a flexible, cost-effective process for enabling new flip chip applications.


For a complete list of references, please contact the authors.

LAURIE S. ROTH, director of Strategic Marketing, and VINCE MCTAGGART, Product Marketing manager, may be contacted at Kulicke & Soffa Industries Inc., 2101 Blair Mill Rd., Willow Grove, PA 19090; (215) 784-6000; e-mail: [email protected], [email protected].


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One thought on “Step 2: Stud Bump Bonding

  1. Zigmund

    Hi! By any chance, would you have a ballpark figure of how big a workpiece can be for stud bumping (ie. maximum wafer size or panel length and width).

    Are there modified bonders out in the market that can possibly stud bump 300mm wafers or even 380×610 mm board panels? Or, if not, is it entirely possible to modify a bonder to accomodate such sizes?


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