Trends in Materials: The Smartphone Driver
Date: Thursday, April 30, 2015 at 1:00 p.m. EST
Free to attend
Length: Approximately one hour
Today the semiconductor industry is driven by smartphone with 1.24B units sold in 2014 out numbering tablets & PC sales. The expected increase in smartphone application processor (AP) demand in 2015 (Apple A9, Samsung Exynos 7 and Qualcomm Snapdragon) is driving the rapid ramp to 14/16nm 3-D FinFET at foundries, 3-D memory devices such as 128Gb Flash with 32-layers and 3-D stacked chips for package area saving. Intel was first to production with 3-D bulk-FinFET devices at the 22nm technology node in 2012 and reported their SOC for Chinese low-end smartphones. Intel’s 2nd generation bulk-FinFET devices at 14nm node was introduced in Aug 2014 and their SOC to follow. Apple uses Sony’s 8M pixel 3-D stacked backside CMOS image sensor for rear-facing cell phone camera and Samsung offers two versions of the 128Gb Flash memory either 16nm 2-D NAND or 32nm 3-D NAND with 32-layers. Samsung Galaxy S6 will also use 3-D ePoP (embedded package on package) which stacks AP+DRAM+Flash+MMC saving 40% area and use 20M pixel rear-facing cell phone camera and 8M pixel RWB image sensor for front-facing camera.
To understand 3-D FinFET doping and high mobility channel material, this talk will first review the current doping and Fin/channel mobility enhancement techniques used for 22nm FinFET production by Intel for both high performance logic and SOC devices and the changes they made for their 2nd generation 14nm FinFET. Apple A6 and A7 used Samsung/Foundry’s 32nm and 28nm technology while the A8 uses TSMC’s 20nm technology. Later this year, Apple will introduce the A9 which will switch from 2-D planar to 3-D FinFET using both Samsung’s 14nm FinFET and TSMC’s 16nm FF+ technologies. Then at the 10nm or 7nm node higher mobility Fin/channel material (SiGe, Ge or III-V) is expected to be introduced and currently exploratory research of gate-all-around nanowire for 5nm technology node. Traditional gas/vapor phase epitaxial growth techniques by chemical vapor deposition (CVD) or an alternative liquid phase epitaxial (LPE) regrowth of an amorphous material layer by melt solidification for direct channel mobility enhancement are under investigation. Finally, a discussion on dopant activation in high mobility material.
John Ogawa Borland received his B.S. and M.S. degrees in Material Science and Engineering from the Massachusetts Institute of Technology (MIT) in Cambridge, MA. He completed his BS thesis research on InP Liquid Phase Epitaxial (LPE) crystal growth at Hughes Malibu Research Labs in 1980 and his MS thesis research on InP Molecular Beam Epitaxial (MBE) crystal growth at Nippon Telephone and Telegraph (NTT) Labs in Musashino, Tokyo, Japan in 1981. He is a senior member of IEEE and the IEEE Hawaii section chair, a member of the Electrochemical Society (ECS) and Materials Research Society. He is co-organizer for the Symposium on ULSI Process Integration IV (2005) and was on the organizing committee for the 2001 & 2003 symposiums, Semiconductor Silicon (1994 & 1998) and Chemical Vapor Deposition X, XI & XII (1987, 1989, & 1991). He also is advisory committee co-chair for the IEEE International Workshop on Junction Technology (2008, 2010, 2011, 2012, 2013 and 2014). He has published over 135 technical and invited papers around the world and has been awarded 6 patents all in the areas of advanced semiconductor device manufacturing techniques. He is also on the Editorial Advisory Board of Solid State Technology magazine.
John was Director of Operations of APIC’s subsidiary Advanced Integrated Photonics which is their Silicon Photonics Foundry Fab in Honolulu, Hawaii from April 2013 to Aug 2014. In June 2003 he founded and is president of JOB Technologies a strategic marketing, sales and technology consulting company providing service to the semiconductor device manufacturing and equipment companies in the area of 14nm down to 7nm node front end of line process development focusing on Ge high mobility material and technology for CMOS.
From July 1998 to May 2003 he was Director of Advanced Business Development at Varian Semiconductor Equipment Associates. While at VSEA, he invented the high tilt high current PoGI process for process simplification and improved device lateral channel and source drain engineering. He also led the revived interest in low temperature diffusion-less activation by solid phase epitaxy (SPE) and its inclusion in the 2003 ITRS roadmap. From Nov. 1992 to July 1998 he was Vice President of Strategic Technology at Genus before they were acquired by Varian and invented the MeV BILLI structure for CMOS epi replacement, process simplification and improved latch-up performance. From Sept. 1983 to Nov. 1992 he was at Applied Materials and pioneering advanced silicon epitaxial and polysilicon/amorphous deposition techniques and equipment designs for blanket epi and polysilicon. He also patented some of his work on selective epi (SEG) and selective poly through surface interface cleaning techniques. This led to the successful implementation of SEG for local strap and elevated source drain by a major DRAM manufacturing company in 1987. Also, a variation to his epitaxial lateral overgrowth (ELO) for SOI is used today for epitaxial bonded SOI wafer manufacturing. From Aug. 1981 to Sept. 1983 he was at National Semiconductor Corp. developing the VHSIC-CMOS front end processing including bulk and epi wafer intrinsic gettering for improved gate oxide integrity and yield as well as substrate and CMOS well engineering for improved latch-up immunity.
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