Wafer bonding for high performance MEMS, power devices, and RF components

Recent trends and future directions for wafer bonding are reviewed, with a focus on MEMS.


All devices and products are evaluated to varying degrees on the following factors: 1) availability or assurance of supply, 2) cooling requirements, 3) cost, 4) ease of integration, 5) ease of use, 6) performance, 7) power requirements, 8) reliability, 9) size, and 10) weight. MEMS devices are no exception and the explosive growth of MEMS devices during the last decade was driven by substantial improvements in some of the aforementioned variables. MEMS manufacturing is based on patterning, deposition and etch technologies developed over the last 50 years for the manufacturing of ICs along with the relatively new technologies of aligned wafer bonding and deep reactive ion etch (DRIE). This article will review the recent trends and future directions for wafer bonding with a focus on MEMS along with some mention of wafer bonding for RF and power devices.

The incredible growth in MEMS over the last 20 years has been enabled by the development of the DRIE process by Bosch and by aligned wafer bonding. Many MEMS devices have very small moving parts, which must be protected from the external environment. Initially, this was done using special packages at the die level, which was relatively expensive. Wafer-level capping of MEMS devices seals a wafer’s worth of MEMS devices in one operation, and these capped devices can then be packaged in a much simpler and lower-cost package. Anodic bonding and glass frit bonding were the initial bonding processes used for MEMS and are often referred to as “tried and true.” However, both of these processes have challenges, and as a result, few new MEMS products and processes are being developed using these processes.

Anodic bonding requires the presence of Na or some other alkali ion which causes several problems. The first is that Na ions are driven to the exterior of the wafer during the bonding process and will accumulate on the bonding tooling, requiring the tooling be cleaned on a periodic basis. The second is that Na can cause CMOS circuits to fail – preventing anodic bonding from being used to combine MEMS and CMOS. Almost all MEMS devices require a CMOS ASIC to process the output signal from the MEMS device. Historically, this integration has been done at the package level with wire bonding but now some high-volume products are available where the integration of the CMOS and the MEMS is done as part of the wafer-level capping process. Also, anodic bonding typically requires a maximum process temperature of over 400 ̊C and the presence of a strong electric field during bonding. The high temperature influences the throughput of the bonding process and some devices cannot tolerate the high electric field.

Even though the majority of the MEMS parts that exist today were probably bonded using glass frit, this wafer bonding process has several challenges as well. The major one is that the glass frit is applied and patterned using a silk screen process, which has a typical resolution in the 250 to 300μm range. This means that as the size of the MEMS die decreases, an ever greater percentage of the wafer surface is consumed by the bond line, which limits the number of die per wafer and increases the cost per die. FIGURE 1 shows the effect of bond line width and die size on the percentage of the wafer surface that is consumed by the bond line [1]. Also, many of the glass frits contain Pb to lower the glass transition temperature. Although the amount of Pb is very small, there is widespread concern regarding the use of Pb and being RoHS (Restriction of Hazardous Substance) compliant.

Wafer bonding 1


Both anodic bonding and glass frit bonds are nonconductive and therefore not suitable for the formation of connections to electrically conductive through silicon vias (TSVs) at the same time as the seal ring is formed. This means that these processes are not as suitable for the 3D integration of CMOS and MEMS.

For MEMS applications there is a strong trend toward the use of metal-based wafer bonding; in particular, liquid metal-based processes such as solder, eutectic and transient liquid phase (TLP). This trend is driven by the aforementioned challenges with anodic and glass frit bonding. Moving from glass frit to a metal-based bonding for a die size of 2mm2 can result in up to a 100% increase in the die per wafer. This doubling of the die per wafer will result in an approximately 50% decrease in the cost per MEMS die.

Some of the metal-based aligned-wafer-bonding processes that are currently used in high-volume manufacturing are: Au-Au thermo-compression bonding, which has been in volume production for over 10 years; and Al-Ge eutectic bonding, which is very popular even though it requires a very careful process setup and control and has a peak process temperature of over 400 ̊C. Cu-Sn transient liquid phase (TLP) wafer bonding, another metal-based process, is used in low-volume production of hermetically sealed devices such as micro-bolometers [2] but is not currently used in medium- or high-volume production. Cu-Sn TLP wafer bonding also requires very careful design and control of the metal stack as well as the bonding process.

The maximum process temperature that is required for a bonding process has three significant effects. The first is that the bonding process takes longer as the maximum process temperature increases due to the increased time required to heat up to the bonding temperature from the loading temperature and the time required to cool down to the unload temperature. The bonding process time determines the throughput of the wafer bonder(s) and factors into the cost of ownership (CoO) for the bonding process. The second is that the process temperature required for bonding may damage the devices on the wafers being bonded. The aluminum metallization of certain CMOS devices may be damaged at tempera- tures greater than 450 ̊C. The VOx or vanadium oxide used on the sensor pixels for micro-bolometers will be damaged by temperatures greater than 200 ̊C. The third is the internal stress that is created when wafers with mismatched coefficients of thermal expansion (CTE) are bonded together at an elevated temperature. In this case the higher the bonding temperature, the higher the internal stress at room temperature.

Unless the bonding metals are noble metals such as Au, oxides will form on the metal layer and have a negative effect on the bonding process – making an oxide management strategy necessary. This oxide management strategy can have elements that prevent the oxide from growing using special storage conditions or coatings, removing the oxide before bonding, and heating in an inert or reducing environment. In some cases, the bonding process can also be adjusted to overcome the effect of the oxides by increasing the pressure, temperature and time for the bonding process.

There is substantial interest in bonding processes and equipment that are capable of removing the native oxide from metals and other materials prior to wafer bonding and preventing the regrowth of oxide. Equipment capable of running such a process will have several substantial advantages. The first is that it will allow materials that have been previously difficult to bond to be bonded at or near room temperature. For example, Al-Al thermo-compression wafer bonding without the removal of the native oxide has previously been demonstrated, but required a process temperature of greater than 500 ̊C, which made the process unattractive for production [3]. Low temperature Al-Al thermo-compression bonding has been demonstrated by using a special surface treatment and doing all handling in a high vacuum environment (FIGURE 2). A low-temperature Al-Al thermo-compression bonding process has the advantage of using an inexpensive readily available conductive material and increased throughput due to the low process temperature. In addition to being used to form the seal ring, this low-temperature Al-Al bonding could be used for the 3D integration of MEMS and CMOS through the use of TSVs filled with Al.

Wafer bonding 2

This surface pretreatment and handling in high vacuum enables covalent bonding of two wafers at or near room temperature with no oxide in the interface. This process has several very significant advantages. The first is that the low process temperature allows the bonding of substrates with substantially different CTE such as LiNbO3 or LiTaO3 to Si or glass. This combination of materials has drawn the interest of RF filter manufacturers due to its ability to reduce the temperature sensitivity of surface acoustic wave (SAW) devices. The second is that materials with both a CTE mismatch and a lattice mismatch can be bonded together without the development of major crystalline defects that can arise when forming the material stack by growing one crystalline layer on top of another when there is a lattice mismatch. One interesting possibility is bonding GaN to diamond for applications where large amounts of heat must be removed from the GaN device. In addition, bonding a thin layer of monocrystalline SiC to a polycrystalline SiC could offer wafers with the electrical performance of monocrystalline SiC at a cost closer to the cost of polycrystalline SiC. Another application of this bonding process is to join materials such as GaInP, GaAs, GaInAsP and GaInAs for fabrication of quadruple junction concentrated solar cells with record conversion efficiency of 44.7% [4, 5].

A high-vacuum cluster tool capable of aligned wafer bonding offers significant advantages for MEMS applications where the vacuum level in the cavity after bonding is important, such as gyroscopes and micro-bolometers (FIGURE 3) [6]. Modules can be added to the base cluster tool to enable the wafers to be baked out at a controlled elevated temperature prior to alignment and bonding in high vacuum. Getter activation can also be done in the bake-out module without loading or saturating the getter, as all subsequent steps are done in high vacuum. For devices where getter activation requires a high temperature and the other wafer has thermal limits, two bake-out chambers allow a high-temperate bake-out and getter activation while the other chamber performs a lower-temperature bake out. For example, micro-bolometers that used vanadium oxide on the detector pixel have a thermal limit of about 200 ̊C, whereas the cap wafer contains a getter that should be activated around 400 ̊C. Also, the high-vacuum capability is beneficial for producing devices that are heated and use vacuum for thermal isolation because a higher vacuum reduces the heat loss, which reduces the power required to maintain the fixed temperature.

Wafer bonding 3

This high-vacuum cluster tool allows the separation of the process steps of bake out, surface treatment, alignment and bonding as well as allows the tool to be configured to the specific application needs. Also, the cluster tool base makes it possible to develop modules for specific applications without redesigning the entire tool.

The availability of reliable, highly automated, high-volume aligned wafer bonding systems and processes was one of the keys to the growth of MEMS over the past 15 years. The next 15 years are expected to be an exciting period of advancement for aligned wafer bonding as new equipment and processes are introduced, such as the tools and processes that allow separate pre-processing of the top and bottom wafer, as well as all handling, alignment, and bonding in vacuum. The cluster tools that will be used to do this will allow for further innovation by adding new modules to the cluster tool. In addition, the ability to remove surface oxides prior to bonding, prevent these oxides from reforming, bond at or near room temperature, and have a strong, oxide-free, optically transparent, conductive bond with very low metal contamination will allow many new product innovations for RF filters, power devices and even products that have not yet been thought of.


1. E. F. Pabo, “Metal Based Bonding – A Potential Cost Reducer?,” in MEMS MST Industry Conference, Dresden, 2011.
2. A. Lapadatu, “High Performance Long Wave Infrared Bolometer Fabricated by Wafer Bonding,” Proc. SPIE, vol. 7660, no. 766016-12.
3. E.Cakmak,“Aluminum Thermocompression Bonding Characterization,” in MRS Fall Mtg, Boston, 2009.
4. Fraunhofer ISE, Fraunhofer ISE Teams up with EVGroup to Enable Direct Semiconductor Wafer Bonds for Next-Generation Solar Cells, Freiburg: Press Release, 2013.
5. F. Dimroth, “Wafer bonded four-junction GaInP/GaAa/GaInAsP/ GaInAs,” Progress in Photonics, vol. 22, no. 3, pp. 277-282, 2014.
6. V.Dragoi,“Wafer Bonding for Vacuum Encapsulated MEMS,” Proc. SPIE9517 Smart Sensor, Actuators, and MEMS VII, 2015.

ERIC F. PABO is Business Development Manager, MEMS; CHRISTOPH FLÖTGEN, and BERNHARD REBHAN are scientists, PAUL LINDNER is Executive Technology Director and THOMAS UHRMANN is Director Of Business Development at EV Group, St. Florian, Austria


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One thought on “Wafer bonding for high performance MEMS, power devices, and RF components

  1. MP Divakar

    Excellent article, quite informative. I am intrigued by the statement “One interesting possibility is bonding GaN to diamond for applications where large amounts of heat must be removed from the GaN device.” Has there been any trials on this by EVG? Thanks,
    MP Divakar, PhD

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