Yearly Archives: 2015

An important step towards next-generation ultra-compact photonic and optoelectronic devices has been taken with the realization of a two-dimensional excitonic laser. Scientists with the U.S. Department of Energy (DOE)’s Lawrence Berkeley National Laboratory (Berkeley Lab) embedded a monolayer of tungsten disulfide into a special microdisk resonator to achieve bright excitonic lasing at visible light wavelengths.

“Our observation of high-quality excitonic lasing from a single molecular layer of tungsten disulfide marks a major step towards two-dimensional on-chip optoelectronics for high-performance optical communication and computing applications,” says Xiang Zhang, director of Berkeley Lab’s Materials Sciences Division and the leader of this study.

Zhang, who also holds the Ernest S. Kuh Endowed Chair at the University of California (UC) Berkeley and is a member of the Kavli Energy NanoSciences Institute at Berkeley (Kavli ENSI), is the corresponding author of a paper describing this research in the journal Nature Photonics. The paper is titled “Monolayer excitonic laser“. The lead authors are Yu Ye and Zi Jing Wong, members of Zhang’s research group, plus Xiufang Lu, Xingjie Ni, Hanyu Zhu, Xianhui Chen and Yuan Wang.

A single molecular layer of tungsten (W) and sulfide (S) is widely regarded as one of the most promising 2D semiconductors for photonic and optoelectronic applications. (Credit: Xiang Zhang, Berkeley Lab)

A single molecular layer of tungsten (W) and sulfide (S) is widely regarded as one of the most promising 2D semiconductors for photonic and optoelectronic applications. (Credit: Xiang Zhang, Berkeley Lab)

Among the most talked about class of materials in the world of nanotechnology today are two-dimensional (2D) transition metal dichalcogenides (TMDCs). These 2D semiconductors offer superior energy efficiency and conduct electrons much faster than silicon. Furthermore, unlike graphene, the other highly touted 2D semiconductor, TMDCs have natural bandgaps that allow their electrical conductance to be switched “on and off,” making them more device-ready than graphene. Tungsten disulfide in a single molecular layer is widely regarded as one of the most promising TMDCs for photonic and optoelectronic applications. However, until now, coherent light emission, or lasing, considered essential for “on-chip” applications, had not been realized in this material.

“TMDCs have shown exceptionally strong light-matter interactions that result in extraordinary excitonic properties,” Zhang says. “These properties arise from the quantum confinement and crystal symmetry effect on the electronic band structure as the material is thinned down to a monolayer. However, for 2D lasing, the design and fabrication of microcavities that provide a high optical mode confinement factor and high quality, or Q, factor is required.”

In a previous study, Zhang and his research group had developed a “whispering gallery microcavity” for plasmons, electromagnetic waves that roll across the surfaces of metals. Based on the principle behind whispering galleries – where words spoken softly beneath a domed ceiling can be clearly heard on the opposite side of the chamber – this micro-sized metallic cavity for plasmons strengthened and greatly enhanced the Q factor of light emissions. In this new study, Zhang and his group were able to adapt this microcavity technology from plasmons to excitons – photoexcited electrons/hole pairs within a single layer of molecules.

In this 2D excitonic laser, the sandwiching of a monolayer of tungsten disulfide between the two dielectric layers of a microdisk resonator creates the potential for ultralow-threshold lasing. (Credit: Xiang Zhang, Berkeley Lab)

In this 2D excitonic laser, the sandwiching of a monolayer of tungsten disulfide between the two dielectric layers of a microdisk resonator creates the potential for ultralow-threshold lasing. (Credit: Xiang Zhang, Berkeley Lab)

“For our excitonic laser, we dropped the metal coating and designed a microdisk resonator that supports a dielectric whispering gallery mode rather than a plasmonic mode, and gives us a high Q factor with low power consumption,” says co-lead author Ye. “When a monolayer of tungsten disulfide – serving as the gain medium – is sandwiched between the two dielectric layers of the resonator, we create the potential for ultralow-threshold lasing.”

In addition to its photonic and optoelectronic applications, this 2D excitonic laser technology also has potential for valleytronic applications, in which digital information is encoded in the spin and momentum of an electron moving through a crystal lattice as a wave with energy peaks and valleys. Valleytronics is seen as an alternative to spintronics for quantum computing.

“TMDCs such as tungsten disulfide provide unique access to spin and valley degrees of freedom,” says co-lead author Wong. “Selective excitation of the carrier population in one set of two distinct valleys can further lead to lasing in the confined valley, paving the way for easily-tunable circularly polarized lasers. The demand for circularly polarized coherent light sources is high, ranging from three-dimensional displays to effective spin sources in spintronics, and information carriers in quantum computation.”

This research was supported by the United States Air Force Office of Scientific Research and by the DOE Office of Science through the Light-Material Interaction in Energy Conversion Energy Frontier Research Center.

North America-based manufacturers of semiconductor equipment posted $1.60 billion in orders worldwide in September 2015 (three-month average basis) and a book-to-bill ratio of 1.07, according to the September EMDS Book-to-Bill Report published today by SEMI. A book-to-bill of 1.07 means that $107 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in September 2015 was $1.60 billion. The bookings figure is 4.1 percent lower than the final August 2015 level of $1.67 billion, and is 35.1 percent higher than the September 2014 order level of $1.19 billion.

The three-month average of worldwide billings in September 2015 was $1.50 billion. The billings figure is 4.6 percent lower than the final August 2015 level of $1.58 billion, and is 19.7 percent higher than the September 2014 billings level of $1.26 billion.

“Both bookings and billings trended slightly lower in the September three-month average compared to August,” said Denny McGuirk, president and CEO of SEMI. “While year-to-date billings through the first three quarters are above 2014 billings, uncertainty with semiconductor demand has dampened expectations with capex plans in the near-term.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars. (Source: SEMI, October 2015.)

  Billings
(3-mo. avg)		 Bookings
(3-mo. avg)		 Book-to-Bill
April 2015 $1,515.3 $1,573.7 1.04
May 2015 $1,557.3 $1,546.2 0.99
June 2015 $1,554.9 $1,517.4 0.98
July 2015 $1,556.2 $1,587.3 1.02
August 2015 (final) $1,575.9 $1,670.1 1.06
September 2015 (prelim) $1,503.9 $1,602.3 1.07

The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

The data are contained in a monthly Book-to-Bill Report published by SEMI. The report tracks billings and bookings worldwide of North American-headquartered manufacturers of equipment used to manufacture semiconductor devices, not billings and bookings of the chips themselves. The Book-to-Bill report is one of three reports included with the SEMI Equipment Market Data Subscription (EMDS).

SEMI recently completed its annual silicon shipment forecast for the semiconductor industry. This forecast provides an outlook for the demand in silicon units for the period 2015–2017. The results show polished and epitaxial silicon shipments totaling 10,042 million square inches in 2015; 10,179 million square inches in 2016; and 10,459 million square inches in 2017 (refer to table below). Total wafer shipments this year are expected to exceed the market high set in 2014 and are forecast to continue shipping at record levels in 2016 and 2017.

“2015 has been a record-breaking year for silicon shipments, attributed primarily to larger diameter wafers,” said Denny McGuirk, president and CEO of SEMI. “The outlook for the next two years is measured, but continues on a modest growth path.”

2015 Silicon Shipment Forecast
Total Electronic Grade Silicon Slices* – Does not Include Non-Polished
(Millions of Square Inches, MSI)

Actual Forecast
2013 2014 2015 2016 2017
MSI 8,834 9,826 10,042 10,179 10,459
Annual Growth 0% 11% 2% 1% 3%

Source: SEMI, October 2015; * Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers shipped by the wafer manufacturers to the end-users. Data do not include non-polished or reclaimed wafers.

For more information on the SEMI Worldwide Silicon Wafer Shipment Statistics, visit www.semi.org/en/MarketInfo/SiliconShipmentStatistics.

Slowing China economy, strong U.S. dollar, and falling DRAM ASPs all contributing to weaker IC market outlook.

IC Insights recently released its October Update to The McClean Report, which examined the effects of slowing worldwide GDP growth and a stronger U.S. dollar on the 2015 IC market forecast.

Since all of IC Insights’ figures are presented in U.S. dollars, a strengthening U.S. currency deflates foreign sales and market results while a weakening U.S. dollar serves to inflate the sales and market figures. The rare occurrence of significant strengthening of the U.S. dollar versus most of the major currencies this year is expected to deflate the 2015 worldwide IC market growth rate by at least three full percentage points. This “deflation” presents itself in the form of lower IC average selling prices (ASPs), which are forecast to register a steep 5% decline this year when reported in U.S. dollars.

Figure 1 compares the worldwide monthly IC market figures from January through August of 2015 and 2014. As shown, the beginning of this year started out very strong with the January 2015/2014 IC market showing year-over-year growth of more than 10%. In total, the 1Q15 IC market ended up 6.5% higher than the 1Q14 worldwide IC market.

The second quarter of 2015 began by registering similar monthly year-over-year IC market growth that was displayed in 1Q15, with the combined 2015 April and May IC markets up 5.6% compared to the combined April and May IC markets in 2014. However, things began to change in June as the IC market ended up 3.1% lower than the June 2014 IC market. Unfortunately, as shown in Figure 1, the 2015 July and August worldwide IC markets followed the disappointing year-over-year trend that began in June.

It should be noted that the average second half versus first half of the year growth rate in the IC market since 1990 is 9.2%. However, IC Insights is forecasting that the 2H15 IC market will be down 1.0% as compared to 1H15. If this occurs, it would be only the fifth time since 1990 that the second half of the year IC market was worse than the first half (the other years being 1996, 2001, 2008, and 2011). This weak second half market has resulted in IC Insights lowering its full-year 2015 IC market forecast from +1% to -1%.

Figure 1

Figure 1

Looking ahead to 2016, three reasons lead IC Insights to believe that the worldwide IC market will register mid-single digit growth next year:

  1. The current excess IC inventory is forecast to be under control by early next year.
  2. Worldwide GDP growth in 2016 is expected to show some improvement as compared to 2015.
  3. The U.S. dollar is unlikely to show nearly as much strength against the major foreign currencies next year as it did this year.

IC Insights will present its detailed 2015-2019 IC market forecast by product type in the November Update to The McClean Report.

 

Caen, Oct. 22, 2015 – Two years after the launch of the PICS project (funded by the FP7 funding instrument dedicated to research for the benefit of SMEs), three European SMEs, IPDiA, Picosun, and SENTECH Instruments along with CEA-Leti and Fraunhofer IPMS-CNT announce the major technological results achieved during this program.

Started in September 2013, the PICS project was focused on developing innovative dielectric materials deposited by atomic layer deposition (ALD) and related tools (ALD batch tool and etching tool) to bring to mass production a new technology of high- density and high-voltage 3D trench capacitors targeting high-end markets like medical or aeronautics. Capacitors are key components presented in every electronic module. The integrated silicon capacitors technology offered by the SME IPDiA outperforms current technologies (using ceramic or tantalum substrates) in stability in temperature, voltage, aging and reliability and enables to build highly integrated and high-performance electronic modules.

The consortium’s three major technological results are:

  • A novel ALD batch tool was developed by Picosun and Fraunhofer IPMS-CNT. It enables to reduce cost-of-ownership and deliver better uniformity and step coverage for high-K dielectrics into 3D structures. With its demonstrated, optimized, and production-proven ALD processes, Picosun is solidifying its position as a technological leader in the IC, Semiconductor, MEMS markets, from R&D to production systems.
  • A new process for accurately etching high-K dielectrics, which are very specific materials, was demonstrated by SENTECH with the help of Fraunhofer IPMS-CNT. As a result, SENTECH has the potential to gain market share in the field of high-k materials, which have high interest for different applications, e.g. LED, MEMS, magnetic data storage.
  • Two new dielectric stacks were developed and integrated into the IPDiA 3D trench capacitors by IPDiA, CEA-Leti and Fraunhofer IPMS-CNT. The initial specifications were fulfilled and proven by electrical measurements. A new record on capacitance density (>500nF/mm² at 3.3V) and an extended operation voltage (10V with 150nF/mm²) were obtained, which expands IPDiA’s ability to meet current market requirements particularly in the field of medical or aeronautics. Qualification procedure was initiated during the project by launching preliminary reliability studies and it will continue in the coming months.

On top of these R&D results, the other main objective of PICS was the industrialization of this new integrated capacitors technology. Thanks to the partnerships set up, the manufacturability and financial viabilities were ensured by developing adequate industrial tools targeting mass production.

The PICS project is a success for all three SMEs and a good example of the benefits brought by the EU funding instrument “Research for the benefit of SMEs”. The SMEs were able to outsource a part of their research to get from RTD performers innovative know-how and cutting-edge technological processes. The project was built to answer the SMEs’ specific needs and a common goal was set up around the new IPDiA capacitors technology and the specific tools (ALD batch tool and etching) required for its commercial exploitation.

 

A report that resulted from a workshop funded by Semiconductor Research Corporation (SRC) and National Science Foundation (NSF) outlines key factors limiting progress in computing—particularly related to energy consumption—and novel device and architecture research that can overcome these barriers. A summary of the report’s findings can be found at the end of this article; the full report can be accessed here.

The findings and recommendations in the report are in alignment with the nanotechnology-inspired Grand Challenge for Future Computing announced on October 20 by the White House Office of Science and Technology Policy. The Grand Challenge calls for new approaches to computing that will operate with the efficiency of the human brain. It also aligns with the National Strategic Computing Initiative (NSCI) announced by an Executive Order signed by the President on July 29.

Energy efficiency is vital to improving performance at all levels. This includes from devices and transistors to large IT systems, as well from small sensors at the edge of the Internet of Things (IoT) to large data centers in cloud and supercomputing systems.

“Fundamental research on hardware performance, complex system architectures, and new memory/storage technologies can help to discover new ways to achieve energy-efficient computing,” said Jim Kurose, the Assistant Director of the National Science Foundation (NSF) for Computer and Information Science and Engineering (CISE). “Partnerships with industry, including SRC and its member companies, are an important way to speed the adoption of these research findings.”

Performance improvements today are limited by energy inefficiencies that result in overheating and thermal management issues. The electronic circuits in computer chips still operate far from any fundamental limits to energy efficiency, and much of the energy used by today’s computers is expended moving data between memory and the central processor.

At the same time as increases in performance slow, the amount of data being produced is exploding. By 2020, an estimated 44 zettabytes of data (1 zettabyte equals 1 trillion gigabytes) will be created on an annual basis.

“New devices, and new architectures based on those devices, could take computing far beyond the limits of today’s technology. The benefits to society would be enormous,” said Tom Theis, Nanoelectronics Research Initiative (NRI) Executive Director at SRC, the world’s leading university-research consortium for semiconductor technologies.

Inspired by the neural architecture of a macaque brain, this neon swirl is the wiring diagram for a new kind of computer that, by some definitions, may soon be able to think. (Credit: Emmett McQuinn, IBM Research - Almaden)

Inspired by the neural architecture of a macaque brain, this neon swirl is the wiring diagram for a new kind of computer that, by some definitions, may soon be able to think. (Credit: Emmett McQuinn, IBM Research – Almaden)

In order to realize these benefits, a new paradigm for computing is necessary. A workshop held April 14-15, 2015 in Arlington, Va., and funded by SRC and NSF convened experts from industry, academia and government to identify key factors limiting progress and promising new concepts that should be explored. The report being announced today resulted from the workshop discussions and provides a guide to future basic research investments in energy-efficient computing.

The report builds upon an earlier report funded by the Semiconductor Industry Association, SRC and NSF on Rebooting the IT Revolution.

To achieve the Nanotechnology Grand Challenge and the goals of the NSCI, multi-disciplinary fundamental research on materials, devices and architecture is needed. NSF and SRC, both individually and together, have a long history of supporting long-term research in these areas to address such fundamental, high-impact science and engineering challenges.

Report Findings

Broad Conclusions

Research teams should address interdisciplinary research issues essential to the demonstration of new device concepts and associated architectures. Any new device is likely to have characteristics very different from established devices. The interplay between device characteristics and optimum circuit architectures therefore means that circuit and higher level architectures must be co-optimized with any new device. Devices combining digital and analog functions or the functions of logic and memory may lend themselves particularly well to unconventional information processing architectures. For maximum impact, research should focus on devices and architectures which can enable a broad range of useful functions, rather than being dedicated to one function or a few particular functions.

Prospects for New Devices

Many promising research paths remain relatively unexplored. For example, the gating of phase transitions is a potential route to “steep slope” devices that operate at very low voltage. Relevant phase transitions might include metal-insulator transitions, formation of excitonic or other electronic condensates, and various transitions involving structural degrees of freedom. Other promising mechanisms for low-power switching may involve transduction. Magnetoelectric devices, in which an external voltage state is transduced to an internal magnetic state, exemplify the concept. However, transduction need not be limited to magnetoelectric systems.

In addition to energy efficiency, switching speed is an important criterion in choice of materials and device concepts. For example, most nanomagnetic devices switch by magnetic precession, a process which is rather slow in the ferromagnetic systems explored to date. Magnetic precession switching in antiferromagnetic or ferrimagnetic materials could be one or more orders of magnitude faster. Other novel physical systems could be still faster. For example, electronic collective states could, in principle, be switched on sub-picosecond time scales.

More generally, devices based on computational state variables beyond magnetism and charge (or voltage) could open many new possibilities.

Another relatively unexplored path to improved energy efficiency is the implementation of adiabatically switched devices in energy-conserving circuits. In such circuits, the phase of an oscillation or propagating wave may represent digital state; devices and interconnections must together constitute circuits that are non-dissipative. Nanophotonic, plasmonic, spin wave or other lightly damped oscillatory systems might be well-suited for such an approach. Researchers should strive to address the necessary components of a practical engineering solution, including mechanisms for correction of unavoidable phase and amplitude errors.

Networks of coupled non-linear oscillators have been explored for non-Boolean computation in applications such as pattern recognition. Potential technological approaches include nanoelectromechanical, nanophotonic, and nanomagnetic oscillators. Researchers should strive for generality of function and should address the necessary components of a practical engineering solution, including devices, circuits, and architectures that allow reliable operation in the presence of device variability and environmental fluctuations.

Prospects for New Architectures

While appropriate circuits and higher level architectures should be explored and co-developed along with any new device concept, certain novel device concepts may demand greater emphasis on higher-level architecture. For example, hysteretic devices, combining the functions of non-volatile logic and memory, might enhance the performance of established architectures (power gating in microprocessors, reconfiguration of logic in field programmable gate arrays), but perhaps more important, they might play an enabling role in novel architectures (compute in memory, weighting of connections in neuromorphic systems, and more). As a second example, there has been great progress in recent years in the miniaturization and energy efficiency of linear and non-linear photonic devices and compact light emitters. It is possible that these advances will have their greatest impact, not in the ongoing replacement of metal wires by optical connections, but rather in enabling new architectures for computing. Computation “in the network” is one possible direction. In general, device characteristics and architecture appear to be highly entwined in oscillatory or energy-conserving systems. Key device characteristics may be inseparable from the coupling (connections) between devices. For non-Boolean computation, optimum architectures and the range of useful algorithms will depend on these characteristics.

In addition to the examples above, many other areas of architectural research might leverage emerging device concepts to obtain order of magnitude improvements in the energy efficiency of computing. Research topics might include architectures for heterogeneous systems, architectures that minimize data movement, neuromorphic architectures, and new approaches to Stochastic Computing, Approximate Computing, Cognitive Computing and more.

SUNNYVALE, Calif. – OCT 21, 2015 – Advanced Linear Devices, Inc. (ALD), a design innovation leader in analog semiconductors, today announced a family of Supercapacitor Auto Balancing (SAB™) Metal Oxide Semiconductor Field Effect Transistors (MOSFET) designed for industrial applications to regulate and balance leakage currents while minimizing energy used for balancing supercapacitor cells stacked in series stack of two or more.

The devices are ideal for a number of industrial-grade energy storage applications that require an operating temperature range between -40 to 85 degrees Celsius. The devices are ideally suited for a range of applications such as remote monitoring applications, automotive systems, backup power, transportation, automation, or any application that operates in exposure to the elements and needs to endure extreme climate conditions.

In outdoor industrial energy storage, leakage current of supercapacitors used in a stack is balanced by connecting one or more SAB MOSFETs across each cell. Leakage current balancing is critical to prevent damage to cells from over voltage that can dramatically shorten supercapacitor operating life.

“ALD’s industrial-grade SAB MOSFETS are designed to withstand a greater range of ambient temperature differential, and are therefore more reliable under greater stresses,” said Robert Chao, President and CEO of Advanced Linear Devices, Inc.

“Operators of industrial grade systems demand the utmost in reliability so all of the components used must be able to withstand harsh environmental elements and climates,” Mr. Chao added.

MOSFETs_thumbEach device in the industrial SAB MOSFET ALD8100xxx/ALD9100xxx family contains 26 different products and each product can balance supercapacitor up to 4 cells in a single IC package. Starting with two cells, the devices can balance an unlimited number of supercapacitor cells stacked in a series.

Each device in the SAB MOSFET family dissipates near zero leakage current to eliminate extra power dissipation. They provide a superior circuit design alternative to passive or active balancing methods by offering automatic active leakage current regulation. As an alternative to op-amp based schemes, the high voltage SAB MOSFET arrays can reduce board space, and lower cost while enhancing system and component lifespan.

SAB MOSFETs connected across these supercapacitors exhibit complementary opposing current levels, resulting in little or no additional leakage currents other than those caused by the supercapacitors themselves.

Leakage current differences in series stacked supercapacitor make it difficult to control respective cell voltages. This causes one or more supercapacitor to exceed its rated voltage over time, which reduces lifespan by rupturing materials inside each cell. Eventually this leads to catastrophic failure, which can begin over days, weeks, or months.

The voltage dependent characteristic of the ALD810019xxx/ALD91001xxx on-resistance controls excessive voltage rise of each individual supercapacitor cell. In series-connected stacks, when one supercapacitor voltage rises, the voltage of the other supercapacitors drops. The supercapacitors that have the highest leakage currents also have the lowest voltages. By increasing drain current exponentially when voltages increase, and by decreasing drain current exponentially when voltages decrease, the MOSFET arrays automatically regulate the voltage across each supercapacitor cell.

The products offer different threshold voltages for various supercapacitor operating voltages and leakage current characteristics which diminishes energy spent in balancing the circuits. The new device family covers a wide range of operating voltages from 1.6V to 2.7V and leakage current ranges from <0.3nA to >3000μA.

Available in both quad and dual packages, the industrial SAB MOSFETs are made with ALD’s precision EPAD® technology.

Lam Research Corporation (LRCX) and KLA-Tencor Corporation (KLAC) today announced that they have entered into a definitive agreement for Lam Research to acquire all outstanding KLA-Tencor shares in a cash and stock transaction. The move, unanimously approved by the boards of directors of both companies, will create a combined company with approximately $8.7 billion in pro forma annual revenue.

The combined company expects to realize $250 million in cost savings within 18 to 24 months of closing, and anticipates gaining approximately $600 million in incremental revenue by 2020 through improved differentiation of each company’s products and creation of new capabilities.

“This is just what the doctor ordered,” Srini Sundararajan, Semiconductor and Semicaps Analyst for W.R. Hambrecht + Co./Summit Research, wrote in an analysis of the move. “It removes excessive dependence of LRCX on memory and excessive dependence of KLAC on foundry/logic.”

According to the LRCX press release, “the combination will create unmatched capability in process and process control, delivering optimized results in partnership with its customers by reducing variability and accelerating yield, ultimately helping the semiconductor industry extend Moore’s Law and performance scaling generally.”

“The pairing of Lam Research and KLA-Tencor brings industry leadership in process and process control together, accelerating our capability to address our customers’ most difficult challenges as they scale to meet the market demands of lower power, higher performance, and smaller form factors,” said Martin Anstice, Lam’s president and chief executive officer. “Lam Research and KLA-Tencor’s shared commitment to collaboration and building strong customer trust, along with our respective track records of innovation, product leadership, and operational excellence, position us as a combined company to deliver the higher levels of technology differentiation and speed to solutions that are critical to our customers’ long-term success.”

“I strongly believe that this transaction represents a great outcome for all of KLA-Tencor’s key stakeholders,” said Rick Wallace, president and chief executive officer of KLA-Tencor. “The combined company will be uniquely positioned to work collaboratively with our customers to help them meet the challenges of FinFET, multi-patterning and 3D NAND development.  Given the complementary nature of the two companies’ product offerings and technologies as well as the lack of product overlap, the combination will create an industry leader with greater opportunities for our respective employees for professional development and growth. Lastly, this transaction will benefit our stockholders who will receive compelling upfront value, in addition to the opportunity to own a meaningful stake in an industry leader and participate in the upside potential created by the combination.”

According to the press release, the transaction is expected to close in mid-calendar year 2016, pending customary regulatory approvals. The transaction is also subject to customary closing conditions, including the adoption by KLA-Tencor’s stockholders of the merger agreement and the approval by Lam Research’s stockholders of the issuance of shares in the transaction. Given their complementary product lines and the industry benefits the transaction will enable, the companies believe that they will be able to obtain the requisite regulatory approvals on a timely basis.

Analyst Sundararajan agrees: “We expect minimal opposition to this deal from the various jurisdictions, rather easily handled.”

However, Robert Maire of Semiconductor Advisors thinks approval could potentially be more difficult. “We think this is going to be the obvious biggest issue after the failed AMAT & TEL merger.  We think there will likely be opposition in the semi industry but probably less so than we heard the screaming related to AMAT/TEL,” he wrote. “While maybe not overjoyed, the combination makes a lot of sense for customers and feels a lot less negative than the failed AMAT/TEL.”

According to the press release, some of the benefits the combined company expects to see are:

  • Creates Premier Semiconductor Capital Equipment Company: Strengthened platform for continued outperformance, combining Lam’s best-in-class capabilities in deposition, etch, and clean with KLA-Tencor’s leadership in inspection and metrology
  • Accelerated Innovation: Increased opportunity and capability to address customers’ escalating technical and economic challenges
  • Broadened Market Relevance: Comprehensive and complementary presence across market segments provides diversity, scale and value creating innovation opportunities
  • Significant Cost and Revenue Synergies: Approximately $250 million in expected annual on-going pre-tax cost synergies within 18-24 months of closing the transaction, and $600 million in annual revenue synergies by 2020
  • Accretive Transaction: Increased non-GAAP EPS and free cash flow per share during the first 12 months post-closing
  • Strong Cash Flow: Complementary memory and logic customer base, operational strength, and meaningful installed base revenues strengthen cash generation capability

According to Sundararajan, the move could have negative impacts for some other companies in the industry. “This deal is quite negative for Applied Materials (AMAT) and Hermes Microvision and perhaps for ASML also,” he wrote. “In the case of AMAT, their process diagnostics and control division being based in Israel does not allow of meshing of capabilities, and product synergies really don’t exist.  In the case of Hermes Microvision, since etch is the pre-dominant user of e-beam inspection due to testing of contacts, a combination of KLAC and LRCX with both e-beam and etch capabilities can be lethal.”

Maire also foresees difficulties for competitors: “The combined LAM and KLA creates a powerhouse in the semicap industry, which is looking a lot more like a duopoly.”

Lam president and CEO Anstice concluded, “We have tremendous respect for the company KLA-Tencor employees have built over nearly 40 years — their culture, technology, and operating practices. I have no doubt that our combined values, focus on the customer, and complementary technologies will create a trusted leader in our industry, capable of creating significant opportunity for profitable growth and in turn delivering tremendous value to all of our stakeholders. This is the right time for the right combination in our industry.”

Western Digital Corporation and SanDisk Corporation today announced that they have entered into a definitive agreement under which Western Digital will acquire all of the outstanding shares of SanDisk for a combination of cash and stock. The offer values SanDisk common stock at $86.50 per share or a total equity value of approximately $19 billion, using a five-day volume weighted average price ending on October 20, 2015 of $79.60 per share of Western Digital common stock. If the previously announced investment in Western Digital by Unisplendour Corporation Limited closes prior to this acquisition, Western Digital will pay $85.10 per share in cash and 0.0176 shares of Western Digital common stock per share of SanDisk common stock; and if the Unisplendour transaction has not closed or has been terminated, $67.50 in cash and 0.2387 shares of Western Digital common stock per share of SanDisk common stock. The transaction has been approved by the boards of directors of both companies.

The combination is the next step in the transformation of Western Digital into a storage solutions company with global scale, extensive product and technology assets, and deep expertise in non-volatile memory (NVM). With this transaction, Western Digital will double its addressable market and expand its participation in higher-growth segments. SanDisk brings a 27-year history of innovation and expertise in NVM, systems solutions and manufacturing. The combination also enables Western Digital to vertically integrate into NAND, securing long-term access to solid state technology at lower cost.

The proposed combination creates significant value for both SanDisk and Western Digital shareholders. Western Digital brings a successful track record of M&A with a number of acquisitions over the last several years helping to fuel innovation, create value and strongly position the company to capture higher-growth opportunities. In addition, Western Digital’s operational excellence, coupled with the recently announced decision by China’s Ministry of Commerce (MOFCOM) allowing Western Digital to integrate substantial portions of its WD and HGST businesses, is expected to generate additional cost synergies.

“This transformational acquisition aligns with our long-term strategy to be an innovative leader in the storage industry by providing compelling, high-quality products with leading technology,” said Steve Milligan, chief executive officer, Western Digital. “The combined company will be ideally positioned to capture the growth opportunities created by the rapidly evolving storage industry. I’m excited to welcome the SanDisk team as we look to create additional value for all of our stakeholders, including our customers, shareholders and employees.”

“Western Digital is globally recognized as a leading provider of storage solutions and has a 45-year legacy of developing and manufacturing cutting-edge solutions, making the company the ideal strategic partner for SanDisk,” said Sanjay Mehrotra, president and chief executive officer, SanDisk. “Importantly, this combination also creates an even stronger partner for our customers. Joining forces with Western Digital will enable the combined company to offer the broadest portfolio of industry-leading, innovative storage solutions to customers across a wide range of markets and applications.”

Western Digital and SanDisk’s complementary product lines, including hard disk drives (“HDDs”), solid-state drives (“SSDs”), cloud datacenter storage solutions and flash storage solutions, will provide the foundation for a broader set of products and technologies from consumer to datacenter. Both companies have strong R&D and engineering capabilities and a rich base of fundamental technologies with over 15,000 combined patents issued or pending worldwide.

Toshiba has been a long-term strategic partner to SanDisk for 15 years. The joint venture (JV) with Toshiba will be ongoing, enabling vertical integration through a technology partnership driven by deep collaboration across design and process capabilities. The JV provides stable NAND supply at scale through a time-tested business model and extends across NVM technologies such as 3D NAND.

Steve Milligan will continue to serve as chief executive officer of the combined company, and the company will remain headquartered in Irvine, California. Upon closing, Sanjay Mehrotra is expected to join the Western Digital Board of Directors.

Led by a seasoned management team, Western Digital has a strong track record of integrating acquisitions to create value. The company expects to achieve full annual run-rate synergies of $500 million within 18 months post-closing. The transaction is expected to be EPS accretive on a non-GAAP basis within 12 months of the transaction close. Pending the closing of the transaction, Western Digital expects to continue paying its quarterly dividend and plans to suspend its share buyback program.

The transaction will be financed by a mix of cash, new debt financing and Western Digital stock.  In connection with the transaction, Western Digital expects to enter into new debt facilities totaling $18.4 billion, including a $1.0 billion revolving credit facility. The proceeds from the new debt facilities are expected to be used to pay part of the purchase price, refinance existing debt of Western Digital and SanDisk and pay transaction related fees and expenses. If SanDisk’s cash balance falls below certain thresholds at the time of transaction close, the merger agreement provides for an adjustment to the mix of cash and stock consideration.

The transaction is subject to approval by SanDisk shareholders and, in the event that the Unisplendor transaction does not close, Western Digital shareholders, receipt of regulatory approvals and other customary closing conditions. The transaction is expected to close in the third calendar quarter of 2016.

SEMI, the global industry association advancing the interests of the worldwide electronics supply chain, today published a new report, “Global 200mm Fab Outlook to 2018.” According to the report, worldwide 200mm semiconductor wafer fab capacity is forecast at 5.2 million wafer starts per month (wspm) in 2015 and expanding to 5.4 million wspm in 2018. In addition to the release of the report, SEMI is offering two complimentary webinars (November 2 at 5:00pm Pacific; November 3 at 8:00am Pacific) with highlights of the newly released 200mm report.

Based on the rapidly increasing number of internet-enabled mobile devices and the emergence of the IoT (Internet of Things), demand for sensors, MEMS, analog, power and related semiconductor devices is growing. While these devices are critical to enable the new era of computing, the applications do not require leading-edge manufacturing capability, and this demand is “breathing new life” into 200mm fabs.

Source: Global 200mm Fab Outlook, SEMI; October 2015

Source: Global 200mm Fab Outlook, SEMI; October 2015

Highlights of the results of the SEMI 200mm report include:

  • 36 facilities are expected to add 300,000 to 400,000 200mm wspm from 2015 through 2018.
  • Capacity investment is expected to total over US $3 billion during the 2015 to 2018 period.
  • Eight new facilities/lines are expected to begin operation from 2015 through 2018.
  • China and Southeast Asia are forecast to lead the expansion in 200mm fab capacity.

In this report, SEMI covers nearly 200 facilities using 200mm wafers, including facilities that are planned, under construction, installing new equipment, active, closing or closed, and fabs changing wafer size to and from 200mm. Analysis covers the years 1995 to 2018, with focus on developments in the recent past through 2018. The 80-page SEMI report offers graphs and tables in PDF slide format and details in Microsoft Excel. In addition, the report includes trend analysis for fab capacity and count; capacity additions for new and existing fabs; capacity loss for fabs closing or converting to other wafer sizes; 200mm equipment spending; and summary and highlights for each region.