Monthly Archives: April 2016

Converting a single photon from one color, or frequency, to another is an essential tool in quantum communication, which harnesses the subtle correlations between the subatomic properties of photons (particles of light) to securely store and transmit information. Scientists at the National Institute of Standards and Technology (NIST) have now developed a miniaturized version of a frequency converter, using technology similar to that used to make computer chips.

False-color scanning electron micrograph of a nanophotonic frequency converter, consisting of a ring-shaped resonator (shaded blue) into which light is injected using a waveguide (shaded red). The input signal, depicted as a purple arrow, is converted to a new frequency (blue arrow) through the application of two pump lasers (light and dark red arrows). Credit: K. Srinivasan et al./NIST

False-color scanning electron micrograph of a nanophotonic frequency converter, consisting of a ring-shaped resonator (shaded blue) into which light is injected using a waveguide (shaded red). The input signal, depicted as a purple arrow, is converted to a new frequency (blue arrow) through the application of two pump lasers (light and dark red arrows). Credit: K. Srinivasan et al./NIST

The tiny device, which promises to help improve the security and increase the distance over which next-generation quantum communication systems operate, can be tailored for a wide variety of uses, enables easy integration with other information-processing elements and can be mass produced.

The new nanoscale optical frequency converter efficiently converts photons from one frequency to the other while consuming only a small amount of power and adding a very low level of noise, namely background light not associated with the incoming signal.

Frequency converters are essential for addressing two problems. The frequencies at which quantum systems optimally generate and store information are typically much higher than the frequencies required to transmit that information over kilometer-scale distances in optical fibers. Converting the photons between these frequencies requires a shift of hundreds of terahertz (one terahertz is a trillion wave cycles per second).

A much smaller, but still critical, frequency mismatch arises when two quantum systems that are intended to be identical have small variations in shape and composition. These variations cause the systems to generate photons that differ slightly in frequency instead of being exact replicas, which the quantum communication network may require.

The new photon frequency converter, an example of nanophotonic engineering, addresses both issues, Qing Li, Marcelo Davanço and Kartik Srinivasan write in Nature Photonics. The key component of the chip-integrated device is a tiny ring-shaped resonator, about 80 micrometers in diameter (slightly less than the width of a human hair) and a few tenths of a micrometer in thickness. The shape and dimensions of the ring, which is made of silicon nitride, are chosen to enhance the inherent properties of the material in converting light from one frequency to another. The ring resonator is driven by two pump lasers, each operating at a separate frequency. In a scheme known as four-wave-mixing Bragg scattering, a photon entering the ring is shifted in frequency by an amount equal to the difference in frequencies of the two pump lasers.

Like cycling around a racetrack, incoming light circulates around the resonator hundreds of times before exiting, greatly enhancing the device’s ability to shift the photon’s frequency at low power and with low background noise. Rather than using a few watts of power, as typical in previous experiments, the system consumes only about a hundredth of that amount. Importantly, the added amount of noise is low enough for future experiments using single-photon sources.

While other technologies have been applied to frequency conversion, “nanophotonics has the benefit of potentially enabling the devices to be much smaller, easier to customize, lower power, and compatible with batch fabrication technology,” said Srinivasan. “Our work is a first demonstration of a nanophotonic technology suitable for this demanding task of quantum frequency conversion.”

This work was performed by researchers at NIST’s Center for Nanoscale Science and Technology.

“Efficient and low-noise single-photon-level frequency conversion interfaces using silicon nanophotonics.” Q. Li, M. Davanço and K. Srinivasan.  Nature Photonics, 18 April 2016. DOI: 10.1038/nphoton.2016.64

Leading innovators in today’s integrated electronics supply chain are preparing to showcase their products and services at SEMICON West 2016 on July 12-14 in San Francisco, Calif.  Attendees will discover new international partners and suppliers, learn about the latest start-ups, and view cutting-edge, critical manufacturing technologies.

The industry has seen dramatic changes since last year’s exposition. Consolidation, IoT, and system integrators increasingly calling the shots have transformed the landscape. Engaging customers and finding new ones have never been more important. SEMICON West 2016 reflects this major realignment — it’s not “business as usual” anymore.

The expanded show floor has been re-engineered to feature megatrend programs and displays, including: the Innovation Theater and four new Exhibit Zones — Advanced Substrate Engineering, Advanced Packaging, Sustainable Manufacturing, and 3D Manufacturing. International Pavilions include Europe, Silicon Saxony, and Malaysia.

SEMICON West 2016 also features three new forums: Advanced Manufacturing, Flexible Hybrid Electronics, and the World of IoT.  Popular recurring programs include the SEMI/Gartner Market Symposium, “Bulls & Bears,” Connect Executive Summit, plus forums addressing wearables, Big Data, mobile, automotive, and other areas of interest to players in these supply chains.

SEMICON West 2016 will attract a broader roster of market makers in today’s globally interconnected semiconductor supply chain, including many of the world’s leading electronics companies as well as their customers and suppliers. To exhibit, visit: www.semiconwest.org.

By David W. Price, Douglas G. Sutherland and Kara L. Sherman

Author’s Note: The Process Watch series explores key concepts about process control—defect inspection and metrology—for the semiconductor industry. Following the previous installments, which explored the 10 fundamental truths of process control, this new series of articles highlights additional trends in process control, including successful implementation strategies and the benefits for IC manufacturing. For this article, we are pleased to include insights from our guest author, Kara Sherman.

As we celebrate Earth Day 2016, we commend the efforts of companies who have found ways to reduce their environmental impact. In the semiconductor industry, fabs have been building Leadership in Energy and Environmental Design (LEED)-certified buildings [1] as part of new fab construction and are working with suppliers to directly reduce the resources used in fabs on a daily basis.

As IC manufacturers look for more creative ways to reduce environmental impact, they are turning to advanced process control solutions to reduce scrap and rework, thereby reducing fab resource consumption. Specifically, fabs are upgrading process control solutions to be more capable and adding additional process control steps; both actions reduce scrap and net resource consumption per good die out (Figure 1).

Figure 1. The basic equation for improving a fab’s environmental performance includes reducing resource use and increasing yield. Capable process control solutions help fabs do both by identifying process issues early thereby reducing scrap and rework.

Figure 1. The basic equation for improving a fab’s environmental performance includes reducing resource use and increasing yield. Capable process control solutions help fabs do both by identifying process issues early thereby reducing scrap and rework.

Improved process control performance

Process control is used to identify manufacturing excursions, providing the data necessary for IC engineers to make production wafer dispositioning decisions and to take the corrective actions required to fix process issues.

For example, if after-develop inspection (ADI) data indicate a high number of bridging defects on patterned wafers following a lithography patterning step, the lithography engineer can take several corrective actions. In addition to sending the affected wafers back through the litho cell for rework, the engineer will stop production through the litho cell to fix the underlying process issue causing the yield-critical bridging defects. This quick corrective action limits the amount of material impacted and potentially scrapped.

To be effective, however, the quality of the process control measurement is critical. If an inspection or metrology tool has a lower capture rate or higher total measurement uncertainty (TMU), it can erroneously flag an excursion (false alarm), sending wafers for unnecessary rework, causing additional consumption of energy and chemicals and production of additional waste. Alternatively, if the measurement fails to identify a true process excursion, the yield of the product is negatively impacted and more dies are scrapped—again, resulting in less desirable environmental performance.

The example shown in Figure 2 examines the environmental impact of the process control data produced by two different metrology tools in the lithography cell. By implementing a higher quality metrology tool, the quality of the process control data is improved and the lithography engineers are able to make better process decisions resulting in a 0.1 percent reduction in unnecessary rework in the litho cell. This reduced rework results in a savings of approximately 0.5 million kWh of power and 2.4 million liters of water for a 100k WSPM fab—and a proportional percentage reduction in the amount of resist and clean chemicals consumed.

Figure 2. Higher quality process control tools produce better process control data within the lithography cell, enabling a 0.1 percent reduction in unnecessary rework that results in better environmental performance.

Figure 2. Higher quality process control tools produce better process control data within the lithography cell, enabling a 0.1 percent reduction in unnecessary rework that results in better environmental performance.

As a result of obtaining increased yield and reduced scrap, many fabs have upgraded the capability of their process control systems. To drive further improvements in environmental performance, fabs can benefit from utilizing the data generated by these capable process control systems in new ways.

Traditionally, the data generated by metrology systems have been utilized in feedback loops. For example, advanced overlay metrology systems identify patterning errors and feed information back to the lithography module and scanner to improve the patterning of future lots. These feedback loops have been developed and optimized for many design nodes. However, it can also be useful to feed forward (Figure 3) the metrology data to one or more of the upcoming processing steps [2]. By adjusting the processing system to account for known variations of an upcoming lot, errors that could result in wafer scrap are reduced.

For example, patterned wafer geometry measurement systems can measure wafer shape after processes such as etch and CMP and the resulting data can be fed back to help improve these processes. But the resulting wafer shape data can also be fed forward to the scanner to improve patterning [3-5]. Likewise, reticle registration metrology data can be used to monitor the outgoing quality of reticles from the mask shop, but it can also be fed forward to the scanner to help reduce reticle-related sources of patterning errors. Utilizing an intelligent combination of feedforward and feedback control loops, in conjunction with fab-wide, comprehensive metrology measurements, can help fabs reduce variation and ultimately obtain better processing results, helping reduce rework and scrap.

Fig 3

Figure 3. Multiple data loops to help optimize fab-wide processes. Existing feedback loops (blue) have existed for several design nodes and detect and compensate for process variations. New, optimized feedback loops (green) provide earlier detection of process changes. Innovative feed forward loops (orange) utilize metrology systems to measure variations at the source, then feed that data forward to subsequent process steps.

Earlier excursion detection reduces waste

Fabs are also reducing process excursions by adding process control steps. Figure 4 shows two examples of deploying an inspection tool in a production fab. In the first case (left), inspection points are set such that a lot is inspected at the beginning and end of a module, with four process steps in between. If a process excursion that results in yield loss occurs immediately after the first inspection, the wafers will undergo multiple processing steps, and many lots will be mis-processed before the excursion is detected. In the second case (right), inspection points are set with just two process steps in between. The process excursion occurring after the first inspection point is detected two days sooner, resulting in much faster time-to-corrective action and significantly less yield loss and material wasted.

Furthermore, in Case 1, the process tools at four process steps must be taken off-line; in Case 2, only half as many process tools must be taken offline. This two-day delta in detection of a process excursion in a 100k WSPM fab with a 10 percent yield impact results in a savings of approximately 0.3 million kWh of power, 3.7K liters of water and 3500 kg of waste. While these environmental benefits were obtained by sampling more process steps, earlier excursion detection and improved environmental performance can also be obtained by sampling more sites on the wafer, sampling more wafers per lot, or sampling more lots. When a careful analysis of the risks and associated costs of yield loss is balanced with the costs of additional sampling, an optimal sampling strategy has been attained [6-7].

Figure 4. Adding an additional inspection point to the line will reduce the material at risk should an excursion occur after the first process step.

Figure 4. Adding an additional inspection point to the line will reduce the material at risk should an excursion occur after the first process step.

Conclusion

As semiconductor manufacturers focus more on their environmental performance, yield management serves as a critical tool to help reduce a fab’s environmental impact. Fabs can obtain several environmental benefits by implementing higher quality process control tools, combinations of feedback and feedforward control loops, optimal process control sampling, and faster cycles of learning. A comprehensive process control solution not only helps IC manufacturers improve yield, but also reduces scrap and rework, reducing the fab’s overall impact on the environment.

References

  1. Examples:
    1. https://newsroom.intel.com/news-releases/intels-arizona-campus-takes-the-leed/
    2. http://www.tsmc.com/english/csr/green_building.htm
    3. http://www.ti.com/corp/docs/manufacturing/RFABfactsheet.pdf
    4. http://www.globalfoundries.com/about/vision-mission-values/responsibility/environmental-sustainability-employee-health-and-safety
  1. Moyer, “Feed It Forward (And Back),” Electronic Engineering Journal, September 2014. http://www.eejournal.com/archives/articles/20140915-klat5d/
  2. Lee et al, “Improvement of Depth of Focus Control using Wafer Geometry,” Proc. of SPIE, Vol. 9424, 942428, 2015.
  3. Tran et al, “Process Induced Wafer Geometry Impact on Center and Edge Lithography Performance for Sub 2X nm Nodes,” 26th Annual SEMI Advanced Semiconductor Manufacturing Conference, 2015.
  4. Morgenfeld et al, “Monitoring process-induced focus errors using high resolution flatness metrology,” 26th Annual SEMI Advanced Semiconductor Manufacturing Conference, 2015.
  5. “Process Watch: Sampling Matters,” Semiconductor Manufacturing and Design, September 2014.
  6. “Process Watch: Fab Managers Don’t Like Surprises,” Solid State Technology, December 2014.
  7. “Reducing Environmental Impact with Yield Management,” Chip Design, July 2012.

About the Authors:

Dr. David W. Price, Dr. Douglas Sutherland, and Ms. Kara L. Sherman are Senior Director, Principal Scientist, and Director, respectively, at KLA-Tencor Corp. Over the last 10 years, this team has worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements

Epitaxy, or growing crystalline film layers that are templated by a crystalline substrate, is a mainstay of manufacturing transistors and semiconductors. If the material in one deposited layer is the same as the material in the next layer, it can be energetically favorable for strong bonds to form between the highly ordered, perfectly matched layers. In contrast, trying to layer dissimilar materials is a great challenge if the crystal lattices don’t match up easily. Then, weak van der Waals forces create attraction but don’t form strong bonds between unlike layers.

In a study led by the Department of Energy’s Oak Ridge National Laboratory, scientists synthesized a stack of atomically thin monolayers of two lattice-mismatched semiconductors. One, gallium selenide, is a “p-type” semiconductor, rich in charge carriers called “holes.” The other, molybdenum diselenide, is an “n-type” semiconductor, rich in electron charge carriers. Where the two semiconductor layers met, they formed an atomically sharp heterostructure called a p-n junction, which generated a photovoltaic response by separating electron-hole pairs that were generated by light. The achievement of creating this atomically thin solar cell, published in Science Advances, shows the promise of synthesizing mismatched layers to enable new families of functional two-dimensional (2D) materials.

The idea of stacking different materials on top of each other isn’t new by itself. In fact, it is the basis for most electronic devices in use today. But such stacking usually only works when the individual materials have crystal lattices that are very similar, i.e., they have a good “lattice match.” This is where this research breaks new ground by growing high-quality layers of very different 2D materials, broadening the number of materials that can be combined and thus creating a wider range of potential atomically thin electronic devices.

“Because the two layers had such a large lattice mismatch between them, it’s very unexpected that they would grow on each other in an orderly way,” said ORNL’s Xufan Li, lead author of the study. “But it worked.”

The group was the first to show that monolayers of two different types of metal chalcogenides–binary compounds of sulfur, selenium or tellurium with a more electropositive element or radical–having such different lattice constants can be grown together to form a perfectly aligned stacking bilayer. “It’s a new, potential building block for energy-efficient optoelectronics,” Li said.

Upon characterizing their new bilayer building block, the researchers found that the two mismatched layers had self-assembled into a repeating long-range atomic order that could be directly visualized by the Moiré patterns they showed in the electron microscope. “We were surprised that these patterns aligned perfectly,” Li said.

Researchers in ORNL’s Functional Hybrid Nanomaterials group, led by David Geohegan, conducted the study with partners at Vanderbilt University, the University of Utah and Beijing Computational Science Research Center.

“These new 2D mismatched layered heterostructures open the door to novel building blocks for optoelectronic applications,” said senior author Kai Xiao of ORNL. “They can allow us to study new physics properties which cannot be discovered with other 2D heterostructures with matched lattices. They offer potential for a wide range of physical phenomena ranging from interfacial magnetism, superconductivity and Hofstadter’s butterfly effect.”

Li first grew a monolayer of molybdenum diselenide, and then grew a layer of gallium selenide on top. This technique, called “van der Waals epitaxy,” is named for the weak attractive forces that hold dissimilar layers together. “With van der Waals epitaxy, despite big lattice mismatches, you can still grow another layer on the first,” Li said. Using scanning transmission electron microscopy, the team characterized the atomic structure of the materials and revealed the formation of Moiré patterns.

The scientists plan to conduct future studies to explore how the material aligns during the growth process and how material composition influences properties beyond the photovoltaic response. The research advances efforts to incorporate 2D materials into devices.

For many years, layering different compounds with similar lattice cell sizes has been widely studied. Different elements have been incorporated into the compounds to produce a wide range of physical properties related to superconductivity, magnetism and thermoelectrics. But layering 2D compounds having dissimilar lattice cell sizes is virtually unexplored territory.

“We’ve opened the door to exploring all types of mismatched heterostructures,” Li said.

The title of the paper is “Two-dimensional GaSe/MoSe2 misfit bilayer heterojunctions by van der Waals epitaxy.”

The 62nd annual IEEE International Electron Devices Meeting (IEDM), to be held at the San Francisco Union Square Hilton hotel December 3 – 7, 2016, has issued a Call for Papers seeking the world’s best original work in all areas of microelectronics research and development.

The paper submission deadline this year is Wednesday, August 10, 2016. This deadline –– about 1½ months later than has been the norm for the IEDM – reduces the time between paper submissions and publication of the cutting-edge research results for which the conference is known. Also new for 2016 is that authors are asked to submit four-page camera-ready abstracts (instead of three pages), which will be published as-is in the proceedings.

Because of the more abbreviated schedule, only a very limited number of late-news papers will be accepted. Authors are asked to submit late-news abstracts announcing only the most recent and noteworthy developments. The late-news submission deadline is September 12, 2016.

“Because microelectronics technology changes so rapidly, it makes sense to shorten the time between when results are achieved and when they are discussed among the industry’s best and brightest who attend IEDM,” said Dr. Martin Giles, IEDM 2016 Publicity Chair and Intel Fellow and Director of Transistor Technology Variation in Intel’s Technology and Manufacturing Group. “This later submission deadline ensures that the freshest and most up-to-date work can be presented at the conference.”

Overall, the 2016 IEDM is seeking increased participation in the areas of power, wearable/Internet of Things (IoT), ultra-high speed, and quantum computing devices, which will be explored in depth in Special Focus Sessions in each area.

At IEDM each year, the world’s best scientists and engineers in the field of microelectronics from industry, academia and government gather to participate in a technical program of more than 220 presentations, along with special luncheon presentations and a variety of panels, special sessions, Short Courses, IEEE/EDS award presentations and other events spotlighting more leading work in more areas of the field than any other conference.

Papers in the following areas are encouraged:

  • Circuit and Device Interaction
  • Characterization, Reliability and Yield
  • Compound Semiconductor and High-Speed Devices
  • Memory Technology
  • Modeling and Simulation
  • Nano Device Technology
  • Optoelectronics, Displays and Imagers
  • Power Devices
  • Process and Manufacturing Technology
  • Sensors, MEMS and BioMEMS

Further information

For more information, interested persons should visit the IEDM 2016 home page at www.ieee-iedm.org.

IC Insights recently released its new Global Wafer Capacity 2016-2020 report that provides in-depth detail, analyses, and forecasts for IC industry capacity by wafer size, by process geometry, by region, and by product type through 2020.  In 2008, 300mm wafers took over as the industry’s primary wafer size in terms of total surface area used. Furthermore, the number of 300mm wafer fabrication facilities in operation continues to grow and is expected to reach 100 this year (Figure 1).

Some highlights regarding 300mm wafer fabs are shown below.

•    A couple fabs that were scheduled to open in 2013 were delayed until 2014.  That, in conjunction with the closure of two large 300mm fabs by ProMOS in 2013, caused the number of active volume-production 300mm fabs to decline for the first time in 2013.

•    At the end of 2015, there were 95 production-class IC fabs utilizing 300mm wafers (there are numerous R&D IC fabs and a few high-volume fabs that make “non-IC” products such as CMOS image sensors using 300mm wafers, but these are not included in the count).

•    Currently, there are eight 300mm wafer fabs scheduled to open in 2017, which would be the highest single-year increase since 2014 when nine 300mm fabs were added.

•    By the end of 2020 there are expected to be 22 more 300mm fabs in operation, bringing the total number of 300mm fabs used for IC fabrication to 117.  If 450mm wafers enter production, the peak number of 300mm fabs may be somewhere around 125.  For comparison, the highest number of volume-production 200mm wafer fabs in operation was 210 (in December of 2015 there were 148).

Today’s 300mm wafer fabs can be huge, but they are being equipped in a modular format, with each “module” generally having the capacity to process somewhere around 25K-45K wafers per month.  Each module is closely connected to nearby fab modules.  TSMC has perfected this modular approach, with its Fab 12, 14, and 15 sites being expanded in phases.

Figure 1

Figure 1

Development of 450mm wafer technology continues to progress toward production, albeit at a tempered pace. Since lithography is one of the biggest challenges in the 450mm wafer transition, ASM Lithography’s announcement in March 2014 that it would temporarily hold off on the development of equipment for 450mm wafers made some in the industry believe it was a signal that the transition would never happen.  ASML reported also that the decision to postpone its 450mm development program was made at the request of its customers.

IC Insights does not believe that ASML’s announcement, along with a couple other signs of a pause in 450mm development, means the 450mm wafer transition won’t happen, but they do indicate that the pilot production status for 450mm won’t be reached until probably 2019.  Volume production might start two to three years after that.

IC Insights’ Global Wafer Capacity 2016-2020—Detailed Analysis and Forecast of the IC Industry’s Wafer Fab Capacity report assesses the IC industry’s capacity by wafer size, minimum process geometry, technology type, geographic region, and by device type through 2020. The report includes detailed profiles of the companies with the greatest fab capacity and gives comprehensive specifications on existing wafer fab facilities.

MU, a medical-device manufacturer, and STMicroelectronics today announced that MU’s US-304 portable ultrasound imager, powered by ST’s STHV800 pulser, is aiming to increase the quality of point-of-care medical diagnostics in remote rural areas of Africa.

MU’s device has been developed for the “Doctor Car” mobile-clinic project to provide medical care in remote rural areas of Africa. In this project, medical workers use a special vehicle equipped with remote-healthcare systems to diagnose residents in remote rural areas where medical facilities are unavailable. The data obtained by the portable ultrasound device is transferred via mobile networks to healthcare entities in urban areas for detailed diagnosis and proper treatment. MU will start shipping ultrasound imagers to Doctor Cars and clinics in Africa this year.

The MU US-304 is a convex-type ultrasonic imager (3.5MHz) capable of performing abdominal diagnosis up to 15cm under the skin. It can be carried anywhere and simply connected via USB to a laptop or tablet. The MU device integrates ST’s high-voltage, high-speed ultrasonic-pulser IC (integrated circuit) with an 8-channel transducer driver circuit manufactured in ST’s proprietary 200V SOI-BCD semiconductor process. This process enables the integration of high-voltage CMOS technology, precise analog circuitry, and robust power stages on the same chip.

The industry’s most highly integrated ultrasonic pulser, ST’s STHV800 also offers low noise and tiny size to help produce accurate diagnostic images at a much lower cost and power consumption compared with stationary ultrasound equipment.

“The challenge in developing point-of-care ultrasound diagnostic devices is to achieve high portability and low cost without sacrificing performance. ST technology has proven an ideal solution to this problem,” said Yasuhiro Tamura, President, MU. “As we continue to create products for medical care in developing regions, in cooperation with ST, we hope to expand our application scope to new areas including livestock care.”

“MU’s newest portable ultrasound device is on course to improve the quality of medical diagnostics in remote rural areas, where the need is great,” said Hiroshi Noguchi, Director, Analog, MEMS and Sensors Group, STMicroelectronics Japan. “The selection of ST technology confirms our commitment to providing ultrasound-equipment makers with the highest performing ICs in the market and positions ST as the go-to partner for creating innovative applications that make positive contributions to people’s health and quality of life.”

ST offers a cost-effective evaluation board (STEVAL-IME013V1) that integrates the STHV800 pulser IC with an STM32F4 ARM Cortex-M microcontroller. The board’s graphical user interface and preset waveforms make it simple for designers to test the pulser under different conditions.

Celebrating its 70th anniversary, Brooks Instrument will be exhibiting at SEMICON West 2016 with new mass flow controllers (MFC) equipped with the high-speed EtherCAT interface, along with a broad range of other mass flow meters, controllers, vaporizers and capacitance manometers for semiconductor manufacturing.

The show runs July 12-14 at the Moscone Center in San Francisco. Brooks Instrument will be located in the South Hall at booth 1323.

A world leader in advanced flow, pressure, vacuum and vapor delivery solutions, Brooks Instrument will showcase key components in its MFC portfolio designed to meet critical gas chemistry control challenges and improve process yields for sub-20nm nodes. This includes the company’s newly enhanced GF100 Series MFCs with high-speed EtherCAT connectivity, as well as the GF135 advanced diagnostic MFC. Information on other pressure-based flow control technologies will also be available.

With its 70-year history in leading technology development, Brooks Instrument is focused on improving the precision and performance of mass flow, pressure and vacuum technologies to help enable advanced semiconductor manufacturing. Key items at SEMICON West include:

GF100 Series MFC with High-Speed EtherCAT Connectivity: Brooks Instrument has enhanced its industry-leading GF100 Series MFCs with high-speed EtherCAT interfaces for both high-flow and low-flow applications.

Responding to rapidly evolving requirements for next-generation tools and fabs, the GF100 Series features several additions to help boost process yields and productivity:

  • Embedded diagnostics to leverage real-time EtherCAT data acquisition capabilities for advanced fault detection and classification;
  • An ultra-stable flow sensor (less than 0.15 percent of S.P. drift per year) enables tighter low set point accuracy and reduces maintenance requirements;
  • Improved valve shutdown reduces valve leak-by, minimizing potential first wafer effects;
  • Enhancements to the GF100 advanced pressure transient insensitivity to less than one percent of S.P. with five PSI per second pressure perturbations, which reduces crosstalk sensitivity for consistent mass flow delivery.

GF135 Advanced Self-Diagnostic PTI MFC: The GF135 is the first “smart” pressure transient insensitive (PTI) MFC that can perform self-diagnostics such as integral rate-of-decay flow measurement without stopping the flow of process gas. This provides a competitive advantage, allowing semiconductor manufacturers to verify process gas accuracy, check valve leak-by, and monitor sensor stability in real time without removing the flow controller from the gas line – saving thousands of dollars in lost productivity.

With this unique real-time error detection technology, process and equipment engineers can reduce wafer scrap and lost production time from unacceptable flow deviations and unnecessary preventative maintenance checks. The Brooks Instrument GF135 PTI MFC also offers industry leading actual process gas accuracy and fast flow settling time for ascending and descending set points, helping to improve productivity and chamber-to-chamber matching.

Interactive Demonstration: The Brooks Instrument booth will include an interactive mass flow control demonstration where attendees can watch real-time gas flow error detection and advanced diagnostics on the GF135 MFC. Applications engineers will also be available to answer questions about the latest technologies to enhance process control, improve chamber matching and support process yield programs for semiconductor manufacturing. In addition, attendees are encouraged to visit the company in booth 1323 to share in its 70th anniversary celebration.

To overcome the current market and technology constraints taking place today within the semiconductor industry, new advanced packaging technologies have been developed by industrial companies. Leaders in the advanced packaging industry have identified new solutions enabling more and more functionalities to be integrated along with many devices in the same package. Yole Développement analysts are currently noting plenty of excitement within the advanced packaging sector: research, innovation and industrialization are the key words of the current industry status.
In this context, NCAP China (NCAP) and Yole Développement (Yole) are pursuing their collaboration and have announced the second Advanced Packaging & System Integration Technology Symposium:
• The symposium will take place in Wuxi, China, on April 21 & 22.
• Click program & registration to see the schedule, list of speakers, abstracts, and more.

In 2014, the first symposium was a notable success: in addition to attracting more than 80 attendees, the show generated numerous valuable discussions, meetings and business collaborations. In 2016, NCAP and Yole are excited to welcome the leaders of the advanced packaging industry for the second time, and are expecting a similar success. They have announced an impressive list of executive speakers including:
•  Li Ming, R&D Director, ASM Pacific technology
•  Ruurd Boomsma, Sr. VP Die Attach & CTO Besi Die Attach & Besi Group
•  Farhang Yazdani, President & CEO, BroadPak Corporation
•  Herb He Huang, Ph.D., Sr. Director, 3DIC & Sensors Technology Development, Corporate R&D Center, Semiconductor Manufacturing International Corporation (SMIC)
•  And many more: the lists of speakers, biographies, and abstracts are available on the i-micronews website. To download the PDF version, click Program & Abstracts.

The collaboration between NCAP & Yole is based on strategic thinking from both organizations. Both names and their international reputation send a strong signal to the advanced packaging community.

NCAP is a technology development center. Its aim is to build up leading edges in advanced packaging by IP licensing and commercialization of technology development and transformation, with a smart combination of the packaging supply chain constraints. This organization has, of course, an important role to play at the national level by developing and supporting valuable advanced packaging expertise and capabilities with local industrial partners.

“The whole advanced packaging industry is facing unbalanced development of semiconductor equipment and materials,” explained Dr. Cao LiQiang, CEO of NCAP. “Prices and cost monitoring are crucial to ensuring the sustainability of the companies.”

For its part, as a “More than Moore” market research and strategy consulting company, Yole is pursuing its research within the advanced packaging world and is expanding its expertise and understanding of this industry, day after day. The number of technology and market reports available each year and dedicated custom collaborations with multiple companies throughout the advanced packaging supply chain show the leadership of the consulting company within this sector.

“At Yole, we expect solid advanced packaging market growth reaching US$30 billion by 2020,” explained Thibault Buisson, Business Unit Manager, Advanced Packaging & Semiconductor Manufacturing at Yole (Source: Status of the Advanced Packaging Industry 2015 report, Yole Développement, November 2015). And he added: “We currently see substantial activity in the Advanced Packaging ecosystem: many companies from different business models are getting involved in this area and the competition is intensifying, New innovative platforms such as System-in-Package, Fan-Out packages and 2.5D/3D technology are changing the industry landscape and turning a new page in Advanced Packaging evolution. This is the motivation behind the organization of the Advanced Packaging & System Integration Symposium. The symposium emphasizes the value transition in packaging and is aimed at providing answers to the current challenges and key questions that the industry is facing today.”

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“The Advanced Packaging & System Integration Technology Symposium taking place next week in China is the result of Yole & NCAP powerful collaboration, a combination of both technical know-how and market expertise,” said Jean-Christophe Eloy, President & CEO, Yole Développement. He adds, “It clearly represents a wonderful opportunity for advanced packaging companies to develop, exchange and expand their activities to the advanced packaging industry in China and also in all other countries.”

NCAP and Yole are extremely enthusiastic about the 2nd advanced packaging symposium. Both partners welcome all industry leaders including: Alpha Szenszor, ASE Group, ASM Pacific Technology, Besi, BroadPak, Evatec, EV Group, JCAP, HuaTian Technology, Huawei, Plasma-Therm, Sinyang, SPTS/Orbotech, STATS ChipPAC, Zeta Instruments, and more. To see the full schedule, please click here: Program.

Moreover, on the afternoon, and on a volunteer basis, NCAP will invite the participants to visit its facilites. Program includes NCAP Introduction, Material Consortium Plan Introduction, Lab Tour.
For more information about the schedule and registration, please contact: Clotilde Fabre ([email protected]), Communication Coordinator, at Yole Développement.

Samco, a Japan-based semiconductor process equipment developer and manufacturer, is employing around 20 more people at its locations in North America, China, Taiwan and Singapore, as well as its subsidiary Samco-UCP in Liechtenstein, in order to better provide services and support to overseas customers.

“Increasing the number of Samco employees abroad is part of the company’s larger strategy to optimize our current sales structure while actively growing our customer base across the globe,” says Osamu Tsuji, Samco’s President, Chairman and CEO.

Samco offers systems and services that revolve around three major technologies, namely thin film deposition with PECVD, MOCVD and ALD systems; microfabrication with ICP etching, RIE and DRIE systems; and surface treatment with plasma cleaning and UV ozone cleaning systems.

“We’ve seen an increase in laser diode, MEMS and power device-related inquiries from abroad,” says Tsuji. “Systems for research and development at universities and research institutions, which is an area Samco specializes in, are also in high demand.”

This includes India, where the growing economy is expected to accelerate in the future. The Indian Institute of Technology Bombay recently installed one of Samco’s DRIE systems and collaborated with Samco to host the company’s first thin-film technology workshop in the country.

Samco is currently considering offering internships to students at IIT Bombay and has started gathering a team that will focus on cultivating the Indian market, Tsuji adds.

Future goals include doubling its on-site staff by July 2018, discussing the possibility of new locations in the future, and ensuring its overseas sales encompass at least 50% of the company’s total net sales within the next two or three years.

“Semiconductor equipment manufacturers’ overseas sales generally account for around 70 or 80 percent of their total net sales,” Tsuji says. “Samco has great potential for growth in the future. With these markets, we’ll actively expand and reach our goal of at least 10 billion yen in total net sales.”