Monthly Archives: April 2016

Nanoelectronics research center imec and Crystal Solar, a pioneer in direct wafer growing technologies for the next generation of solar photovoltaic products, today announced that they have achieved a 22.5 percent cell efficiency (certified by FhG ISE CalLab) with nPERT silicon (Si) solar cells manufactured on 6-inch mono-crystalline epitaxially grown kerfless wafers. Marking an industry first, imec and Crystal Solar have demonstrated the highest efficiency to-date for homojunction solar cells on epitaxially grown silicon wafers, paving the way toward industrialization of this promising technology.

Crystal Solar’s breakthrough manufacturing technology called Direct Gas to Wafer enables direct conversion of feedstock gas to mono crystalline silicon wafers by high throughput epitaxial growth. By skipping the polysilicon, ingoting and the wire-sawing steps altogether, this approach not only results in lowest cost/watt for the wafers but also significantly reduces the capital required to set up a manufacturing plant. Furthermore, this process enables the growth of high quality p-n junctions in-situ which reduces cell making steps while increasing the efficiency.

Imec has adapted its highly efficient nPERT Si solar cell process to align with the properties of Crystal Solar’s kerfless wafers. The 156x156mm2 cells were fabricated on 160 to 180 um thick grown n-type wafers with built-in rear p+ emitter. Imec’s n-PERT process included a selective front surface field realized by laser doping, advanced emitter surface passivation by Al2O3 and Ni/Cu plated contacts. The novel process using all industrially available processing steps resulted in record efficiencies for homojunction large area solar cells of 22.5 percent and a record Voc of 700mV. This high Voc illustrates the high quality of the wafers and the built-in junction.

Jozef Szlufcik, PV Department Director at imec: “We are extremely happy to have achieved such high conversion efficiencies on nPERT solar cells processed from kerfless wafers using imec’s pre-pilot industrial silicon PV manufacturing line. The combination of our advanced cell process and the innovative wafer manufacturing technique of Crystal Solar, is paving the way for manufacturing of highly efficient solar cells at substantially lower cost and will be disruptive for the complete solar manufacturing value chain.”

“We are pleased to see such a high conversion efficiency on our epitaxially grown n-type wafers with built in boron doped junctions,” said T.S. Ravi, CEO of Crystal Solar. “This approach represents a new paradigm in cell manufacturing with its unique ability to bypass significant steps in both wafer and cell manufacturing thereby dramatically reducing the capex and the overall cost per watt.  We expect to achieve >23% efficiencies with IMEC’s PERT technology in the very near future,” Mr. Ravi concluded.

Imec, the nanoelectronics research center, today announced that its annual Imec Technology Forum (ITF) in Brussels will take place May 24-25, 2016 in Brussels, Belgium at SQUARE, Brussels Meeting Centre. ITF Brussels is the flagship of imec’s worldwide series of technology forums that brings experts and visionaries together to discuss the future of technology and tech-innovation to market. This year’s theme is “Daring to Take a Different View—Nanotechnology in the Hot Seat,” which will explore nanotechnology from all angles, question its future course, and identify new applications and paths for its use.

“The heart of imec is innovation and collaboration, and ITF Brussels will demonstrate that. Innovation is the result of hard work, endless questions, challenges to the status quo. Attendees will experience first-hand how constantly pushing these boundaries is essential to come up with groundbreaking solutions and stimulate innovation,” stated Luc Van den hove, president and CEO of imec. “The recent events in Brussels have deeply touched all of us, however the city is open for business and travel. Imec is privileged to bring our partners and international guests together in Brussels to focus on this year’s theme.”

Expecting to draw more than 1,000 attendees, ITF Brussels will offer numerous expert speakers from within the imec organization such as An Steegen, senior vice president process technology, and Wim Van Thillo, director perceptive systems for IoT, automotive and wireless. Industry speakers will also headlineincluding C-level executives from Samsung, Mentor Graphics, ASM International, Infineon Technologies, GlobalFoundries, J&J Pharmaceuticals, Audi, Microsoft, to name just a few.

ITF Brussels will introduce two new additions to the conference line up: interactive panel discussions and imec hot seats. Hot topics in today’s technology discussion will be explored such as “Scaling is dead. Long live scaling.”; “How close are we to precision medicine?’; “It’s a software world but it would be nothing without hardware?”, and “Combining ecological and economical sustainability.” Panelists will comprise both imec and guest partner executives and offer their various perspectives, and attendees will have an interactive role with panel voting and Q&A. Imec hot seats will place imec experts front and center to answer attendee questions, exchange ideas, investigate collaboration opportunities and consider different views. Spanning its vast R&D focus, topics such as energy, IoT, healthcare, services, and CMOS will be analyzed.

ITF Brussels 2016 takes place May 24-25, 2016 at the SQUARE, Brussels Meeting Centre. For the full list of speakers, conference program, registration and more information, please visit: http://www.itf2016.be/Homepage/page.aspx/2098

Park Systems is sponsoring a webinar entitled Metrology Challenges and Opportunities presented by  Solid State Technology Magazine on April 14, 2016 at 10am PST. The webinar will address advanced materials used in semiconductor silicon wafer manufacturing and new device structures and designs under various stages of development. The presenter for the webinar is industry expert and SPIE Fellow, Dr. Alain Diebold, whose career includes cutting edge research on advanced metrology methods to improve nanoelectronics fabrication as Director of the Center for Nanoscale Metrology at CNSE.

According to the World Semiconductor Trade Statistics, the worldwide semiconductor market is forecasted to be up 0.3% to US$336 billion in 2016 and up another 3.1% to US$347 billion in 2017. Since 2007, Park has gained a reputation as the technology leader of nanoscale measurement and systems in both research and industry for the semiconductor and other industries and their impressive client list includes Harvard, Stanford, NASA, NIST, Micron, Imec, Seagate, Western Digital and IBM.

Park Systems provides the best quality AFM for Semiconductor microscopy for failure analysis and defect review, an integral part of the process of advancing semiconductor research and manufacturing. Park Smart ADR is the most advanced defect review solution available, featuring automatic target positioning without the need for labor intensive reference marks that often damage the sample. The Smart ADR process improves productivity by up to 1,000% compared to traditional defect review methods and offers up to 20x longer tip life thanks to Park’s groundbreaking True Non-Contact Mode AFM technology.

“AFM enables the determination of surface and sidewall roughness and feature line shape and is often used in conjunction with TEM, CD-SEM, and Scatterometry in Hybrid Metrology. The goal of Hybrid Metrology is to use the measurement information from multiple methods to improve 3D determination of feature shape and dimensions,” explains Dr. Alain Diebold, Interim Dean at the College of Nanoscale Sciences and Director of the SRC NRI INDEX Center.
Many of the new design challenges and opportunities will be presented in the webinar, showcasing the enhanced concepts under research and being commercialized. A critical role in the development and ongoing application of new device structures and materials is the advanced microscopy provided by world-leading Park Systems Atomic Force Microscopes, designed to meet the industry’s strict requirements for nanoscale accuracy.

“Our AFM technology is still unbeatable because of the high degree of accuracy and repeatability the non contact mode provides and because it is the only wafer fab AFM with automatic defect review,” stated Keibock Lee, Park Systems President. “Park’s fully automated Automatic Defect Review (ADR), designed specifically for the semiconductor industry, is the most advanced defect review systems available, providing identification and enabling a critical inline process to classify defect types and source their origin through high resolution 3D imaging.”

Much emphasis is being placed on new designs for more complex device structures and exploration of highly advanced new materials. This webinar will focus on some of the new device structures such as FinFETs and 3D stacking, new materials that are emerging and how they are proceeding towards future manufacturing. The industry continues to search for materials for transistors and interconnects. For example, a high dielectric constant “high K” material that is compatible with Ge channels are key to enabling the use of Ge channels. Thinner barrier layers for copper interconnects are another topic of research as well as the often mentioned replacement for copper itself.

“Lithography continues to drive a significant research effort. Quadruple patterning will replace double patterning. Double patterning (Self Aligned Double Patterning) refers to the use of oxide spacers on the side of lithographically patterned lines to double to line pattern density,” explains Dr. Diebold. “The space process can be applied multiple times. When the spacer process is applied twice, the pattern density is quadrupled. There are many variations of the use of multi-pattern methods.”

“Over the past several years, the industry has also investigated Directed Self Assembly of Block Co-Polymers as a means of increasing pattern density beyond that possible with traditional lithography. Research into EUV lithography also continues to be a critical topic,” adds Diebold.

Park NX-Wafer makes accurate, repeatable, and reproducible sub-Angstrom roughness measurements for the flattest substrates and wafers with minimized tip-to-tip variation. Park NX-Wafer delivers the industry’s lowest noise floor of less than 0.5 Å throughout the wafer area, combined with True Non-Contact Mode to achieve reliable measurements even for the long-range waviness measurement of scan sizes up to 100m x 100m.

LED Taiwan, the most influential LED exhibition in Taiwan, is organized by SEMI and the Taiwan External Trade Development Council (TAITRA). Opening at TWTC Nangang Exhibition Hall in Taipei on April 13-16, the four-day event features theme pavilions, industry forums, TechSTAGE and academic paper presentations. The Taiwan International Lighting Show (TiLS) is co-located. With 748 booths and 238 exhibitors demonstrating the local LED supply chains’ R&D capabilities, LED Taiwan is expected to attract over 16,000 visitors from Taiwan and internationally.

Research firm Strategies Unlimited estimates that the global LED packaging market had US$15.6 billion revenue in 2014. The market is expected to grow to US$22 billion by 2019, 45 percent from lighting applications. However, as the price of white LEDs continues to fall, new applications are regarded as the key to higher earnings. Prospects of niche-market applications like IR LED and UV LED look good, while automotive LED lights are becoming another important market with greater demand for high-power chips.

Five theme pavilions to fully demonstrate a complete LED industry chain

To satisfy the market’s demand for LED in an era of IoT, LED Taiwan 2016 will add three new pavilions — LED Components, Smart Lighting Technology, and Power Device — to the two existing pavilions High-Brightness LED and Sapphire. Leading players in the areas of LED equipment, materials, components and packaging ─ like Aurora Optoelectronics, Cree, Epileds, GlobalWafers, Han’s Laser, Lextar, an alliance of sapphire processing companies organized by the Metal Industries Research & Development Centre, Rapitech, Rubicon and Wei Min Industrial ─ will all showcase their products in the exhibition to help local and foreign visitors understand the structure, manufacturing processes and technologies of Taiwan’s LED industry.

Event to feature the results of innovation in five areas

To enable innovation and bring more energy to the local LED industry, TechSTAGE will be held as part of this year’s LED Taiwan event, showcasing Taiwan’s LED R&D capability in the areas of LED

Manufacturing Equipment & Materials, Power Device Technology, Sapphire Processing Technology & Application, LED Advanced Technologies, and Smart Lighting & Automobile Lighting.

Seeking more possibilities with innovative materials and power devices

As awareness about energy conservation increases around the world and the market seeks better profits and opportunities, more companies are investing in power device R&D and production. This has prompted LED Taiwan to focus on the hot topic of power devices this year, and in addition to a special pavilion for the segment, the event will also organize a forum for vendors to discuss and understand trends and development concerning this technology.

International forums to explore key issues in the industry

As the LED market is gradually maturing, companies in the industry are aggressively seeking new applications and “blue ocean” strategies. In addition to visible LED applications in back-lit display, mobile phones, lighting equipment and cars, more companies have invested in the development and production of invisible LEDs. While demand continues to diversify with a focus on custom-made applications, the ability to find new opportunities in this trend, improving competitiveness and innovation, will be the key to future success. The LED Taiwan 2016 Executive Summit will discuss future trends by exploring innovation, LED lighting/non-lighting opportunities, current challenges and strategies in the market. The IR and UV Summit will focus on IR and UV LED applications in wearable devices, medical appliances and measuring equipment in a bid to help participants get a quick grasp of latest trends around the world.

Integration of resources helps boost local LED industry’s global presence

LED Taiwan is made possible with the collaboration and resources from influential organizations in the industry, including SEMI, TAITRA, the Taiwan Lighting Fixture Export Association and the Taiwan Optoelectronic Semiconductor Industry Association. Each year, foreign buyers and leading manufacturers are invited to the exposition where various business matching events, VIP luncheons and banquet meetings are arranged to help Taiwan vendors expand connections and secure business opportunities by interacting with the elite members of foreign industrial and academic circles.

“SEMI has many connections and resources in the area of LED manufacturing, and by working with the Taiwan Lighting Fixture Export Association and TAITRA, we are able to organize LED Taiwan and TiLS at the same time, ” said Terry Tsao, president of SEMI Taiwan. “In addition to showing the world the robust ecosystem of Taiwan’s LED industry and attracting more foreign buyers, we also hope that innovative technologies and academic papers announced in the forums will help integrate industrial and academic resources. We want to create more opportunities for the LED industry and make Taiwan’s outstanding R&D capabilities visible to the world.”

LED Taiwan is the most influential LED exposition in Taiwan, showcasing LED production equipment & materials, epi wafers, crystals, packaging, modules, etc., as well as related technologies and manufacturing solutions. The Taiwan International Lighting Show is co-located at LED Taiwan as a multi-purpose event facilitating technology exchanges and procurement in the areas of LED and lighting. LED Taiwan was inaugurated in 2010, and in 2015, the event attracted buyers from over 68 countries and created more than US$13 million of business.

For more information on LED Taiwan, please visit: www.ledtaiwan.org/en/

By Paul Trio (SEMI); Dalia Vernikovsky (Applied Seals NA)

Evolving Industry Priorities

As the microelectronics industry becomes more mature and products become more advanced, there is greater emphasis on improving process control deeper within the supply chain. Whereas much of the attention has historically been at the fab as well as on equipment and materials, the spotlight is now focused on components and subcomponents.

As the industry prepares for 7nm and beyond, there is a realization that high-volume manufacturing at these advanced process nodes will be gated by equipment parts performance. With device manufacturers refining advanced process recipes pushing equipment, components, and subcomponents to the fringes of their performance envelopes, control is paramount. Industry standards will be as important in providing consistent parameters to enable users to compare similar parts and assess performance differences.

The Seal Situation

The subcomponent industry challenge outlined above certainly rings true for elastomeric seals. “Seals were invented near the end of the 19th century and the disturbing fact is that their manufacturing, material composition, and overall position in the vast industry is industrial in nature,” said Dalia Vernikovsky (Applied Seals North America), SCIS co-chair,  “Unless this industry comes together to forge guidelines or standards that correlate to SEMI’s stringent applications, and we bring the awareness that seal language still correlates to the mechanical make-up (thus the metal adders and constituents of things such as magnesium ferrous oxides), not the cleanliness specifications required, 7nm manufacturing will see defects traced to those components long after they are incorporated.”

Sealed with a Standard

With a myriad of applications and a variety of options, it is often difficult for users to select appropriate sealing materials. This problem is further compounded when O-ring suppliers use different criteria for quantifying O-ring performance coupled with inconsistent parameters and test methods. Control is key: making the right choice is essential for improving equipment uptime and reducing operational costs.

SEMI F51, Guide for Elastometric Sealing Technology, has been in publication since early 2000. This Document is a basic guide for the use of seals in semiconductor fabrication equipment. However, in order to meet the latest customer requirements, the standard needed an overhaul.

In 2014, the F51 Revision Task Force, under the North America Facilities Technical Committee Chapter was chartered to bring the standard to current industry specs. After a few ballot attempts, the task force’s 5080B proposal passed technical committee review at SEMICON West 2015 (July). By fall, the 5080B Ratification Ballot met the required acceptance conditions as well as clearing the necessary procedural reviews by the ISC Subcommittee on Audits & Reviews. The latest version of SEMI F51was published in November 2015 is now available for purchase from SEMI. It defines the criteria by which sealing performance can be judged in comparable measurements and seal materials can be chosen.

Behind the Scenes: A SEMI Special Interest Group

Determining how the SEMI F51 Standard would be revised didn’t happen overnight. Even before the F51 Revision Task Force was chartered, another SEMI group architected the characterization of seals parameters required at these advanced process nodes.

The Seals Group first identified seal performance criteria in several applications or process areas. The performance criteria was mainly divided into two groups: sealing requirements (e.g., etch rate, sealing force retention) and impurities (e.g., leachable, ash, outgassing, total organic carbon [TOC] testing). Process areas included: wet etch, etch, CVD/PVD, diffusion, and sub-fab.

Once the parameters were identified, the group prioritized which characteristics it needed to focus on. These included TOC, surface extractable metal contamination, and ash metal analysis. The Seals Group then developed test methodologies for measuring each performance. If test methods or standards already existed, the group simply referenced them.

Relative Importance of Seal Performance Criteria in Several Applications/Process Areas (1 – most important, 5 – least important) Figure 1

The Seals Group is part of a SEMI Special Interest Group (SIG) focused on Semiconductor Components, Instruments, and Subsystems (SCIS). SEMI SIGs provide a forum that fosters discussion and aligns stakeholders on industry-critical issues. SCIS represents companies that produce, package and/or distribute any of the following used in semiconductor or related industries:

  • Components such as seals, filters, mass flow controllers, valves, sensors, ion beam sources, etc.
  • Instruments for in-line and off-line data measurement, collection, and monitoring
  • Sub-systems that support process tools such as vacuum, robotics, power conversion, abatement, chillers, etc.

SCIS participation encompass Subcomponent-OEM-IDM stakeholders, including: Applied Seals NA; ASM; Brooks Automation; Busch Vacuum; Ebara; Edwards Vacuum; Entegris; Festo; GLOBALFOUNDRIES; Greene, Tweed; Horiba; Intel; KLA-Tencor; Lam Research; Pall; Parker; SMC; Swagelok; Texas Instruments; UltraClean Technology; VAT Valve.

SEMI SCIS SIG – Addressing Defectivity Problems in HVM

With defect and traceability playing a critical role in enabling high-volume manufacturing, SCIS is currently structured to focus on these problem areas. It aims to establish a framework that will enable industry partners to define:

  • Measurable defects for different components specific to intended process applications
  • Standardized test methods to measure the defects
  • Consistent methods for reporting the results

“Increased collaboration is required to establish new industry standards and parameters associated with semiconductor process control to meet the ever increasing yield, variability, and reliability challenges that comes with continued technology scaling,” said Gary Patton, CTO and SVP of WW R&D at GLOBALFOUNDRIES. “The SEMI SCIS group is playing a very crucial role in driving alignment between semiconductor manufacturers and equipment and sub-component suppliers on successful standards for sub-component defectivity and traceability needed for future technology nodes.”

The Seals Group is just one of four subteams under SCIS focused on defectivity. Subteams are established in the following areas:

  • Valves, Seals, and Pumps
  • Liquid and Gas Delivery
  • Critical Chamber Components and RF
  • Automation

As of this writing, each SCIS subteam has identified at least one process-critical component considered to be a primary contributor to defects:

Scope of Defectivity Components Figure 2

The subteams are now focusing on establishing a standard system of comparable metrics which will be used to rate, compare, and classify each of these identified components. This process is dictated by the following template:

SCIS Defectivity Template Figure 3

The Seals Group is not resting on its laurels with the latest revision to SEMI F51. The Seals team is now working on the next set of parameters including: sealing force retention, etch rate (range), permeation, and particles (size and range).

Visibility with Traceability

SCIS is also addressing the need for improved component parts traceability that will enable effective problem diagnosis and faster resolution.

Consider this rather common scenario: Fab yield excursion is traced to a batch of custom machined parts manufactured by Supplier A on a pump supplied by Supplier B on a process tool manufactured by Supplier C.  Fab engineer requests Supplier C to provide a list of all affected systems and spares to enable global containment plan. Without a standardized traceability process in place, the list takes a week to compile, introducing delays to the corrective action. 

The Traceability Verification Subteam under SCIS is chartered to implement an industry standard parts traceability process that will:

  • Define standardized formats and protocols
  • Facilitate communication among suppliers, OEMs, and IDMs.
  • Enable efficient problem diagnosis and resolution

“The Traceable Verification Model ensures Key Characteristics are controlled with compliance information easily accessed via a cloud based application. Intellectual property is secured via pre-approved access levels. The model holds all suppliers accountable but also ensures proprietary information is not compromised.” said Lance Dyrdahl (Lam Research), Defect Traceability Subteam leader.

Full Circle Engagement

As with the F51 seals activity, output from these SCIS Subteams will feed in to the various committees and task forces under the SEMI International Standards Program. As these Standards are used by the industry, new requirements will emerge and it will be up to SEMI Members to address them.

“Components standards should be effectively linked to the field performance for all-around benefits to component makers, OEMs and IDMs. The committee deliverables are structured to allow competitors to work together in driving commonality. Standardization and normalization methodology will provide IP-free participation.” said Ya-hong Neirynck (Intel), SCIS RF subteam co-leader. Lance Dyrdahl further pointed out, “Speedy ratification occurs when all participants agree on self-evident non-proprietary methods.”

The demands of the next-generation high-volume manufacturing will no doubt require a concerted effort among device manufacturers, OEMs, and suppliers. Diverse stakeholder participation is critical in solving these problems proactively. Failure to do so will certainly result in greater challenges (and pain) that will be shared by all.  “A piece of equipment or process line is only as strong as its weakest component,” said Sanchali Bhattacharjee (Intel), SCIS cochair.

Engaging in these SEMI SCIS initiatives provides a very strong value proposition for IDM-OEM-suppliers alike.

Engaging in SEMI SCIS Benefits All Industry Stakeholders Figure 4

The SEMI SCIS Special Interest Group is open to all SEMI Members. There will be an SCIS face-to-face meeting in conjunction with the SEMI Advanced Semiconductor Manufacturing Conference (ASMC) – May 16-19, 2016 – in Saratoga Springs, New York. Conference attendees are welcome to attend this face-to-face meeting. Future face-to-face meeting are also scheduled for SEMICON West 2016 (July) as well as the SEMI Strategic Materials Conference (SMC) in September. SCIS subteams meet via teleconference in between these face-to-face meetings. For more information or to join the SCIS SIG, please contact Paul Trio at SEMI ([email protected]).

By Jan Vardaman (TechSearch International) and Dan Tracy (SEMI)

While much of the recent attention has been focused on the growth of wafer level packages (WLPs), specifically fan-out WLPs, this is not the only segment forecast to undergo strong unit growth. In total, IC leadframe shipment growth will trend in the low single-digit range; the growth is entirely attributed to the chip-scale package (CSP) leadframe form factor. Combined, the more traditional IC leadframe segments are expected to experience flat shipments trends, while leadframe CSP shipments continue to growth.

Source: SEMI and TechSearch International, Global Semiconductor Packaging Materials Outlook

Leadframe CSP packages find broad adoption in analog, power, mixed signal, general purpose logic, sensors, and other device applications. A number of leadframe CSPs are in the form of quad flat no-lead (QFN) packages. These packages have pads instead of leads and do not use solder balls.  QFNs are found in mobile phones including smartphones, toys, games, tablets, medical systems, industrial, computers, networking, and automotive products.  Devices packaged in QFNs include many different MEMS and sensors such as accelerometers, gyroscopes, magnetometers, and pressure sensors, and power management devices, controllers, and ASICs.  Stacked die versions are increasingly common.  Gyroscopes and accelerometers are stacked with wire bonds in the QFNs found in many wearable products.  QFNs are also increasingly common as packages for automotive electronics.

This form factor will grow as it delivers a thin, small, and low-cost solution required in many applications. Emerging in the market are coreless structures based on a modified leadframe technology called a Molded Interconnect Solution/System (MIS) that deliver higher I/O and SiP solutions. Advancements are needed to further the high-volume ramp of MIS and other routable-leadframe CSP technologies.

Small package form factors deliver solutions needed in mobile applications and will provide the package technology for many sensor and wearable applications emerging in the market place.

The information in this article is from the Global Semiconductor Packaging Materials Outlook—2015-2019 report produced by SEMI and TechSearch International.

Micron Technology, Inc. today announced a new portfolio of PCIe solid state drives (SSDs) that leverage the high-performance NVMe protocol. The new Micron 9100 and 7100 PCIe SSDs provide data center customers with purpose-built storage products for implementing an agile, scale-out IT infrastructure. These new drives extend Micron’s rich portfolio of SATA and SAS SSDs that enable customers to extend and improve their legacy data center infrastructure with proven flash products.

Customers are disaggregating storage from Storage Area Networks (SANs) and frame-based arrays, moving toward server-based storage as a solution because of today’s changing computing landscape, which is largely driven by the influx of data being created, accessed and stored from the proliferation of mobile devices and cloud computing. Many of today’s leading hyperscale companies, who have taken advantage of server-based storage, have deployed Micron memory and storage in their data centers, giving them consistent, accelerated access to the world’s data wherever they are, whenever they want and from any device.

“Wikibon research shows that game-changing productivity potential awaits enterprises that develop and deploy new data-rich applications. These systems will heavily depend on flash-enabled, shared-data environments with low latency and predictable performance,” said David Floyer, CTO and co-founder, Wikibon. “The range of products Micron is announcing today allows enterprises to improve both the performance of existing platforms and to deploy vastly more functional applications that truly exploit flash technologies; all while leveraging any legacy infrastructure organizations have in place.”

“Dstillery, a pioneer in big data intelligence, uses a combination of proprietary technology and human intuition to help brands and media companies achieve their marketing objectives. In a world where content consumption continues to grow rapidly, we ingest billions of data points on a daily basis,” said Amit Gupta, vice president of infrastructure at Dstillery. “We perform 50 billion+ web transactions daily, most of which must be read from reliable storage media like Micron’s PCIe SSDs. Micron’s products have performed exceptionally well and have helped us achieve scale and value for our business.”

“Companies around the world are partnering with Micron to architect and future proof their data center design,” said Darren Thomas, vice president of storage at Micron. “As one of the founding innovators of the NVMe storage interface, Micron architected its portfolio of NVMe SSDs to take full advantage of the complete storage solution stack. With the addition of a high-performance NVMe drive to our portfolio—and with the recent addition of SAS—Micron has a product for every storage performance tier within the data center as we know it today.”

Enabling an agile storage platform, the new NVMe PCIe SSDs announced today are:

Micron 9100 NVMe PCIe SSD: Bringing Your Data up Close & Personal
The Micron 9100 NVMe PCIe SSD brings nonvolatile memory as close as possible to the processor, maximizing data speeds in the most demanding environments. The blazing-fast performance of a single Micron 9100 NVMe SSD enables customers to deliver dramatic business results—up to 10x faster—when compared to a single data center SATA SSD.

Micron’s 9100 NVMe PCIe SSD offers workload-focused capacity for both read-centric and mixed-used applications. Achieving 3.2TB of storage in both a HHHL & a 2.5″ U.2 form factor, the Micron 9100 SSD is purpose built to efficiently process business data. The U.2 form factor of Micron’s 9100 SSD allows front-bay access to the server, delivering a recognizable form, fit and function of that IT knows. Visit the Micron 9100 NVMe PCIe SSD product page for more information.

Micron 7100 NVMe PCIe SSD: Lean, Mean and Green
From power sensitive applications to space conscious environments, the Micron 7100 NVMe PCIe SSD brings higher performance and lower TCO to meet growing and changing enterprise needs. Whether it’s the slim 7mm U.2 (2.5″) hot-pluggable form factor or the tiny M.2, the 7100 allows dense designs that pack a punch. It uses half as many watts as a standard high-performance NVMe drive but provides low latencies unachievable by SATA SSDs. Visit the Micron 7100 NVMe PCIe SSD product page for more information.

Now shipping in volume, Micron is also working with customers to extend their existing IT investment with SAS SSDs.

Micron S600DC SAS SSDs: Bigger, Faster and Costs Less Compared to Hard Drives
Micron’s S600DC SAS Series provides customers with greater capacity, better performance and higher endurance at a much more affordable price point compared to 15K HDDs. Micron’s S600DC Series SSDs are the ideal solution to modernize and accelerate storage infrastructure supporting the heart of business. Databases, OLTP and business-critical virtualized applications all run on dependable SAS storage.

The S600DC SSD is one of the largest SAS solutions in the market achieving 4TB of storage in a 2.5″ form factor – more than double the capacity 10K 2.5″ HDDs and 4x the capacity of 15K HDDs. Micron’s S600DC SSD portfolio offers ultra-fast 12Gb/s SAS dual port bandwidth, delivering dramatic improvements in storage and server performance. The S610DC and S630DC provide up to 450x the performance of a single 15K RPM SAS HDD, while maintaining an equal or less dollar per gigabyte.

For years the primary barrier to entry for flash-based storage has been the higher dollar per gigabyte compared to HDD—this is no longer the case with Micron’s S600DC Series of SSDs. When matching usable capacity at a system level, the S610DC provides dramatic improvements in performance while offering a 27 percent lower acquisition cost. Visit the S600DC SAS Series product page for more information.

The Internet of Things (IoT) is a technology concept that is currently transforming and redefining virtually all markets and industries in fundamental ways. In fact, IHS forecasts that the IoT market will grow from an installed base of 15.4 billion devices in 2015 to 30.7 billion devices in 2020 and 75.4 billion in 2025, according to “IoT Platforms: Enabling the Internet of Things” a new white paper available as a free download from IHS Inc. (NYSE: IHS), a global source of critical information and insight.

An important sign of the fundamental significance of the IoT concept is that most major information and communication technology vendors are now strategically developing IoT offerings. Companies that sit at the heart of the telecom, networking, industrial infrastructure, enterprise system, and cloud computing sectors are now offering platforms to facilitate the broader economy’s transformation to pervasive connectivity. Over the past five years, fragmented efforts to connect machines and sensors in industry-specific ways are now coalescing into a comprehensive vision of connectivity permeating the global physical environment.

“IoT platforms serve to remove the complexity when developing, deploying, and managing applications over the application lifecycle,” said Sam Lucero, senior principal analyst, IHS Technology. “Moreover, these underlying platforms provide operators flexibility to choose various strategic approaches to the IoT beyond simple managed connectivity offers. IoT platforms enable new value-added services for developers and implementers, while providing complete, end-to-end IoT solutions directly to the market.”

Leti, an institute of CEA Tech, today announced the continuation of its collaboration with Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated, to develop CoolCube, Leti’s new sequential integration technology that eliminates the need for through-silicon vias (TSVs) and enables the stacking of active layers of transistors in the third dimension.

The extended project’s goals include building a complete CoolCube ecosystem that takes the technology from design to fabrication.

CoolCube was created by Leti as a unique and innovative device scale-stacking technology that allows the design and fabrication of very high-density and high-performance circuits.

By introducing an innovative stacking process combined with low-temperature transistor processing, the technology allows vertical integration of a transistor without degrading the performance of the transistors beneath or the metal interconnects between the layers of the transistors.

Mobile devices, in which minimal power consumption is key, are the primary segment for chips manufactured with the CoolCube technology. It also enables designers to include back-side imagers in chips, and co-integration of NEMS in a CMOS fabrication process.

Launched in 2014 so that Qualcomm Technologies could evaluate CoolCube’s potential, the project achieved several breakthroughs and original design methodology that demonstrated that it can provide a concrete solution for true 3D chips.*

“The Qualcomm Technologies and Leti teams have demonstrated the potential of this technology for designing and fabricating high-density and high-performance chips for mobile devices,” said Karim Arabi, vice president of engineering, Qualcomm Technologies, Inc. “We are optimistic that this technology could address some of the technology scaling issues and this is why we are extending our collaboration with Leti.”

As part of the collaboration, Qualcomm Technologies and Leti are sharing the technology through flexible, multi-party collaboration programs that will accelerate adoption of the technology.

“This is a new wave that CoolCube is creating and it has been possible thanks to the interest and support of Qualcomm Technologies, which is pushing the technological development in a good direction and sending a strong signal to the microelectronics community,” said Leti CEO Marie Semeria. “Together, we aim to build a complete ecosystem with foundries, equipment suppliers, and EDA and design houses to assemble all the pieces of the puzzle and move the technology into the product-qualification phase.”

ClassOne Technology, manufacturer of cost-efficient Solstice electroplating systems, has announced the completion of a major new round of funding from Salem Investment Partners of Winston-Salem, North Carolina. The announcement was made jointly by Byron Exarcos, CEO of ClassOne and Meredith Jolly, Vice President at Salem Investment Partners.

“It’s evident that 2016 will be another significant growth year for ClassOne Technology,” said Mr. Exarcos. “With this new funding we will fill order backlogs and address a forecast that is strong and rapidly increasing. This surge in business is coming from the many emerging markets that build products on 200mm and smaller substrates. These users are looking for advanced plating performance at an affordable price — and that’s precisely what Solstice systems are designed for. As a result, more and more of these companies are ordering our tools. And that now includes many of the top-tier manufacturers from around the world.”

“We’re delighted to see the exceptional and sustained growth that ClassOne Technology is achieving across the U.S., Europe and Asia,” said Ms. Jolly. “It’s even more remarkable given that the company just introduced the Solstice system two years ago. It’s great to be on a winning team and to be able to contribute to their success.”

ClassOne’s Solstice electroplating line serves many cost-sensitive emerging markets such as MEMS, Sensors, LEDs, Opto-electronics, RF and more. Designed specifically for ≤200mm wafer processing, Solstice tools are available in three different models and can electroplate a range of metals and alloys, either on transparent or opaque substrates. The company also just announced their Plating-Plus capability which allows Solstice to perform additional processing — such as Metal Lift-Off, Resist Strip and UBM Etch — along with plating, all on a single tool.

In addition to plating equipment, ClassOne also provides spin rinse dryers, spray solvent tools, advanced software and more. ClassOne equipment is strategically priced at less than half of what similar tools from the larger manufacturers would cost — which is why it has been described as “Advanced Wet Processing Tools for the Rest of Us.”