Yearly Archives: 2016

When it comes to putting technology in space, size and mass are prime considerations. High-power gallium nitride-based high electron mobility transistors (HEMTs) are appealing in this regard because they have the potential to replace bulkier, less efficient transistors, and are also more tolerant of the harsh radiation environment of space. Compared to similar aluminum gallium arsenide/gallium arsenide HEMTs, the gallium nitride-based HEMTs are ten times more tolerant of radiation-induced displacement damage.

Until recently, scientists could only guess why this phenomena occurred: Was the gallium nitride material system itself so inherently disordered that adding more defects had scant effect? Or did the strong binding of gallium and nitrogen atoms to their lattice sites render the atoms more difficult to displace?

The answer, according to scientists at the Naval Research Laboratory, is none of the above.

Examining radiation response

In a recent open access article published in the ECS Journal of Solid State Science and Technologyentitled, “On the Radiation Tolerance of AlGaN/GaN HEMTs,” the team of researchers from NRL state that by studying the effect of proton irradiation on gallium nitride-based HEMTs with a wide range of initial threading dislocation defectiveness, they found that the pre-irradiation material quality had no effect on radiation response.

Additionally, the team discovered that the order-of-magnitude difference in radiation tolerance between gallium arsenide- and gallium nitride-based HEMTs is much too large to be explained by differences in binding energy. Instead, they noticed that radiation-induced disorder causes the carrier mobility to decrease and the scattering rate to increase as expected, but the carrier concentration remains significantly less affected than it should be.

Applications in space exploration

Because of their relative radiation hardness, gallium arsenide- and gallium nitride-based HEMTs are desirable for space application. Take, for example, the Juno Spacecraft.

On July 4, the Juno Spacecraft successfully entered orbit around Jupiter – a planet scientists still know very little about, which generates extreme levels of radiation. Without the proper technology, the radiation levels of Jupiter could destroy the sensitive electronics in the satellite upon approaching the planet. Better understanding of why gallium arsenide- and gallium nitride-based HEMTs are more tolerant of radiation could ultimately accelerate innovative and bolster projects where radiation levels prove to be barriers.

Novel advancements in HEMTs

The paper was designated ECS Editors’ Choice due to its significance and expected impact on the solid state science and technology community.

“Editors’ Choice articles are elite publications because they are deemed by reviewers and journal editors to demonstrate a transformative advance, discovery, interpretation, or direction in a field,” says Dennis Hess, Editor of the ECS Journal of Solid State Science and Technology. “They represent very high quality science and engineering and hold the promise of altering current technology practices.”

Unexpected answers

The explanation for this novel discovery turns out to be rather elegant.

In gallium nitride-based HEMTs, a piezoelectric field forms at the aluminum gallium nitride/gallium nitride interface due to lattice strain. The field gives rise to two-dimensional electron gas by which carriers travel across the transistor from source to drain. It also provides an electrically attractive environment that causes carriers that are scattered out of the two-dimensional electron gas by radiation-induced defects to be reinjected. In this way, the scattering rate can increase and the mobility can decrease without greatly affecting the two-dimensional electron gas carrier density.

In other words, it is the internal structure itself that renders aluminum gallium nitride/gallium nitride HEMTs rad-hard.

“Gallium nitride is such a complicated system – not like gallium arsenide at all,” says Bradley Weaver, co-author of the study. “We struggled for four years to figure out why it’s so rad-hard, expecting a complicated solution. But the answer turned out to be really simple. Science does that sometimes.”

Materials researchers at North Carolina State University have fine-tuned a technique that enables them to apply precisely controlled silica coatings to quantum dot nanorods in a day – up to 21 times faster than previous methods. In addition to saving time, the advance means the quantum dots are less likely to degrade, preserving their advantageous optical properties.

Morphological control of the silica shell on CdSe/CdS core/shell quantum dot nanorods is reported, giving single or double lobes of silica or a uniform silica shell. Credit: Joe Tracy

Morphological control of the silica shell on CdSe/CdS core/shell quantum dot nanorods is reported, giving single or double lobes of silica or a uniform silica shell. Credit: Joe Tracy

Quantum dots are nanoscale semiconductor materials whose small size cause them to have electron energy levels that differ from larger-scale versions of the same material. By controlling the size of the quantum dots, researchers can control the relevant energy levels – and those energy levels give quantum dots novel optical properties. These characteristics make quantum dots promising for applications such as opto-electronics and display technologies.

But quantum dots are surrounded by ligands, which are organic molecules that are sensitive to heat. If the ligands are damaged, the optical properties of the quantum dots suffer.

“We wanted to coat the rod-shaped quantum dots with silica to preserve their chemical and optical properties,” says Bryan Anderson, a former Ph.D. student at NC State who is lead author of a paper on the work. “However, coating quantum dot nanorods in a precise way poses challenges of its own.”

Previous work by other research teams has used water and ammonia in solution to facilitate coating quantum dot nanorods with silica. However, those techniques did not independently control the amounts of water and ammonia used in the process.

By independently controlling the amounts of water and ammonia used, the NC State researchers were able to match or exceed the precision of silica coatings achieved by previous methods. In addition, using their approach, the NC State team was able to complete the entire silica-coating process in a single day – rather than up to one to three weeks needed for other processes.

“The process time is important, because the longer the process takes, the more likely it is that the quantum dot nanorods being coated will degrade,” says Joe Tracy, an associate professor of materials science and engineering at NC State and senior author on the paper. “The time factor may also be important when we think about scaling this process up for manufacturing processes.”

That said, researchers still have a problem.

The process of applying the silica coating etches the cadmium sulfide surface of the quantum dot nanorods, which shortens the length of the nanorods by as much as four or five nanometers. That shortening is indicative of etching, which reduces the brightness of the light emitted by the quantum dot nanorods.

“We think ammonia may be the culprit,” Tracy says. “We have some ideas that we’re pursuing, focused on how to substitute another catalyst for ammonia in order to minimize the etching and better preserve the quantum dot nanorod’s optical properties.”

The paper, “Silica Overcoating of CdSe/CdS Core/Shell Quantum Dot Nanorods with Controlled Morphologies,” is published online in the journal Chemistry of Materials. The paper was co-authored by Wei-Chen Wu, a former Ph.D. student in Tracy’s lab. The work was done with support from the National Science Foundation under grant number DMR-1056653.

Tracy has previously published related research in Chemistry of Materials on coating gold nanorods with silica shells.

This article was originally posted on SemiMD.com and was featured in the July 2016 issue of Solid State Technology.

By Ed Korczynski, Sr. Technical Editor

Applied Materials has disclosed commercial availability of new Selectra(TM) selective etch twin-chamber hardware for the company’s high-volume manufacturing (HVM) Producer® platform. Using standard fluorine and chlorine gases already used in traditional Reactive Ion Etch (RIE) chambers, this new tool provides atomic-level precision in the selective removal of materials in 3D devices structures increasingly used for the most advanced silicon ICs. The tool is already in use at three customer fabs for finFET logic HVM, and at two memory fab customers, with a total of >350 chambers planned to have been shipped to many customers by the end of 2016.

Figure 1 shows a simplified cross-sectional schematic of the Selectra chamber, where the dashed white line indicates some manner of screening functionality so that “Ions are blocked, chemistry passes through” according to the company. In an exclusive interview with Solid State Technology, company representative refused to disclose any hardware details. “We are using typical chemistries that are used in the industry,” explained Ajay Bhatnagar, managing director of Selective Removal Products for Applied Materials. “If there are specific new applications needed than we can use new chemistry. We have a lot of IP on how we filter ions and how we allow radicals to combine on the wafer to create selectivity.”

From first principles we can assume that the ion filtering is accomplished with some manner of electrically-grounded metal screen. This etch technology accomplishes similar process results to Atomic Layer Etch (ALE) systems sold by Lam, while avoiding the need for specialized self-limiting chemistries and the accompanying chamber throughput reductions associated with pulse-purge process recipes.

“What we are doing is being able to control the amount of radicals coming to the wafer surface and controlling the removal rates very uniformly across the wafer surface,” asserted Bhatnagar. “If you have this level of atomic control then you don’t need the self-limiting capability. Most of our customers are controlling process with time, so we don’t need to use self-limiting chemistry.” Applied Materials claims that this allows the Selectra tool to have higher relative productivity compared to an ALE tool.

Due to the intrinsic 2D resolutions limits of optical lithography, leading IC fabs now use multi-patterning (MP) litho flows where sacrificial thin-films must be removed to create the final desired layout. Due to litho limits and CMOS device scaling limits, 2D logic transistors are being replaced by 3D finFETs and eventually Gate-All-Around (GAA) horizontal nanowires (NW). Due to dielectric leakage at the atomic scale, 2D NAND memory is being replaced by 3D-NAND stacks. All of these advanced IC fab processes require the removal of atomic-scale materials with extreme selectivity to remaining materials, so the Selectra chamber is expected to be a future work-horse for the industry.

When the industry moves to GAA-NW transistors, alternating layers of Si and SiGe will be grown on the wafer surface, 2D patterned into fins, and then the sacrificial SiGe must be selectively etched to form 3D arrays of NW. Figure 2 shows the SiGe etched from alternating Si/SiGe stacks using a Selectra tool, with sharp Si corners after etch indicating excellent selectivity.

“One of the fundamental differences between this system and old downstream plasma ashers, is that it was designed to provide extreme selectivity to different materials,” said Matt Cogorno, global product manager of Selective Removal Products for Applied Materials. “With this system we can provide silicon to titanium-nitride selectivity at 5000:1, or silicon to silicon-nitride selectivity at 2000:1. This is accomplished with the unique hardware architecture in the chamber combined with how we mix the chemistries. Also, there is no polymer formation in the etch process, so after etching there are no additional processing issues with the need for ashing and/or a wet-etch step to remove polymers.”

Systems can also be used to provide dry cleaning and surface-preparation due to the extreme selectivity and damage-free material removal.  “You can control the removal rates,” explained Cogorno. “You don’t have ions on the wafer, but you can modulate the number of radicals coming down.” For HVM of ICs with atomic-scale device structures, this new tool can widen process windows and reduce costs compared to both dry RIE and wet etching.

—E.K.

BY DR. PHIL GARROU, Contributing Editor

At the ECTC conference in May, in the “Advances in Fan Out Packaging” session, Matt Lueck of RTI International discussed the results of their joint program with X-Celeprint.

A common aspect to all fan-out packaging is the requirement to physically assemble devices into dispersed arrays, often called reconfigured wafers, which provides the real estate needed to fan-out. Devices made in sub-mm chip sizes can impose cost and performance challenges to FO-WLP using serial pick-and place assembly technologies. RTI and X-Celeprint joined forces to develop a fan out package for sub mm IC using the X-Celeprint massively parallel assembly technology called micro transfer-printing, which is well-suited for handling very thin and fragile devices.

In their micro transfer-printing technology a polymer layer is first applied to the substrate before the assembly process, and the devices are assembled in a face-up configuration. Following the formation of the reconfigured substrates, conventional redistribution layer (RDL) and solder ball processing was performed. Two different photo-imageable spin on dielectrics, HD4100 PI and Intervia 8023 epoxy, were used as the RDL dielectrics. The fan-out package contains no molding compound and is made using standard wafer-level packaging tools.

There are potential benefits from fan-out packaging strat- egies that do not require molding compound. The process described here does not suffer from the “die drift” that occurs during compression molded fan-out packaging which often requires special adaptive alignment techniques. It also does not suffer from the wafer and package warpage that can occur in molding compound based fan-out packages.

Micro-transfer printing was used to assemble reconfigured wafers of devices (80um x 40um chips with a redistribution metal and six contact pads), onto 200mm wafers. After assembly, they undergo a standard wafer level redistribution and bumping process. The final fan-out package pitch on the 200 mm wafer is 1.4mm x 1.0mm with six 250 μm solder bumps. The fan-out packages were assembled and reflowed onto FR4 test boards.

The Figure shows (A) the chiplet source wafer after partial removal of chiplets with the elastomer stamp; (B) a completed fan out package before solder ball placement; (C) close-up of the interconnect to the chi pads; (D) Final FO-WLP. Initial yields are reported to be 97%.

Screen Shot 2017-04-21 at 12.08.29 PM

Two PCB test vehicles populated with 60 die each were built for thermal cycle testing. The board level thermal cycle testing was run under -40°C to 125°C. None of the die showed more than 0.2 ohm change in average resistance.

Infineon Technologies AG and Cree, Inc. (Nasdaq:  CREE) announced today that Infineon has entered into a definitive agreement to acquire the Wolfspeed Power and RF division (“Wolfspeed”) of Cree. The deal also includes the related SiC wafer substrate business for power and RF power. The purchase price for this planned all-cash transaction is US Dollar 850 million (approximately Euro 740 million). This acquisition will enable Infineon to provide the broadest offering in compound semiconductors and will further strengthen Infineon as a leading supplier of power and RF power solutions in high-growth markets such as electro-mobility, renewables and next-generation cellular infrastructure relevant for IoT.

Dr. Reinhard Ploss, CEO of Infineon Technologies AG, said: “Joining forces with Wolfspeed represents a unique growth opportunity. Wolfspeed’s and Infineon’s businesses and expertise are highly complementary, bringing together industry leading experts for compound semiconductors. This will enable us to create additional value for our customers with the broadest and deepest portfolio of innovative technologies and products in compound semiconductors available in the market. With Wolfspeed we will become number one in SiC-based power semiconductors. We also want to become number one in RF power. This will accelerate the market introduction of these innovative technologies, addressing the needs of modern society – such as energy efficiency, connectivity and mobility.”

Chuck Swoboda, Cree Chairman and CEO, said: “After much consideration and due diligence over the past year, we concluded that selling Wolfspeed to Infineon was the best decision for our shareholders, employees and customers. We believe that Wolfspeed will now be able to more aggressively commercialize its unique silicon carbide and gallium nitride technology as part of Infineon.”

Frank Plastina, Wolfspeed CEO, said: “By joining the Infineon team, Wolfspeed will now have all the advantages of a global company in our sector, including the ability to leverage Infineon’s market reach and infrastructure. With Infineon’s complementary culture and additional investment, we’ll be better positioned to unlock the potential of our portfolio and our people.”

Wolfspeed is based in Research Triangle Park, North Carolina, USA, and has been a part of Cree for almost three decades. Wolfspeed is a premier provider of SiC-based power and GaN-on-SiC-based RF power solutions. This also includes the related core competencies in wafer substrate manufacturing for SiC, as well as for SiC with a monocrystalline GaN layer for RF power applications. With these competencies, more than 550 highly skilled employees and a strong IP portfolio of approximately 2,000 patents and patent applications, this deal complements Infineon’s previous acquisition of International Rectifier in early 2015. Wolfspeed’s SiC-based product portfolio ideally adds to Infineon’s offering.

Power management solutions based on compound semiconductors have several advantages enabling Infineon’s customers to develop systems with higher energy-efficiency, smaller footprints and lower system costs. Combining the comprehensive portfolios of technologies, products and manufacturing capabilities, Infineon and Wolfspeed will accelerate the development of components enabling customers to develop differentiating systems. Major areas where the applications will profit from SiC are renewables and especially automotive. Both areas benefit from the increased power density and improved efficiency. In automotive it fits well with the recent increased commitment of the industry to plug-in hybrid and all-electric vehicles (xEV). Combining both portfolios and competencies will significantly accelerate the time-to-market for new products based on compound semiconductors.

Next-generation cellular infrastructure standards such as 5G and beyond will use frequencies up to 80 gigahertz. Only advanced compound semiconductors can deliver the required efficiencies at these high frequencies. GaN-on-Si allows higher levels of integration and offers its advantages at operating frequencies of up to 10 gigahertz. GaN-on-SiC enables maximum efficiency at frequencies of up to 80 gigahertz. Both technologies are crucial for next generation cellular infrastructure standards. Together with its Si-based LDMOS products Infineon is the industry’s most complete provider for RF power components.

The combined portfolio advances Infineon’s strategic “Product to System” approach. Additionally, Infineon will benefit from accelerating the adoption of SiC- and GaN-based components in early-adopter markets, e.g. electro-mobility, high-end photovoltaic inverter, xEV charging infrastructure, and RF power components in cellular infrastructure.

The business to be acquired by Infineon has generated pro-forma revenues of US Dollar 173 million in the twelve months ending March 27, 2016. The acquisition will be immediately accretive to Infineon’s adjusted earnings-per-share and margin. Infineon will fund the transaction with bank financing of US Dollar 720 million and US Dollar 130 million of cash-on-hand. Infineon will maintain its strong balance sheet after the cash- and debt-financed transaction. Infineon’s capital structure will stay well within the previously communicated targets of Euro 1 billion gross cash plus 10 to 20 percent of revenue, and no more than two times the gross debt-to-EBITDA.

Cree’s Board of Directors and Infineon’s Supervisory Board have approved the acquisition. The closing of the transaction is subject to regulatory approvals in various jurisdictions and is expected by the end of calendar year 2016.

The increasing value of the average IC content in cellular handsets along with the increasing percentage of smartphones sold as a percent of total cellular handsets will help drive the cellphone IC market to $94.3 billion in 2019. Strong double-digit growth rates in the cellular handset IC market were logged in 2013 and 2014 but only a 2% increase was registered in 2015. Despite the expected increase of 4% in 2016, the 2015-2019 total cellphone IC market CAGR is forecast to be 6.7%, 3.0 points higher than the 3.7% CAGR forecast for the total IC market during this same time.  The $94.3 billion 2019 cellphone IC market is forecast to be about 30% higher than the level registered in 2015.

Figure 1

Figure 1

In 2015, the IC product segment that had the highest average content per cellphone was the MPU category ($9.92), which includes the application processors used in smartphones.  The second highest was the application specific logic segment, which had an average $8.55 of IC content per cellular handset.  In total, there was an average of $38.78 worth of ICs in a 2015 cellular handset.

DRAM memory held 59% ($12.3 billion) of the total cellphone memory market in 2015, with NAND flash representing most of the remainder of the market.  The $21.0 billion cellphone memory market in 2015 was driven by the surge in shipments of memory-rich high-end smartphones and the 6% increase in the cellphone DRAM market.

The average analog content in a cellphone increased in 2015 to $6.64 while the total cellphone analog IC market increased by 8%, six points better than the 2% growth rate experienced by the total 2015 analog IC market.  Application specific analog, mostly comprised of mixed-signal devices, represented about 83% of the total $12.5 billion 2015 cellular handset analog IC market.

In 2019, as the market shifts more toward low-end smartphones, the cellphone MPU market is expected to represent 23% of the total cellphone IC market, down two points from 26% in 2015.  Moreover, the cellphone DRAM memory market in 2019 is forecast to reach $19.9 billion and be more than 2x larger than the total flash cellphone IC market ($9.5 billion) in that year.  In contrast to the high-growth cellphone DRAM market, the 2019 cellphone DSP market is forecast to be less than $0.1 billion, down from $1.3 billion in 2012.

NSTAR Global Services is now offering facilities management services for operations and maintenance (O&M) of installed OEM facility equipment or previously constructed systems that support fab operations in high-tech industries. As fab/facilities owners look to optimize their operating costs in production support areas, NSTAR offers to reduce fixed overhead costs and provide a flexible workforce solution to reduce fixed headcount while still allowing the client to maintain control over its operations and results.

“NSTAR’s facilities services can apply to both new and already-existing fabs, helping them to ramp up their operations and hand over existing staff to outsource part or entire sections of facilities O&M,” said Darrell McDaniel, President of NSTAR Global Services. “This new service solution expands on NSTAR’s already-existing service expertise, working with IDMs and other facilities’ owners to deliver a fixed fee solution, helping the client to save money and reduce risks.”

“We have a stringent policy on safety, so all of our staff is fully trained for on-site processes as well as mandatory safety protocols,” stated Hardev Grewal, VP of Business Development at NSTAR. “Our customers appreciate the availability and reliability of our qualified personnel.”

NSTAR has a well-tested method to implement services at any fab/facility, and customize them to clients’ needs. These new facilities services have already been implemented by several major tier-one OEMs in the United States. In the past, facilities services have traditionally been performed in-house or completely outsourced to a third-party vendor. Instead, NSTAR’s approach to facilities services uses already-proven methods, allowing clients to ultimately maintain control over their operations rather than depend entirely on third-party processes.

Sono-Tek Corp. unveiled a new photoresist ultrasonic coating system in Booth #2146. The new photoresist coating system, SPT200, has been designed specifically to meet the unique challenges of coating high aspect ratios and deep well topographies such as MEMS wafers with photoresist.

The SPT200 replaces traditional spin coating equipment, providing more uniform coverage of side walls in difficult to coat applications. Ultrasonic spray has been used for photoresist deposition for years, and is a well proven method for semiconductor lithography manufacturing.

SPT200 is typically configured with Vortex or AccuMist ultrasonic spray shaping nozzles, depending upon coating requirements. Sono-Tek’s team of application engineers ensures the correct configuration for each process. At the heart of the system is Sono-Tek’s patented ultrasonic nozzle technology. All ultrasonic nozzles feature up to 95 percent reduction in material consumption, non-clogging performance, and precise, targeted spray patterns at ultra-low flow rates.

SPT200 unique system features include:
• Automated spray coating with recipe storage
• Designed for 100, 150, 200, and 300mm wafers
• Precision temperature control
• Integrated wafer lockdown
• Highly repeatable syringe pump with auto refill
• Manual wafer load/unload
• Highly repeatable, stable process

Sono-Tek has application expertise in depositing photoresist onto MEMS and other semiconductor wafer substrates.

Pall Corporation announced this week the availability of its new 5nm XpressKleen filter. The filter is the latest addition to the company’s XpressKleen chemical filter line-up and is a key component of Pall’s disposable PFA (Perfluoroalkoxy alkanes) KleenChange assemblies. The new 5 nm XpressKleen filter is designed to meet the growing defectivity challenges of sub-10nm critical chemical processing. It demonstrates finer retention, fast flow, and higher purity than previous filters. Retention is validated using Pall’s gold nanoparticle challenge test.

“The 5 nm XpressKleen filter leverages Pall’s proprietary ‘XP’ cleaning process that reduces trace metal contamination by 50% to less than 500 parts per trillion (ppt) total for nineteen critical metal ions for a ten-inch device,” said Steve Chisolm, President of Pall Microelectronics. “The ‘XP’ cleaning process also removes organics, surface particles, and anions. Pall is proud to bring these important purity and retention capabilities to the market to enable the semiconductor scaling cadence.”

Pall’s completely integrated manufacturing capability extends from PTFE resin to the finished filter device. The company’s advanced manufacturing process uses clean room manufacturing and statistical process control to ensure the reliability and performance of every 5nm XpressKleen filter.

By Ed Korczynski, Sr. Technical Editor

Medical and health/wellness monitoring devices provide critical information to improve quality-of-life and/or human life-extension. To meet the anticipated product needs of wearable comfort and relative affordability, sensors and signal-processing circuits generally need to be flexible. The SEMICON West 2016 Flexible Electronics Forum provided two days of excellent presentations by industry experts on these topics, and the second day focused on the medical applications of flexible circuits.

Flexible ultra-thin silicon

While thin-film flexible circuits made with printed thin-film transistors (TFT) have been developed, they are inherently large and slow compared to silicon ICs. Beyond dozens or hundreds of transistors it is far more efficient to use traditional silicon wafer manufacturing technology…if the wafers can be repeatedly thinned down below 50 microns without damage.

Richard Chaney, general manager of American Semiconductor, presented on a “FleX Silicon-on-Polymer” approach that provides a replacement polymer substrate below <1 micron thin silicon to allow for handling and assembly. Processed silicon-on-insulator (SOI) wafers are front-side temporarily bonded to a “handle-wafer”, then back-side grinded to the buried oxide layer, then oxide chemically removed, and then an application-specific polymer is applied to the backside. After removing the FleX wafer from the handle-wafer, the polymer provides physical support for dicing and the rest of assembly.

For the last few years, the company has been doing R&D and limited pilot production by shipping lots of wafers through partner applications labs, but in the second-half of 2015 acquired a new manufacturing facility in Boise, ID. Process tools are being installed, and the first product dice are “FleX-OPA” operational amplifiers. Initial work was supported by the Air Force Research Laboratory (AFRL), but in the last 12-18 months the company has seen a major increase in sample requests and capability discussions from commercial companies.

Printed possibilities

Bob Street of Xerox’s Palo Alto Research Center (PARC) presented on “Printed hybrid arrays for health monitoring.” There are of course fundamentally different sensor needs for different applications, and PARC is working on many thin-film transducers and circuits:

Gas sensing – outer environment or human breath,

Optical sensing – monitoring body signals such as blood oxygen,

Electrochemical sensing – detect specific enzymes, and

Pressure/Accelerometers – extreme physical conditions such as head concussions

“There are many and various ways that you can do health monitoring,” explained Street. “There will be sensors, and local electronics with amplifiers and logic and switches. One of the prime features of printing is that it is a versatile system for depositing different materials.”

PARC has built an amazing printing system for R&D that includes different functional dispense heads for ink-jet, aerosol, and extrusion so that a wide varieties of viscosities can be handled. The system also include integrated UV-cure capability. Printing tends to have the right spatial resolution on the scale of 50-100 microns for the target applications spaces.

PARC worked on an early system to monitor for head concussions and store event information. They used printed PVDF material to print accelerometers and pressure sensors, as well as ferroelectric analog memory. Various commercially available materials are used to print organic thin-film transistors (OTFT) for digital logic. For complementary digital logic, different metals would conventionally be needed for contacts to the n-type and p-type TFTs, but PARC found an additive layer that could be applied to one type such that a single metal could be used for both.

A gas sensor prototype that can can detect 100-1000ppm of carbon-monoxide was printed using carbon nano-tubes (CNT) as load resistors. They printed a 4-stage complementary inverter to provide gain, using 7 different materials. “This is a case where a very simple device uses many layers,” explained Street. “Four drops of one materials does it, so you wouldn’t look at using a subtractive process for this.”

Rigid/flex integration

Dr. Azar Alizadeh, GE Global Rsearch, presented on “Manufacturing of wearable sensors for human health & performance monitoring.” Wearables in healthcare applications include medical, high exertion, occupational, and wellness/fitness. The Figure shows a flexible blood pressure-sensor that measures from a finger-tip. Future flexible devices are expected to provide more nuanced biometric information to enable personalized medicine, but any commercially viable disposable device will have to cost <$10 to drive widespread adoption. Costs must be limited because just in the US alone the annual amount spent to serve ~50M patients in hospitals is >$880B.

Finger-tip optical blood-pressure sensor created with printed photodetector by GE Corp.

Finger-tip optical blood-pressure sensor created with printed photodetector by GE Corp.