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WEBCASTS
 Environment, Safety & Health Date and time TBD The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.
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Wafer Processing Date and time TBD As the industry moves to 10nm and 7nm nodes, advances in wafer processing etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.
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Rudolph Technologies Inc. (RTEC) is partnering with a major outsourced semiconductor assembly and test (OSAT) services manufacturer to provide its inspection and metrology capability in the development of stacked packaging processes. The process uses silicon interposer technology, sometimes referred to as 2.5D IC, as an intermediate step toward full blown 3D ICs.
Di Ma spoke with Debra Vogler, senior technical editor, ElectroIQ, about TSMC's work with silicon interposers, die stacking with through-silicon vias (TSV), and gate-last transistor fab.
Package-on-package, implemented with flip chip package assembly, is meeting requirements for next-gen mobile devices. Challenges remain: fine pitch underfill, brittleness of ultra low-k (ULK) dielectrics, and shorting between adjacent bumps. Craig Mitchell, Tessera, examines the lucrative 3D packaging step and how to face these challenges.
Andrew Smith, Ventmark Technology Solutions, presents a 3D die stacking technology to address package miniaturization. Using bare die and vertical interconnect structures, this stacking technology permits the design of ultra-thin, near-CSP solutions without TSVs. Designers lacking custom ICs should look to new chip stacking technology.
While speculation abounds about what will be the next generation of memories and their applications, CNRS, a French government-funded research organization, has 4 new concepts of memories in 2010. The organization is actively recruiting collaborators on RE-RAM, A-RAM, MS-DRAM, and MELRAM memory technologies.
Xilinx (XLNX) debuted a stacked silicon interconnect technology for breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package. The stacked silicon package suits applications that require high-transistor and logic density, as well as intense computational and bandwidth performance. This article includes a podcast interview with the company about the technology.
Nanoplas introduced a fully automatic dry-processing batch system for high-volume 200mm production. The DSB 9000A is based on Nanoplas’s High Density Radical Flux (HDRF) technology.
PoP packages present some unique rework challenges, such as how to rework an underfilled package; also, these packages are prone to warpage. Inspecting the area array devices can be a challenge. Bob Wettermann, BEST Inc., discusses rework solutions.