11/14/2009 

Updates to a pair of reports from Yole Developpement aim to help better identify remaining integration challenges and high-volume production implementation strategies for 3D ICs and through-silicon vias (TSV).

11/04/2009 

Micron Technology says it is now sampling a multichip package combing its 34nm-based 4Gb SLC NAND flash and 50nm-based 2Gb low-power DDR DRAM memories, a combination it says offers better cost and power savings for mobile devices.

11/04/2009 

A new study suggests that through-silicon vias (TSV) with higher aspect ratios (20:1 or 10:1, vs. 5:1) offer a significant payback by saving space on a die, up to $700 per wafer.

10/26/2009 

Embedded computing modules employing "silicon circuit board" technology as an alternative to expensive ASIC developments offer advantages in performance and power for integrating memory and logic -- and are a practical alternative to 3D integration due to thermal and supply chain issues, explains siXis' David Blaker.

10/22/2009 

Specialty TSV foundry Allvia is expanding its manufacturing capabilities away from high-cost Silicon Valley to a newly-purchased facility in Oregon, a site with its own chip-equipment pedigree.

10/20/2009 

Bart Swinnen, IMEC's director of interconnect and process technology unit, discusses with SST/AP the research center's 3D program, from its annual press event in Leuven, Belgium.

10/16/2009 

Taiwan's Industrial Technology Research Institute (ITRI) will add Applied Materials to its partners for developing 3D chip stacking technology, by placing "a full line" of AMAT processing tools in its labs.

09/30/2009 

IMEC and its 3D integration partners have taped-out Etna, a new 3D chip integrating a commercial DRAM chip on top of a logic IC. The new 3D stack resembles as close as possible to future commercial chips. It consists of a 25µm thick logic die on top of which a commercial DRAM is stacked using through-silicon vias (TSVs) and micro-bumps.

09/16/2009 

Elpida Memory recently pushed vertical stacking of DRAM to new heights by connecting eight 1G chips using through-silicon vias, creating what it calls the world's largest-capacity DRAM with ~8GB of storage.

08/28/2009 

Vicky Wang, Henkel Loctite (China) Co. Ltd. and Dan Maslyk, Henkel Corp. show how underfill type and strategy will be key to enabling highly reliable PoP devices. Few studies have evaluated the effects of the underfilling strategy — such as underfilling the bottom component only or underfilling both top and bottom components — or the effects of solder alloy choice on the reliability of PoPs. This article presents findings from a recent study on the drop test reliability of PoP devices as a function of underfill dispensing type and PoP ball alloy type.

08/28/2009 

In this video interview from SEMICON West 2009, Bart Swinnen, reviews the established interconnect bonding and through-silicon via (TSV) technologies at the system-integration level. He also discusses the newer TSV possibilities and different application-specific TSVs.

08/10/2009  (August 10, 2009) SAN FRANCISCO, CA -- Karen Twillmann, executive director of corporate marketing at Brewer Science, and Dan Wallace, the company's director of 3D packaging, discusses the advances made by the company's temporary bond adhesive for wafer bond applications.

08/05/2009  The BrightSpots 3D IC Forum came to a close on Friday, July 24. Out of 3 topic areas covering technology progress, supply chain issues, and standards development, the discussions around technology progress were clearly the most active, both from a panelist and attendee perspective. What follows is a summary of each discussion. Where topics overlapped, and discussions were brief, the summaries have been combined into one.

08/05/2009  Steven Dwyer, VP & GM, North America at EV Group, provides highlights of 3D integration papers the company presented at SEMICON West. By achieving alignment accuracy down to 200nm, thin wafer handling at thicknesses <10μm, and 300mm-capable wafer bonding, he says the company is ready for whatever comes along.

08/05/2009  Larry Smith, sr. member of the technical staff in SEMATECH's 3D interconnect division, discusses toolset acquisitions at the U. of Albany's CNSE, where work focuses on replacing traditional global interconnect and intermediate level processes.

08/05/2009  Robert Rhoades, CTO, Entrepix, describes the nontraditional technology behind TFT-dual gate memory and how CMP enables that innovation among others -- e.g., TSVs, 3D packaging, MEMS, and engineered substrates.

08/04/2009  Bart Swinnen, director of interconnect and packaging in IMEC's process technology unit, discusses the status of 3D technology efforts -- in particular, IMEC's work on TSV tech that will enable higher aspect ratio TSVs suitable for thicker dies.

07/17/2009  Paul Siblerud, SEMITOOL, discusses the role of the EMC-3D consortium in developing new packaging technologies, such as through silicon vias (TSV). Jan Vardaman, TechSearch International, examines the barriers, and breakthroughs, around 3D integration.

07/17/2009  EV Group and Applied Materials say they will jointly develop wafer bonding processes for making through-silicon vias (TSV) in 3D IC packaging applications, working as members within the Semiconductor 3D Equipment and Materials Consortium (EMC-3D).

07/17/2009  EV Group and Applied Materials say they will jointly develop wafer bonding processes for making through-silicon vias (TSV) in 3D IC packaging applications, working as members within the Semiconductor 3D Equipment and Materials Consortium (EMC-3D).