06/30/2008  (June 30, 2008) It was a month for names in the news as acquisitions and evolving business strategies inspired executive appointments and reorganization; industry organizations added members and directors, and books got published. Company announcements came in from JP Sercel Associates, TRUMPF, Dage Precision Industries, ECD, Jordan Valley, Rogers Corp., Formfactor, Unisem Group, Mentor Graphics, and Alchimer.

06/18/2008  June 18, 2008 -- NEXX Systems, a provider of process equipment for advanced wafer-level packaging applications, will participate in IMEC's Industrial Affiliation Program (IIAP) on 3D integration.

05/30/2008  eG ViaCoat is the latest in Alchimer's eGTM series of electrochemical coating processes, for the metallization of high aspect ratio through-silicon vias (TSVs) used in advanced 3D packaging applications. It reportedly produces conformal, thin, uniform, and adherent copper seed layers, even on resistive barriers. It is said to enables significant reductions in cost of ownership (CoO) compared to dry vacuum processes.

05/22/2008  The "3D Integration North American Tour" came to San Jose on May 15 after stops in Durham, NC and Dallas, TX. The event, hosted by SUSS MicroTec, Surface Technology Systems (STS) and NEXX Systems outlined the current state of the art in through silicon vias (TSVs) and related technology.

05/21/2008  by Ed Korczynski, senior technical editor, Solid State Technology
May 21, 2008 - Masaaki Kinugawa, GM of Toshiba's Oita operations, discussed the tough challenges faced by fabs developing advanced processes today in his Confab talk, including increasing complexity of process and device technologies (and proportionally rising costs) -- and an ugly truth waiting around the corner at the 32nm node.

05/21/2008  by Bob Haavind, Editorial Director, Solid State Technology
May 21, 2008 - Beyond today's stacked chips in a package may come higher performance 3D stacked ICs using through-silicon vias to interconnect layers, according to Sitaram Arkalgud, who spoke on the economic implications of 3D at the ConFab in Las Vegas.

05/21/2008  by Ed Korczynski, senior technical editor, Solid State Technology
May 21, 2008 - While manufacturing of 3D ICs is today limited mostly to memory chip stacks and cell-phone camera modules, the next huge application seems to be the embedded memory in microprocessors. Subramanian Iyer, distinguished engineer and chief technologist of IBM's systems and technology group, explained the economic considerations behind 3D microprocessors at the ConFab in Las Vegas.

05/14/2008  EV Group, equipment manufacturer for semiconductor, MEMS, and nanotechnology applications, announced the opening of a subsidiary, EV Group Korea Ltd., in Seoul, Korea to serve as a direct-to-customer site for sales, service, and support efforts for EVG's existing and potential new customer base. The subsidiary will reportedly house sales, service, process/application and administrative capabilities.

05/06/2008  Last week's 3D/SiP Symposium hosted by SMTA, and co-sponsored by Advanced Packaging magazine, turned out to be an intimate gathering of approximately 55 attendees representing not only the U.S., but Canada, France, Japan, Taiwan, United Kingdom, Austria and the Republic of Korea.

05/06/2008  When the IEEE International Interconnect Technology Conference convenes at the Hyatt Regency San Francisco Airport Hotel, Burlingame, CA, June 1-4, the focus will be squarely on 3D technologies. Attendees will have the opportunity to gain both fundamental knowledge and practical manufacturing advice from 3D experts at chip companies and universities from around the world.

05/05/2008  Oerlikon Esec, provider of automated chip assembly equipment and system solutions for the semiconductor industry, formally introduced the introductory platform of an entirely new product family at an official unveiling during SEMICON Singapore. The Die Bonder 2100 xP targets the high-volume epoxy die attach market.

05/01/2008  You would think that because I’m a National Public Radio junkie, news would be of vital importance to me – any type of news.

04/23/2008  3D packaging is expected to emerge as a dominant performing solution in the electronic/chip packaging industry. Its performance promises to drive efforts across the entire supply chain to successfully deploy it, according to analysis reports from Frost & Sullivan's Global Trends in Electronic/Chip Packaging. Analysis indicates that the industry is moving beyond system on chip (SoC) to explore various forms of system in package (SiP).

04/14/2008  By Gail Flower, editor-in-chief
The ninth annual Burn-in and Test Socket Workshop (BiTS 2008) on March 9-12, 2008 in Mesa, AZ, presented an interactive, growing, and technical successful forum for experts dedicated to sharing knowledge. BiTS brought together 350 conference attendees and 60 exhibitors worldwide from users of sockets, boards, burn-in systems, handlers, packaging engineers, and suppliers to the industry.

04/09/2008  EMC^3D, an international semiconductor equipment and materials consortium dedicated to the cost-effective development of 3D through silicon via (TSV) interconnects, announced the addition of Datacon Technology to the organization. Datacon, manufacturer of die bonding & sorting equipment will provide high-precision assembly expertise to the consortium.

04/01/2008  By Fran

03/11/2008  by Bob Haavind, Editorial Director, Solid State Technology
An insightful update on three key semiconductor technologies -- SOI, TSV/3D, and SOI -- sparked a lively Q&A following a SEMI-sponsored breakfast near Boston (Mar. 5), held at an MKS Instruments facility. Here, Gordon Starkey, a senior engineer in technical operations for IBM, explained how silicon-on-insulator (SOI) has made a transition from a niche to mainstream technology.

03/11/2008  by Bob Haavind, Editorial Director, Solid State Technology
An insightful update on three key semiconductor technologies -- SOI, TSV/3D, and SOI -- sparked a lively Q&A following a SEMI-sponsored breakfast near Boston (Mar. 5). Here, Gregory Denbeaux, assistant professor of nanotechnology at the U. of Albany, gave an overview of progress needed in EUV to make it suitable for high volume manufacturing.

03/11/2008  by Bob Haavind, Editorial Director, Solid State Technology
An insightful update on three key semiconductor technologies -- SOI, TSV/3D, and SOI -- sparked a lively Q&A following a SEMI-sponsored breakfast near Boston (Mar. 5). Here, Sitaram Arkalgud, head of SEMATECH's 3D interconnect program in Albany, discusses the expected evolution of through-silicon vias (TSVs) and 3D chip stacks for future electronics.

03/03/2008  This intuitive cost-of-ownership (CoO) tool model is specifically designed to evaluate the cost of a given through-silicon-via (TSV) process flow. It has been developed using Excel so as to be widely exploitable and upgradable. This CoO tool will enable evaluation of the cost/wafer level for manufacturing TSVs using user inputs or pre-defined parameters.