03/03/2008  ; This article is the third in a series on 3D packaging technology, and summarizes information presented during a January 2008 webcast hosted by Advanced Packaging magazine. Participants were: Fred Roozeboom, Research Fellow, NXP Semiconductors and professor at TU Eindhoven; Kai Zoschke, Research Engineer for Fraunhofer IZM; and Thorsten Matthias, Director of Technology North America, EV Group.

02/21/2008  by Ed Korczynski, Senior Technical Editor, Solid State Technology
A new report from TechSearch International forecasts millions of silicon wafers will be made with through-silicon vias (TSV) in the year 2014. With TSV technology now moving past the feasibility (R&D) phase and into the commercialization phase, the question isn't whether this 3D interconnect will be adopted, but how soon it will balance cost/performance vs. existing technologies to break into real mainstream use.

02/13/2008  ; A new study reports that 3D through-silicon vias (TSV) will eventually be adopted, but the timing for mass production depends on how the cost of the new technology compares with that of existing technologies. Design, thermal, and test issues remain a barrier to TSV adoption in some applications, although progress is being made.

02/04/2008  adapted for print by AP editors

This article is the second in a series on 3D packaging technology, and summarizes information presented during a December 2007 webcast produced and hosted by Advanced Packaging magazine. Participants included: Dan Schmauch and Rozalia Beica, Semitool Inc.; Jean-Marc Thevenoud, Alcatel MicroMachining Systems; and Markus Wimplinger, EV Group.

01/21/2008  adapted for print by AP editors

This article, the first in a series of three on 3D packaging technology, summarizes information presented during a November 2007 webcast produced by Advanced Packaging magazine. Participants were Jean-Christophe "J.C." Eloy, founder and GM of Yole D

01/01/2008  Packaging technology has evolved over the years, transitioning into more of a revolution with the introduction of new packaging styles practically every month. Designers face designing extremely high-performance packages with mixed technology content such as high speed digital, analog, and RF.

12/05/2007  December 5, 2007 - EV Group (EVG) and Brewer Science say they have demonstrated temporary wafer bonding capabilities for a wide range of backside processes, including through-silicon vias (TSVs) and backside metallization, using an approach optimized for high-temperature advanced packaging applications.

12/04/2007  ; Agilent Technologies Inc. and Multiprobe Inc. today announced their intent to expand the companies' strategic partnership. As a result, Agilent will sell and support Multiprobe's Multiscan atomic force prober (AFP) to customers in Asia and Japan.

11/20/2007  November 20, 2007 - STATS ChipPAC says it will expand its flip-chip offerings to its Shanghai, China operation, encompassing wafer bump, sort, assembly and final test. Volume production is expected to start in 1H08, followed by a second phase adding electroplated wafer bumping capabilities for 200mm wafers in 1H07 and 300mm wafers in 2H08.

11/14/2007  ; Fred Roozeboom, Ph.D., research fellow at NXP Semiconductors Research and a professor at the Eindhoven University of Technology, has agreed to join the EMC3D consortium and provide technical advice and guidance in support of the EMC3D effort to quickly bring the technology of through-silicon via (TSV) chip stacking to market.

11/14/2007  Actel Corp. has announced it is offering its low-power 5mW IGLOO field-programmable gate arrays (FPGAs) in a 4-mm package with a 0.4-mm ball pitch, reportedly the smallest package for any programmable logic device on the market.

11/06/2007  November 6, 2007 - AMD, Carl Zeiss SMT, and Qimonda AG are forming a 12M euro (US ~$17.4M) "innovation center" in Dresden, Germany ("Silicon Saxony"), under a larger "Nanoanalysis" project to develop new analytical and characterization methods for next-gen chip development.

11/02/2007  By Rudi Cartuyvels, IMEC

3D integration explores the possibilities to interconnect active devices in different 2D planes. These interconnects can be considered at different levels of the wiring hierarchy, from the package, over global, to local interconnect levels. The future looks bright for 3D integration, as it promises to become a Holy Grail for system integration with uses in electronics, consumer, automotive, medical, office, and networking applications.

10/29/2007  While the industry struggles to continue on the Moore's Law track, 3D approaches superior to those of systems-on-chip may provide an interim solution if the shrink slows down. A SEMATECH-organized workshop in Albany, NY earlier this month (Oct. 11-12) addressed fundamental issues about 3D, including four reasons why every chipmaker has 3D/TSVapproaches on its roadmap, and what needs to be solved before 3D can be effective beyond simple memory.

10/16/2007  For an editor of a semiconductor manufacturing publication, there are several sides to every trade show. On one hand are the technical sessions, where we get a glimpse of the latest and greatest technologies being developed. On the other hand, are the industry players

10/15/2007  By Happy Holden, Mentor Graphics, Inc.
3D packaging technology is evolving rapidly to improve functionality and performance while maintaining a compact form-factor. Embedded passive components (EP) will play a major role in all of these 3D schemes.

09/25/2007  SUSS Microtec, NEXX Systems, and Surface Technology Systems (STS), manufacturers of semiconductor process equipment, announced their collaboration with Fraunhofer IZM to demonstrate integrated process solutions for 3D wafer-level packaging (WLP).

08/22/2007  Lam Research Corp. has shipped its first 300 mm 2300 Syndion etch system, designed for 3-D IC through-silicon via (TSV) etch applications.

07/31/2007  A polymeric spin-on coating, WaferBOND HT-250, temporarily attaches device substrates to a carrier substrate, enabling wafer thinning and subsequent processing. It will reportedly permit advanced packaging processes such as the creation of through-silicon vias (TSVs), 3D stacking, and other etching, plating, and follow-on processes.

07/23/2007  Alcatel Micro Machining Systems will provide two 200-mm DRIE and LTPE CVD systems at CEO/Léti-Minatec R&D institute under a joint development agreement. The parties will collaborate to develop and demonstrate a suite of turnkey silicon microvia technologies for 3D integration at wafer and die levels.