07/20/2007  By Bob Haavind, editorial director, Solid State Technology

3D chip packaging with through-silicon vias (TSVs) will transform the industry over the next 3–5 years, say presentations and discussions at SEMICON West. Using TSVs could enable compact packaging with increased performance. Two approaches to TSV are leading the evolution.

07/19/2007  Amkor, IMEC collaborate on 3D wafer-level packaging

07/19/2007  July 18, 2007

07/18/2007  July 18, 2007 - IMEC has expanded its 3D packaging research program to fully exploit the potential of novel 3D technologies. Besides 3D interconnection technologies developments, the program is extended with research on system design methodologies. Both the technology and design sub-programs will be based on actual system requirements and closely coupled.

07/18/2007  July 18, 2007 - At SEMICON West, Amkor Technology Inc., a provider of advanced semiconductor assembly and test services, and IMEC, the independent nanoelectronics and nanotechnology research center based in Belgium, announced that they have entered into a 2-year collaboration agreement. They will develop cost-effective, 3D integration technology based on wafer-level processing techniques.

07/10/2007  As another SEMICON West opens, IMEC's experts discussed with WaferNEWS what they see are they major keys to the future of semiconductor industry: exploring new markets, bringing finFETs into manufacturing, mastering 3D integration, and addressing sub-32nm low-k deposition challenges.

06/12/2007  June 12, 2007 - Tezzaron Semiconductor says it is ramping its 2D "3T-iRAM" line of 72Mbit memory devices at Singapore foundry Chartered Semiconductor on the foundry's 0.13-micron process technology, and plans to use this SRAM drop-in replacement as the basis for its first 3D ICs. Robert Patti, Tezzaron CTO, discusses both technologies with WaferNEWS.

06/12/2007  Samsung, Hynix, and Akita Elpida have all made announcements recently about their latest achievements in memory stacking technology. There was definitely a competitive tone to these releases, but they actually appear to be pushing somewhat different agendas.

06/11/2007  June 11, 2007 - STATS ChipPAC Ltd. says it will sell certain assembly and test assets for its discrete power packages to China's Ningbo Mingxin Microelectronics Co. Ltd., following a similar transaction a year ago to farm out some work to mainland China in order to pursue better growth opportunities in areas such as system-in-package, flip-chip, and 3D technologies.

06/07/2007  June 7, 2007 - Tronics Microsystems SA and Alcatel Micro Machining Systems (AMMS) say they will jointly develop deep reactive ion etch (DRIE) systems for "extreme-performance" MEMS.

06/01/2007  By Phil LoPiccolo, Editor-in-Chief

Among the most significant developments in interconnect slated to appear at this month's International Interconnect Technology Conference (IITC, June 4-6, in Burlingame, CA) involve 3D chip architectures. Sitaram Arkalgud, director of SEMATECH's interconnect division and its newly created 3D interconnect initiative, calls 3D chip architecture his "new religion," because stacked chips allow interconnects to be much shorter than...

05/31/2007  e2v, developer and manufacturer of electronic components and subsystems, has announced a new generation of high-sensitivity imaging sensors that leverage technology from Tracit Technologies, a new division of the Soitec Group.

05/21/2007  In the new consumer-driven electronics industry, where beating your competition to market with innovative technology is the surest route to success, process control equipment suppliers have an expanded role in manufacturing alliances to help dramatically shorten product-development and production-ramp times, and thus significantly improve yield and profitability, according to Brian Trafas, chief marketing officer at KLA-Tencor, in his talk at the Confab in Las Vegas.

05/14/2007  May 14, 2007 - STATS ChipPAC has formally established its new R&D facility in Singapore, to develop next-generation technologies including through-silicon vias (TSV), microbump bonding methods for 3D die, silicon substrate-based system-in-package solutions, and embedded active die technology.

05/08/2007  Among the most significant developments in interconnect to look for at the upcoming International Interconnect Technology Conference (IITC, June 4-6, in Burlingame, CA) are those involving 3D chip architectures. Sitaram Arkalgud, director of SEMATECH's interconnect division, discusses the "new religion" of 3D chip architecture with WaferNEWS, and explains why it's the most promising route to eliminating the main stumbling block to higher chip speeds and lower power consumption.

04/23/2007  Samsung Electronics Co., Ltd., has developed an all-DRAM stacked-memory package using through-silicon vias (TSVs) housed in aluminum pads to avoid performance slow-downs caused by the redistribution layer. The company applied a proprietary wafer-thinning technique to eliminate warped die in the low-profile package.

04/18/2007  The IEEE components, packaging, and manufacturing technology (CPMT) society — an international forum for scientists and engineers in microsystems packaging design and manufacture R&D and development — named professor Herbert Reichl, director of Fraunhofer IZM, recipient of its electronics manufacturing technology award.

04/13/2007  April 13, 2007 - IBM says it has developed a way to incorporate through-silicon vias (TSV) into its chipmaking process that shortens data-travel distances by up to 1000x and allows for 100x more pathways than 2D chips. Samples of 65nm chips using the 3D stacking technique will be shipped by year's end, with production ramping in 2008.

04/05/2007  April 5, 2007 - Ziptronix Inc. and Raytheon Vision Systems (RVS) say they have demonstrated compatibility of Ziptronix's "direct bond interconnect" (DBI) interconnect technology with multilayer CMOS IC processes, involving 3D integration of five-layer metal 0.5-micron CMOS devices with silicon PIN detector devices.

03/14/2007  March 14, 2007 - Elpida Memory Inc., a Japanese supplier of dynamic random access memory (DRAM), has entered into a multi-year partnership with IMEC, an independent nanoelectronics research center, to perform R&D for beyond 50nm DRAM process generations, said IMEC today.