3D Integration

3D INTEGRATION ARTICLES



System-in-Cube Technology Addresses Parasitics, KGD

03/06/2007  Irvine Sensors Corporation demonstrated its 3D packaging technologies to stack four 500-mHz DDR memory chips without operating-speed degradation, which was verified by the chip maker. The company will now explore commercial exploitation of packaging techniques for the memory chips.

Consumers, Integration Dictate Future of MEMS, 3-D Packages

01/24/2007  The future of MEMS and 3-D packages relies on similar factors — consumer drivers and increased integration — according to industry analysts. 3-D integration will affect MEMS and IC packaging industries, says Yole Développement's "3-D ICs." Advanced packages require acceptance from the consumer market to reach targets for technological advancement, commercialization, and sector revenues.

Qimonda's Arkalgud to head up SEMATECH's 3D program

01/05/2007  January 5, 2007 - SEMATECH has appointed Sitaram Arkalgud, appointee from Qimonda/Infineon Technologies, as director of its new 3D interconnect initiative, in addition to his duties leading SEMATECH's interconnect division.

Samsung touts 3D methods, multilayered dielectric in new 50nm DRAM chip

10/19/2006  October 19, 2006 - Samsung Electronics Co. Ltd. says it has developed a 50nm DDR2 DRAM chip utilizing 3D design and multilayered dielectrics, a process that enhances performance and data storage capabilities.

Consortium to develop cost-effective 3D interconnects

10/12/2006  October 12, 2006 - A list of equipment providers, materials companies, and researchers have joined to create an international consortium to address technical and cost issues of creating of thru-silicon-via (TSV) 3D chip interconnect, for use in chip stacking and MEMS/sensor packaging.

SanDisk widens memory reach with Msystems deal

07/31/2006  July 31, 2006 - In the latest big move to consolidate power in the memory sector, flash memory giant SanDisk Corp., Milpitas, CA, has agreed to acquire Msystems Ltd., Kfar Saba, Israel, in an all-stock deal valued at up to $1.55 billion, including stock options and convertible debt.

ICOS, IMEC to develop 3D packaging metrology

07/27/2006  July 27, 2006 - ICOS Vision Systems Corp. NV and European R&D center IMEC have agreed to collaborate on development of metrology methods targeting 3D packaging processes for ICs, including wafer-level packaging, flip-chip, systems-in-package, and microelectromechanical systems (MEMS).

Cookson, Microbonds combine insulated wire bonding, mold compounds

07/06/2006  July 6, 2006 - Cookson Electronics Semiconductor Products and Microbonds Inc. have formed a codevelopment project to combine Microbonds' X-Wire insulated wire bonding technology with Cookson's Plaskon family of mold compounds.

Package-on-Package Trends and Technology

07/01/2006  Destined for Growth

STATS ChipPAC handing low-end packaging ops to China firm

06/26/2006  June 26, 2006 - STATS ChipPAC Ltd., a provider of semiconductor test and packaging services, has signed a deal with China Resources Logic Ltd. to set up a JV in Wuxi, China, providing assembly and test service for STATS' lower-end leadframe package families, allowing the firm to focus on more leading-edge products such as system-in-package, flip-chip, and 3D technologies.

FlipChip, Engent to make 3D packaging tech

05/26/2006  May 26, 2006 - FlipChip International LLC and Engent Inc. are partnering to develop 3D wafer-level CSP (WLCSP) technologies, seen as a low-cost alternative to system-on-chip for highly integrated stacked die packaging applications.

iNEMI Takes Roadmap Workshop to Asia

05/15/2006  Herndon, VA — The International Electronics Manufacturing Initiative (iNEMI) will hold a 2007 Roadmap workshop in Shanghai, China, in tandem with the High-density Microsystem Design and Packaging and Component Failure Analysis in Electronics Manufacturing (HDP) 2006 conference. The half-day workshop will take place June 27, 2006, on the Yan Chang Campus of Shanghai University.

SEMATECH 3D project seeks interconnect answers

02/09/2006  February 9, 2006 - SEMATECH has launched a new project to explore the feasibility of three-dimensional (3D) interconnect technology for the semiconductor industry.

Ziptronix reports first 3D SoC

09/26/2005  September 26, 2005 - Ziptronix, Morrisville, NC, has made good on its efforts at creating a three-dimensional IC device to serve as an alternative to system-in-package (SiP) technology, according to a company statement.

RSL opens packaging R&D lab with Suss MicroTec

08/10/2005  August 10, 2005 - RoseStreet Labs (RSL), Phoenix, AZ, has announced the opening of its 3D Research and Development laboratory for next-generation semiconductor packaging, as well as an alliance with Suss MicroTec, which will provide the lab with a full suite of lithography and 3D packaging equipment.

Ziptronix appoints Phil Nyborg as new CEO

03/02/2005  March 2, 2005 - Ziptronix has appointed 17-year semiconductor industry veteran Phil Nyborg as its new president and CEO. The company said that Nyborg will guide it as it more fully commercializes its proprietary bonding and interconnect processes for 3DICs.

APEX EXTRAVAGANZA

03/28/2003  The following companies will be exhibiting these products at APEX 2003, taking place Monday, March 31 through Wednesday, April 2 in Anaheim, Calif. Be sure to visit them to see their latest innovations, and pick up SMT's official Show Daily for more product coverage. ( March 28)
Click here for these and more product briefs.

Amkor to expand development of 3D IC packages

04/05/2001  April 5, 2001 - West Chester, PA - Amkor Technology is expanding its development and qualification of 3D IC packages in order to reduce production costs and handling time. 3D or stacked ICs also require less space, have higher reliability and better electrical performance than the combination of devices they replace, the company said.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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