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Sartorius and ProMetic announce two agreements

04/05/2006  April 3, 2006 -- /MARKET WIRE/ -- GOETTINGEN, GERMANY, and MONTREAL, CANADA -- Sartorius AG and ProMetic Life Sciences Inc. announced today the signing of a collaboration agreement utilizing bioseparation systems to recover proteins from human blood plasma.

Renesas Technology joins International SEMATECH Manufacturing Initiative

04/05/2006  April 3, 2006 -- /MARKET WIRE/ -- AUSTIN, Texas -- Japanese semiconductor leader Renesas Technology Corp. has joined the International SEMATECH Manufacturing Initiative (ISMI), adding momentum to the two-year-old manufacturing-oriented microchip consortium, and increasing Renesas' access to cutting-edge technology.

Millisecond annealing for USJ dopant activation

04/04/2006  By Debra Vogler, Senior Technical Editor

At a seminar at San Francisco's Moscone Hall, a leading technologist surmised that millisecond annealing for USJ dopant activation will be pushed out to the 45nm node, but flash/RTA (rapid thermal annealing) or laser annealing will be needed at the 65nm node for poly depletion improvements.

FEI CEO steps down

04/04/2006  April 4, 2006 - FEI Co., Hillsboro, OR, said that its president and CEO Vahe Sarkissian has resigned, and will step down from his chairman/board position prior to the company's annual shareholders meeting on May 11.

Intel prepping 65nm NOR flash

04/04/2006  April 4, 2006 - Intel Corp. said it is the first company to offer NOR multilevel cell (MLC) flash memory chips at 1Gbit density using 65nm process technology, with samples available to customers by June.

IMEC unveils bendable chip package

04/04/2006  April 4, 2006 - IMEC and its associated laboratory at the U. of Ghent have developed a new process flow for ultrathin chip packages resulting in bendable packaged chips. The process has been demonstrated with silicon chips thinned down to 20-30µm, with total thickness of 50µm.

Samsung ramps 1Gbit/70nm flash output

04/04/2006  April 4, 2006 - Samsung Electronics Co. Ltd. has ramped to mass production of 1Gbit OneNAND flash memory devices, using 70nm process technology that achieve 70% greater efficiency than the 90nm process.

Toshiba merges ASSP, embedded SoC units

04/04/2006  April 4, 2006 - Toshiba America Electronic Components Inc. has merged its ASSP and embedded processor SoC business units into a single operation.

Applied joins SRC for input into R&D agenda

04/04/2006  April 4, 2006 - Applied Materials Inc. has joined the Semiconductor Research Consortium (SRC), a university research consortium spun out from the Semiconductor Industry Association (SIA) as a research cooperative supporting the domestic semiconductor industry.

Intel SCQI Awards Tout Packaging

04/04/2006  Santa Clara, CA — Out of 12 recipients of the 2005 Intel's prestigious Supplier Continuous Quality Improvement (SCQI) award, five are from the packaging industry.

Owlstone Nanotech hires security screening veteran

04/04/2006  Owlstone Nanotech Inc., a developer of nanotechnology-based chemical detection products, announced that it has appointed Bret Bader to the position of chief executive officer. As CEO of Owlstone, Bader will be responsible for developing and executing the strategic direction of the company.

Nano toolmaker's CEO steps down

04/04/2006  FEI Co., a Hillsboro, Ore., maker of focused ion- and electron-beam tools for nanoscale characterization and research, announced late Monday that Vahe Sarkissian has stepped down as the company's chairman, president and chief executive officer and will be leaving the company. Sarkissian, who joined the company in 1998, would also resign as a director prior to the company's annual shareholder meeting on May 11.

Skystar expects to receive Chinese government's new GMP certification for its new facility in the third quarter

04/04/2006  March 30, 2006 -- /MARKET WIRE/ -- XI'AN, CHINA -- Skystar Bio-Pharmaceutical announced today that it expects to complete it's new, state of the art manufacturing facility by the end of September.

Stress-free Modeling for ICs

04/03/2006  IC packages are becoming more and more complex as time forges ahead; therefore, designing and building a cost-effective, robust product in a shrinking time-to-market window first poses challenges for the packaging industry. Most often, today's packaging OEMs take on an incredible amount of risk and investment resources in the prototype stage.

Keynote Explains 3-D Stacking

04/03/2006  The main purpose of 3-D stacking of semiconductor die is not to save space — it is to save time. "To bring cells closer together by stacking them vertically, so that they are connected through only the thickness of the silicon," explained Philip Garrou, Ph.D., of RTI International. "Die stacking is not bringing more integration into the IC, but disassembling it."
By George Riley, Ph.D., contributing editor