Author Archives: ssteditor

At the recent ECTC conference, various presentations addressed silicon interposers for 2.5D (Shinko), CoWoS reliability (TSMC) and microbumping (imec).

Dr. Phil Garrou, Contributing Editor

Shinko and CEA Leti detailed their presentation entitled “Warpage Control of Silicon Interposer for 2.5D Package Applications.”

Large silicon-interposers when attached to an organic substrate can cause significant warpage problems. Shinko/Leti examined several warpage control techniques including:

  • Using a “chip first process” where chips are mounted on the interposer first vs “chip last process” where the silicon-interposer is mounted on the organic substrate first and chips are mounted onto the interposer last.
  • Using various underfill resins.
  • Using Sn-57Bi solder and thus lowering peak temperature 45-90 degree C. This reduced warpage after reflow to 75% of that using SAC305.

Warpage of silicon-interposer using three types of underfills for 0 level assembly (micro bumps) were investigated. Maximum warpage using U.F. A1, A2 and A3 were 108, 123 and 132mm, respectively. The lowest warpage was obtained at using U.F. A1. With U.F.A3, solder bump open failures were observed. The authors conclude that “using underfill material with low Tg and high storage modulus for 0 level leads to high reliability.”

TSMC and customer Xilinx presented “Reliability Evaluation of a CoWoS-enabled 3D IC Package” which used FEA to study the thermo-mechanical response of the interposer-based package during thermal cycle reliability stressing. Focus was especially on the fatigue failures of the C4 and BGA joints. Experimental data collected on CoWoS test vehicles were used to validate the FEM models. Parametric study of key package material and geometric parameters was performed to analyze their effects on C4 bump thermal cycle reliability. Package materials of interest include UF (underfill), lid and substrate, and the geometric parameters include lid thickness and C4 bump scheme.

Results showed that the CoWoS package using AlSiC lid has better C4 bump life than the CoWoS package using Cu lid. While a thicker lid has the higher stiffness and better co-planarity, the higher constraint from the thicker lid induces higher stress inside the package which negatively impacts C4 bump fatigue and the micro-bump Ti/Al delamination.

C4 bump layer underfill with Tg of 70°C or 120°C, were studied. The underfill with lower Tg has higher driving force to C4 bump fatigue. When temperature is above Tg, the underfill has much lower Young’s Modulus which has much lower capability to protect C4 bump; and therefore the underfill with lower Tg has higher driving force to C4 bump fatigue. On the contrary, the underfill with lower Tg has lower driving force to Ti/Al delamination in the micro-bump structure. The C4 underfill with lower stiffness can play as a buffer layer and results in lower driving force to Ti/Al delamination in microbump.

imec reported on “Key Elements for Sub-50μm Pitch Micro Bump Processes.” Scaling the microbump pitch from hundreds to a few tens of microns is not straightforward. Several process parameters need to be taken into account to allow a reliable Cu(Ni)Sn ubumping process. One of the challenges for fine pitch Cu(Ni)Sn stacking is to obtain a high bump uniformity. The non-uniformity prevents Cu and Sn from having good contact and subsequent intermetallic formation and increases the risk of underfill entrapment.

A bump scheme that offers better margin for alignment error is better based on a scheme where the size of top die bumps is smaller than the size of the bottom pads. For example it is better to achieve 20μm pitch with 7.5μm bump on 12.5μm pad than with 10μm bump and pad because equal bump and pad diameter can tolerate only 2μm misalignment whereas the 7.5μm/12.5μm bump/pad can tolerate 5μm. This is a significant difference when working close to the stacking tool’s limit of alignment accuracy.

Details on the plasma treatments necessary when attempting to plate into these fine featured plating resists are also discussed.

BOBBY ISAACS and ANYA CORNELL, Texas Instruments, Dallas, Tex.

Results can depend on the properties of the wafers used, the conditions of the implant, the conditions of the anneal process, and even the measurement technique.

Semiconductor chip geometries continue to shrink, causing once unimportant parameters in the manufacturing process to become more critical. With the shrinkage in transistor size and requirements for improved precision in devices, ion implantation has become an increasingly more delicate and accurate operation. Implantation angle has become extremely important as transistors have decreased in size and voltage specifications. Adjustment and pocket implants, channeling implants, and high accuracy sidewall and HALO implants have become requirements for high performance, with little to no tolerance for incorrect implantation placement.

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FIGURE 1. Illustration of wafer slicing angle and associated offset.

Older generations of ion implanters have been designed with only cursory regard to the extreme precision now required for implant placement. Because of this, semiconductor manufacturers must regularly monitor the implantation angle of these tools as part of normal production operations. In this monitoring, multiple potential issues exist that could cause a misinterpretation of the proper implantation angle, resulting in faulty tool calibration or production of out of tolerance product. This article will describe several variables to be considered when defining the angle of implant for a tool, and offer recommended conditions to achieve reliable and repeatable performance on two older implant tool sets.

The standard production test to determine if the angle of implant is accurate involves implanting 5 to 7 wafers tilted around a theoretical channeling angle, annealing the wafers to activate the implant, and charting the sheet resistance vs. implanted angle to find the channel. This procedure is commonly called a V-curve test. The as-measured channeling angle (found by identifying the minimum sheet resistance of the charted curve for the wafers, or the bottom of the “V”) should be equal to the theoretical channeling angle if the tool set-up is accurate. Unfortunately, the number of steps required by this procedure introduces errors that could lead to a false result. The properties of the wafers used, the conditions of the implant, the conditions of the anneal process, and even the measurement technique can all significantly affect the outcome.

Experimental
One of the most commonly overlooked variables that can introduce significant error into measurement of the angle of implant is the wafer which is used for the testing. One relevant silicon property of the wafers, the surface orientation angle offset (angle tolerance of the on-axis cut), has a significant effect. All wafers have a base surface orientation angle offset, as required by the process of slicing the wafers from the ingot (FIGURE 1).

This offset can directly translate into an offset in the V-curve measurement, depending on the angular rotation of the slice. It has been shown in previous work[3] that channeling is minimized at implant angles higher than 0.5°. In this work, the effect of the orientation angle offset on channeling was similarly studied. Implants were performed with 200mm, , N-type (phosphorus-doped) CZ wafers of resistivity 3-5 Ω-cm, surface orientation angle of 0.0+/-1°(on-axis ), Oi spec of <=32 ppma (ASTM-79), and LLS of <20 @0.20µm. The wafer type was chosen for use with Boron implant (P-type dopant) and the orientation was picked for its good channeling properties. Using the above specification, wafers were chosen at various extremes of the angle window (close to 0° and close to 1°) in order to characterize the effect of wafer angle variation. Other silicon properties shown in the spec above, such as surface defects, oxygen concentration, and resistivity are in the standard range for a typical test wafer. These parameters have a lesser effect on the implant angle measurement and were not explored in this study.

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FIGURE 2(L). Comparison of Varian E500 V-curves generated using Thermawave vs TRS-100. FIGURE 3(R). Effect of wafer orientation angle offset on V-curve of Axcelis Optima MD.

The two implant tool types used were an Axcelis Optima MD implanter and a Varian E500 implanter. Implant conditions were chosen as follows based on experimentation and comparison of common processes among multiple manufacturing facilities utilizing several tool types: Boron11 at 100 keV energy, 1.0e14 ion/sq dose, 35° tilt, and 0° twist. Boron11 was chosen as the dopant for its small mass and channeling properties, as discussed in Downey, et.al.[2] Energy of 100 keV is high enough to prevent outgassing of the dopant during the anneal process, and 1.0e14 ion/sq dose was chosen to place the resultant resistance as measured on a standard Tencor RS-100 into a stable range for the measurement equipment.[1] For all tests, the ion beam was optimally tuned to minimize beam instability or non-linearity. The potential process variables influencing beam steering on the tool were not explored during this experimentation, but it should be commented that an improperly tuned ion beam will also significantly affect the result. A tilt angle of 35° was chosen as the optimal channeling condition. Although multiple potential channeling angles exist for [100] N-type silicon wafers, the angle of 35.26o has shown the most sensitive, clear channel for implant angle testing[1], and it is also recommended by Varian Semiconductor[4]. A twist angle of 0° was applied for best resolution of the channel in all but one of the tests, which utilized a rotation angle of 90° to characterize the effect of the wafer substrate angle offset.

The anneal process needed to be selected in such a way as to eliminate any variation or sensitivity due to temperature of anneal, anneal time, or even annealer tool type. An anneal temperature of 1060oC for 30 seconds was selected from earlier work[1] as the condition at which small temperature variations can be tolerated. Two types of annealer tools were used – an Axcelis Summit furnace annealer, and an AG Associates 8800 lamp annealer – to determine if the V-curve could be shifted through anneal by varying the tool type.

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FIGURE 4. Effect of wafer orientation angle offset and wafer rotation on V-curve of Varian E500

Measurement of sheet resistance is well documented for ion implant processing. For this experimentation, Thermawave and Tencor RS-100 measurement tools were researched to identify possible areas of concern in the measurement of V-curve wafers. The advantage to Thermawave processing is the elimination of the need for anneal after implant, removing this source of potential variation. Also, a previous experiment with a different implant has shown that the Tencor RS-100 produces a sharper V-curve than the Thermawave (see sample V-curve in FIGURE 2). Therefore, the Tencor RS-100 tool was chosen for the present work. Testing on the Tencor RS-100 was performed using both 9-point and 49-point radial measurement patterns.

Results and discussion
By far the strongest effect was observed from the silicon wafer orientation angle offset. In particular, at angles above 0.5o, the effect was so pronounced that it shifted the V-curve. See below graph of two sets of wafers processed with identical implant and anneal conditions. The only difference was the orientation angle offset (0.04° vs 0.68°), as shown in FIGURE 3.

In an effort to further characterize the effect of a larger orientation angle offset of the wafers, testing was performed by rotating the wafers 90o during the implant to measure the change in the resultant V-curve. Using wafers with very small surface orientation offset angles (0.04o), the change in the measured V-curve could not be easily seen. However, using wafers with a surface orientation offset angle above 0.5o (0.68o), the change in the measured rotated V-curve became much more visible (FIGURE 4). Repeatability of the tests using high surface orientation angles was also noted to be inconsistent, with significant variance in results from test to test.

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FIGURE 5. Effect of anneal tool and temperature on V-Curve of Varian E500.

Based on the results presented above, it is our recommendation that high-angle offset wafers (above 0.5°) should not be used for implant angle qualifications. It is also recommended that the surface orientation angle of the test wafers be scrutinized if the V-curve produced shows abnormal variance from the expected outcome. To reduce variability from other wafer parameters, we also recommend a tight resistivity specification (ex: 3-5 ohm-cm) for the silicon ingot, and advocate the use of wafers not only from the same ingot, but from the same area of the ingot, to ensure similar properties.

Minor effects were observed from other variables studied. An experiment comparing two anneal temperatures confirmed earlier findings1 of 1060C being the optimal temperature to produce a sharper V-curve (FIGURE 5). The type of anneal tool was also a factor. Although the process was matched as closely as possible through matching of the thermal budget, a difference could be seen between the annealer types (Fig. 5, left). Based on the clarity of the V-curve inflection on the lamp annealer, this tool was used as the benchmark for anneals during other experiments.

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FIGURE 6. Effect of measurement map resolution on V-Curve of Axcelis Optima MD.

As for the Sheet Resistance measurement, very little to no effect was observed from varying the measurement pattern and number of measured points. A 9-point measurement showed the same accuracy as a 49-point measurement, making the additional points unnecessary (FIGURE 6).

Conclusion
As a result of this testing, multiple recommendations can be made to ensure accurate and repeatable measurement of the implant angle of a tool. These areas can result in significant variation of results if not accounted for during testing. The silicon quality of the wafers is one of the most overlooked variables in performance of implant angle measurement. The surface orientation angle offset can significantly change the measured implant angle, especially in ranges above 0.5° (from on-axis cut). Wafers with angle cut tolerance greater than 0.5° produce inconsistent results, severe enough to shift the sheet resistance values or even the entire V-curve, and are therefore not recommended for implant angle testing.

The parameters used in implantation also contribute significantly to the resolution and accuracy of a V-curve test. Although multiple potential channeling angles exist for [100] N-type silicon wafers, a 35° angle is recommended as the most sensitive, clear channel for implant angle testing.[1,4] The implanted species, energy, and dose all contribute to the stability and repeatability of the measurements. Once implanted, the anneal of the wafer must be tuned to a temperature and thermal budget that minimizes variation, as this will also cause slight changes in results. Finally, measurement techniques can change the outcome of a V-curve test through differences in the measurement tool used.

Once the angle of implant of a given tool is characterized, regular verification (qualification) is highly recommended, especially for events which involve components handling wafer orientation. To save on wafer cost, a test may be performed using 1 or 3 wafers once the baseline sheet resistance of the channeling angle is obtained, and charted through standard SPC techniques. If a failure is observed, escalation of the testing can then include a full 5 or 7 wafer V-curve test to determine if the angle of implant has shifted. Standard troubleshooting for common sheet resistance failure events should be included in disposition of a failure, since hardware issues in the form of leaks, contamination and other failure modes can influence the sheet resistance measurement obtained during angle testing.

Acknowledgments
The authors would like to thank TI silicon material technologist Thomas McKenna for valuable insight into starting material properties, as well as Jeff Bell of SUMCO-USA for providing substrate orientation angle data.

1. Rathmell, M.A. (2006). Implant Angle Monitoring – A Comparison of Channeling Features. Ion Implantation Technology Conference Proceedings, Marseille, France, June 11-16.

2. Downey, D.F., Arevalo, E.A., Eddy, R.J. (2000). The Significance of Controlling “Off-Axis” (from 1-0-0) Oriented Si Wafers During High Angle Implants. Ion Implantation Technology Conference Proceedings, Alpbach, Austria, September 17-22.

3.Guo, B.N., Variam, N., Jeong, U., Mehta, S., Posselt, M., & Lebedev, A. (2002). Experimental and Simulation Studies of the Channeling Phenomena for High Energy Implantation. Ion Implantation Technology Conference Proceedings, Taos, New Mexico, USA, September 22-27.

4.Canning, Stephen, (7/17/2006). BKM – System related Checks for Process Control, PSB2621A, Varian Semiconductor VSEA Product Support Bulletins, Pg. 6.

BOBBY ISAACS is an Ion Implant Fabrication Engineer for Texas Instruments’ DMOS5 manufacturing site in Dallas, TX ([email protected]). ANYA CORNELL is an Ion Implant and Silicon Processing Engineer for Texas Instruments’ MFAB manufacturing site in Portland, Maine.([email protected]).

DR. MIKE CZERNIAK, ANDREW CHAMBERS and ADRIENNE PIERCE, Edwards, Clevedon, UK.

The move to 450mm wafers will likely result in gas flow increased on process vacuum and abatement equipment.

The semiconductor industry is gearing-up for a transition in silicon wafer diameter from 300mm to 450mm, driven by the requirement to reduce device manufacturing costs. This transition is the latest in a series of wafer size increases, as illustrated in FIGURE 1. The transition to 450mm wafer high volume manufacturing is currently predicted to occur sometime beyond 2020.

With each new generation, the corresponding process gas flows have increased in order to maintain throughput for the larger wafers and the larger process chambers they required. A similar increase in process gas flow rates is anticipated for the 300mm to 450mm transition, but with industry demands to reduce overall utility consumption while simultaneously increasing productivity, there is pressure to reduce the gas flow scaling factor relative to the 2.25 times geometrical scaling factor of the larger wafer surface area. Nevertheless, a significant increase in gas flows is still anticipated.

Impact of increased gas flows When process gases or by-products are corrosive, flammable, condensable, or contain significant quantities of solid material, nitrogen is often added into the pump mechanism itself and/or into the downstream exhaust pipe. So, higher process gas flows will drive a proportional increase in nitrogen purges added to the exhaust, which in turn, will augment the vacuum and abatement capacity required by 450mm processes. This nitrogen serves a number of important purposes:

1) diluting corrosive gases to reduce damage to pump components, 2) diluting flammable gases to avoid flammable mixtures when either an oxidant is also present or in the event of an air leak into the system, 3) diluting condensable gases to avoid condensation of damaging materials onto equipment surfaces, 4) assisting the pumping of light gases, and 5) increasing the gas velocity to ensure that entrained particulate matter keeps moving through the pump mechanism and exhaust pipe. In practice, the total nitrogen purge and dilution flow rate is scaled with the process gas flow to maintain overall system reliability or to meet a specific operational requirement, for example, dilution of a flammable gas to avoid a potential flammable mixture.

For vacuum pumps, higher process gas flows require the deployment of larger capacity pumps, increasing not only the capital cost and but also the total operating cost due to higher nitrogen and pump power consumption. Furthermore, the increased flow rates also affect the capacity requirements of point-of-use (PoU) gas abatement systems. The impact of the increased gas flow on the abatement system is similar to that on the vacuum pumps, namely, higher capital cost for greater capacity, potentially physically larger systems, higher operating costs for more fuel or electricity to heat the gas to a sufficient reaction temperature for destruction, and more water to cool the system and scrub reaction by-products from the exhaust stream.

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FIGURE 1. Historical evolution of Si wafer diameter in the semiconductor industry.

Integrated vacuum and abatement

The most obvious scenario for the 450mm transition would simply scale the capital and operating requirements of vacuum and abatement systems to match the increased gas flows. While this approach would still capture the economic efficiencies accruing from a gas flow scaling factor that is lower than the wafer surface area scaling factor, it misses other significant opportunities to enhance overall efficiency and realize even larger reductions in cost per unit area – the intended goal of the 450mm transition.

Since 450mm wafer processes are still under development, the gas flows that will ultimately be deployed are unknown at this time. However, it is possible to investigate methods to reduce nitrogen dilution or purge flow rates now, based on 300mm processes and 450mm projections. With clear process specification, the optimal pump design can be selected, and the requirement for purging of the pump mechanism itself can be reduced. For instance, the use of chemically-resistant seals would allow exposure to higher concentrations of corrosive gases. Similarly, running the pump at higher operating temperatures could allow the passage of higher concentrations of condensable gases without the build-up of solids. Examples include NH4Cl from low pressure CVD (LPCVD) nitride deposition processes and AlCl3 from metal etch processes.

The practical limitation to reducing nitrogen purge flows is often the pipeline that connects the pump exhaust to the PoU gas abatement system, which can be very long. Because the gas in this pipe is at approximately atmospheric pressure, the risk of corrosion is greater than at the reduced pressure found in the vacuum foreline and the gas is often diluted to avoid damage to the equipment. Likewise, condensable gases are most prone to condense into solids and block the pipe when the pressure is higher, and the typical response to this problem is to increase the nitrogen purge flow rate. A flammable gas may be diluted to prevent fire or explosion if the gas leaks into the fab environment.

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FIGURE 2. Integrated vacuum and abatement.

A viable solution is to make the pump exhaust pipe very short, which minimizes the volume of enclosed gas and reduces the cooling that occurs over extended pipe runs, as illustrated in FIGURE 2. While it is common practice to actively heat long pump exhaust runs, the power used for heating can exceed the power consumed by the pump itself. In addition, bends, valves and joints all need to be properly heated and insulated otherwise they act as sites for solids accumulation and blockages. To minimize the risk of flammable, toxic or hazardous gas escaping into the fab environment, the vacuum pumps and gas abatement can be housed in a common extracted enclosure held at lower pressure than the fab, ensuring that any leaking gas does not escape into the fab. By monitoring the cabinet extraction, the presence of a gas leak can be detected and suitable alarms raised for remedial action, while the leaking gas remains confined within the equipment enclosure and factory personnel are protected from exposure.

The opportunity to optimize exhaust pipe configuration and system operation while minimizing nitrogen purging, equipment size and utility costs, constitutes a major benefit for adopting an “integrated system” approach to vacuum and abatement. An expertly integrated design can resolve potential conflicts between reducing utility costs and ensuring operational safety in the presence of flammable or reactive gases. New approaches to safe equipment operation can be better implemented, and more readily accepted, in the context of an integrated system, in which the various elements are designed to be complementary and mutually supportive. The integrated supervisory monitoring and control system can be designed to ensure safe operation, monitor leak integrity, detect equipment malfunction, and shut-off process gas if a critical situation arises. The integrated system also offers better alignment with sub-system performance requirements under specific process conditions driving optimized BKMs (Best Known Methods). For example, during a deposition versus a clean process, and a purge only mode can be added when appropriate.

Additional benefits of sub-fab equipment integration include:

  • Reduced overall equipment footprint compared to traditional “stand-alone” configurations.
  • Reduced utilities hook-up requirements, since facilities connections can be shared between vacuum and abatement systems, reducing hook-up cost and installation time.
  • Easier implementation of “Green Mode” utility-saving strategies – the process tool only needs to send one set of signals to the integrated system controller to trigger low power or idle mode operation.
  • Overall system ownership and the reduction of unintended consequences.

Integrated vacuum and abatement systems, such as the one shown in figure 3, are installed and operating at more than fifteen 300mm fabs across the full spectrum of process applications. The higher overall costs and productivity requirements for 450mm processing make the arguments for adopting integrated systems even more compelling. The industry has a unique opportunity to incorporate and enhance these cost-saving system considerations in the 450mm fab. Collaborative 450mm initiatives are at the forefront of “changing the game” to reduce the higher overall costs while improving the value of wafer throughput and reducing the manufacturing cost by area of device produced.

Summary

The transition from 300mm to 450mm is underway and it is likely to be accompanied by significant increases in not only process gas flows, but also the consequential nitrogen purges used in process vacuum pumps and downstream exhaust systems. Simply increasing pump and abatement capacity will result in increased capital and operating costs proportional to the increased flow. An alternative strategy is to integrate the vacuum pumps and gas abatement into a combined system with optimized exhaust pipe configuration, process exhaust temperature control, a common extracted housing, single utilities connection points and a single supervisory control system. These integrated systems with better tool communications interfaces have the potential to increase the value of the 450mm transition by further reducing operating costs.

DR. MIKE CZERNIAK, is a product marketing manager, ANDREW CHAMBERS, is technical manager and ADRIENNE PIERCE is business development manager with Edwards, Clevedon, UK.

The next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks.

Pete Singer, Editor-in-Chief

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FIGURE 1. A small pit on the substrate surfaces gets magnified through the multilayer stack.

According to Veeco’s Tim Pratt, Senior Director, Marketing, the tools in place today are not capable of producing mask blanks with the kind of yield necessary to support a ramp in EUV. “Based on the yield today, the mask blank manufacturing capacity can’t produce enough mask blanks to support the ASML scanners that they’re planning to ship,” Pratt said.

The requirement for 2015 is to have zero blank defects larger than 62nm. SEMATECH in 2012 reported work showing eight defects larger than 50nm. “A lot of progress being made but the elusive zero defects has not yet been hit,” Pratt said. Veeco, which is the sole supplier of EUV multilayer deposition tools, has plans to upgrade the existing Odyssey tool and launch a new platform in the 2017/2018 timeframe.

An EUV mask is considerably more complicated than conventional photomasks. The EUV mask begins with a substrate. On the back of the substrate you have some material that’s used for chucking (an electrostatic chuck is used to hold the mask to a stage in the ASML tool and in the Veeco ion beam deposition tool). On top of the substrate is a multilayer sandwich made up of 40-50 moly silicon pairs that creates a mirror. A ruthenium capping layer helps protect the mask. The top layer is an absorber, and that’s what gets patterned.

FIGURE 1 shows a small pit on the substrate. “As the multilayer gets deposited on top of it, you take what in the beginning might have been a small pit and at the top it becomes 1.5X or so larger,” Pratt said.

Where is EUV today? Billions have already been invested to build the EUV infrastructure with particular emphasis on the light source. Chipmakers have invested in ASML, and ASML acquired light-source provider Cymer. There has also been a very large Industry investment in Zeiss to build the AIMS tool, which is a defect detection and repair system at EUV wavelengths.

In July, ASML said NXE:3300 scanner imaging and overlay performance reached levels where they are engaging with customers on a strategy for the 10nm logic node insertion (23nm half pitch). Good imaging performance was shown down to 13nm half pitch, and overlay between the NXE:3300 and NXT systems, had been demonstrated at less than 3.5nm. Good performance, stability and reliability of the pre-pulse source concept was demonstrated with a rate of around 40 wafers per hour, and ASML expressed confidence in reaching the goal of 70 wafers per hour productivity in 2014.

What could derail the EUV ramp, according to Pratt, is a supply of defect-free mask blanks. “EUV is, despite many years and many dollars of investment, not yet in production. The two main gaps are the EUV light sources and the defects on the mask. As they start to make progress, people start to look more seriously at the list of things to worry about for EUV going to production. Number one on that list is the mask defects,” Pratt said. “The most dangerous (un-repairable) defects come from the ML (multilayer) coating process during mask blank manufacturing. You can’t clean them and you can’t repair them and if you have more than some very small amount, there’s really nothing you can do about it. You just have to throw that mask blank away and try again,”Pratt said.

Veeco is addressing the defect challenge in two ways. The short-term solution is an Odyssey upgrade. The longterm solution is a new platform. “The Odyssey upgrade improves the yield of the tool. But then longer term we think the next gen is needed, especially as you get out to years 4 and 5 where high volume manufacturing starts to occur,” Pratt said.

KEIBOCK LEE, Park Systems, Santa Clara, CA.

3D atomic force microscopes can measure critical dimensions, line edge roughness and sidewall roughness in a way that is highly accurate, non-destructive and cost-effective.

One of the most challenging features in the semiconductor industry is the continuous research and the subsequent fabrication of integrated circuits with enduringly smaller critical dimensions (CDs). As shown in FIGURE 1, CDs must be measured at the top, middle and bottom of features, as well as various parameters such as line edge roughness (LER), the line width roughness (LWR) and the sidewall roughness (SWR).

The characterization of such factors that determine the shape and the roughness of the device patterns for device manufacturers is of utmost importance due to the fact that they directly affect the device performance. Optical measurement techniques, which are limited in terms of resolution. Therefore, the existing prevalent method for measuring these factors prior was primarily the scanning electron microscopy (SEM) with its image analysis software. Despite the fact that this technique offers substantial advantages such as automation and compatibility with standard critical dimension SEM tools, it cannot provide the user with high resolution LER data due to the fact that SEM resolution is reaching its limits, therefore 3D AFM offers a highly desirable solution. Leading manufacturers have implemented AFM that can measure resist profile, LER and SWR in a way that is highly accurate, non-destructive and cost-effective. The precise and full characterization of such features is extremely essential during the pattern transfer process as it offers the possibility of imaging all surfaces of the pattern.

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FIGURE 1. LER, LWR and SWR are the limiting factors of resolution in optical lithography.

What is non–contact 3D AFM?
The basic principle of non-contact 3D-AFM is that a cantilevered beam rapidly oscillates just above the surface of the imaging sample. This offers several advantages, as compared to the traditional contact and intermittent modes. One of the advantages is that there is no physical contact between the tip and the surface of the sample. Moreover, as depicted in FIGURE 2, the Z-scanner, which moves the tip, is decoupled from the XY scanner, which solely moves the sample, thus, offering flat scanning and an additional benefit of improved Z-scan bandwidth. Furthermore, by tilting the Z-scanner, the sidewall of the nanostructures can be accessed and roughness measurements performed along the sidewall of photoresist lines. At the same time, measurements of the critical dimensions of top, middle, and bottom lines can be made.

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FIGURE 2. The independent tilted Z-scanner enables measurements of the sidewalls of features.
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FIGURE 3. Combination of the three acquired images for 3D AFM pattern reconstruction.

Data acquisition is performed by a conical tip in predefined tilted angles, typically 0º, a, and -aº. Consequently, and by combining these three scans (a method called image stitching), the 3D pattern can be constructed, as shown in FIGURE 3. This provides an excellent and extremely accurate method that takes advantage of the interference pattern of the standing waves in order to measure features such as the total height, the top, middle, and bottom width. 3D AFM is capable of advanced three-dimensional imaging of both isolated, and dense line profiles. It is less costly than the alternative techniques (CD-SEM and focused ion beam (FIB)) for imaging and measuring parameters of line profiles since the preparation of the sample is by far simpler.

Noise levels in 3D-AFM
A critical requirement when dealing with metrology tools is associated with constraining the level of noise in the manufacturing environment. A study of noise levels on a 300 mm wafer (FIGURE 4) shows the overall 3D AFM system noise at levels are lower than 0.05 nm (0.5 angstrom).

Roughness measurements
Roughness can be transferred into the final etched profile, thus, roughness measurements can describe and determine the quality of the patterns. The tilted Z scanner in combination with the low noise levels that are prevalent during the AFM process can provide accurate results in terms of sidewall roughness measurements. FIGURE 5 depicts the 3D AFM imaging of a photoresist semi-dense line pattern and the respective grainy structure of its sidewall. The precision with which the SWR was measured is validated by the high repeatability (0.08nm 1 sigma for 5 sites wafer mean) for the sidewall roughness of about 6.0 nm.

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FIGURE 4. 3D AFM noise levels on a 300 mm wafer. The system noise level is less than 0.05 nm at every position and typically 0.02~0.03 nm RMS.
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FIGURE 5. 3D AFM image of a photoresist semi-dense line pattern imaged with Z-scanner tilt. The bottom figure clearly depicts the grainy structure of the sidewall.

It needs to be noted that roughness depends, amongst others, on the aerial image contrast (AIC) or in other words the physics of exposure. AIC is determined as the quotient between the subtraction and the addition of the maximum and minimum image intensities.

Several consequent series of images with variable exposure reveal that LER significantly increases when the AIC is decreased, a fact that underlines that AIC is a controlling factor for LER. Moreover, and as depicted in FIGURE 6, reduced levels of AIC produced line profile images of the resist that were more blunted, and also smaller sidewall angles (SWA).

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FIGURE 6. Park 3D AFM line profiles at different AIC levels reveal the proportionate relationship between SWA and AIC.
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FIGURE 7. A 3D AFM image of a 300 nm photoresist line pattern yields full information regarding the morphology of the sidewall (top) Side-wall Roughness is different at different AIC levels, a fact that indicates the connection between LER and SWR (bottom).

FIGURE 7 illustrates the capability of Park 3D AFM to image all surfaces of the pattern, in contrast to the conventional AFM or the SEM, which cannot fully characterize the surface data, and obtain information such as base, top and both sidewall roughness from sidewall characterization. A 300 nm photoresist line pattern was imaged and the respective line profiles were obtained that clearly showed a substantial difference in terms of SWR between 97% and 40% AIC. More specifically, the lower the value of AIC, the more increased was the measured roughness. This intense decrease of roughness is underlying the fact that LER and the measured sidewall roughness are clearly correlated.

Finally, it needs to be emphasized the role of non-contact 3D AFM in terms of preserving the tip sharpness of the cantilever. In an independent study, researchers performed 150 consecutive measurements using the same tip and the tip wearing proved to be minimal. This is a prominent feature of AFM that prevents the continuous costly replacement of the tip but also ensures that the sample will be viable and not damaged by the AFM cantilever. The preservation of the tip sharpness allows for continual measurements of high resolution roughness data.

Conclusions
The potentialities of the innovative, non-destructive imaging technique of 3D AFM has several advantages compared to conventional SEM systems. An independent and tilted Z-scanner overcomes the disadvantages of alternative metrology tools and measure parameters such as detailed sidewall morphology and roughness, and sidewall angle characterization that render the optimization and evaluation process easier and far more detailed. •

KEIBOCK LEE is president and general manager of Park Systems, Santa Clara, CA.

JULIAN GATES and TIM JOHNSON, AG Semiconductor Services; and
DARRELL McDANIEL, NSTAR Global Services, M+W Group.


The choice between buying new systems from OEMs or fully capable refurbished gear from qualified used equipment vendors is examined.

A significant portion of semiconductor production continues to take place in facilities equipped with 200mm or smaller equipment, which run processes for analog, mixed-signal, power ICs, and other mature device types. Recent data from Semico shown in FIGURES 1 and 2 reveal that 39% of the silicon consumed is devoted to 200mm, with another 9% going for wafers of <200mm, while technology nodes of 130nm and above account for approximately 50% of the silicon used.

Managers of these legacy fabs must balance tight process and time-to-market requirements with limited capital and operational budgets to stay competitive with low-cost producers. As the major original equipment manufacturers devote more of their budgets to 300mm tooling (or even 450mm) and invest less into their 200mm efforts, older semiconductor factories need high-quality sources of used systems and components as well as the tribal process knowledge that goes with them. The emergence and growth of the market for refurbished 300mm production tools has added even more complexity and challenges.

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FIGURE 1. 39% of the silicon consumed is devoted to 200mm, with another 9% going for wafers of <200mm.
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FIGURE 2. Technology nodes of 130nm and above account for approximately 50% of the silicon used.

After growth fueled by thousands of tools coming on the secondary market in the mid- to late 2000s followed by an extended recession-fueled downturn, the secondary equipment market is seeing increased order activity and is expected to grow into a $3 billion-plus sector this year (see FIGURE 3). During this cycle, the companies specializing in procuring, modifying, reconfiguring, refurbishing, installing, qualifying and offering ongoing warranty and service support for those thousands of pieces of process equipment have become key partners with the likes of Texas Instruments, GLOBALFOUNDRIES, ON Semiconductor, STMicroelectronics, Fairchild, Maxim, Tower, and other IDM, foundry and OEM firms.

High quality, low cost
One key question facing legacy fab operators is how to upgrade their processes and factories or expand their capacity in a timely and cost-effective manner. When there is a choice between buying new systems from OEMs or fully capable refurbished gear from qualified used equipment vendors, whether the mission is to convert from a 150mm to a 200mm line or push to a more advanced technology node, the difference in price can range from hundreds of thousands of dollars to a few million dollars per tool for big-ticket systems such as lithography steppers and scanners. The price tag for secondary equipment ranges from as little as 20-30% of what a new tool would cost, depending on the age, condition, availability, and provenance of the system, to a tighter 70-80% of the new-tool price. In some cases, fab management may have to choose between different pieces of used gear, as the OEM either does not manufacture those particular 200mm systems or is no longer in business.

Considering the risk-averse personalities of most fab engineers, they need to be assured that any tool, new or used, that they bring onto their factory floor will produce the level of product needed, at profitably high yields and a compelling cost of ownership and productivity metrics. They also want to see lead times for equipment delivery, installation and qualification narrowed as much as possible. This means secondary equipment providers must now offer a detailed and exhaustive evaluation of any tool that comes into inventory, working up a detailed configuration, baseline and dataset for prospective buyers. To meet demand, suppliers often maintain large inventories in cleanroom-equipped warehouses located in strategic global locations that can provide and qualify fully process capable equipment in a matter of weeks not months (FIGURE 4). The old model of aggressively brokered, “what you see is what you get” used equipment of unknown condition sitting in unopened containers has been replaced by a value-added, collaborative approach that brings new tool-like quality and reliability to the secondary space as well as a dedicated support team of experts with deep knowledge about older equipment and processes.

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FIGURE 3. The secondary equipment market is expected to grow into a $3 billion-plus sector this year.
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FIGURE 4. Used semiconductor equipment in AG Semiconductor Services’ Nijmegen, The Netherlands refurbishing facility.

Exceeding specifications
Despite the increased quality of secondary equipment and related services, there are still instances when process engineers might be taken out of their comfort zone and must be convinced that the used solution will meet or exceed requirements. A recent example involved the acquisition of surplus toolsets from a leading-edge IC manufacturer by a secondary equipment company, which then sold the systems to a 200mm foundry operation seeking to expand its capacity. The original specifications of the tools indicated that they would be functional up to the 180nm process node, but the previous owners of the equipment had successfully extended the equipment capability down to at least the 130nm node. After their initial reticence, the foundry engineers were convinced of the refurbished tools’ enhanced capability through a combination of compelling performance data such as etch and via depth results as well as domain expertise and consultation provided by the secondary equipment provider. The resulting upgrade saved the customer millions of dollars in avoided new capital equipment expenditures.

Spare parts conundrum
A study on 200mm equipment obsolescence conducted by Semico for ISMI focused on issues surrounding legacy fabs’ tool issues. As TABLE 1 shows, chief concerns of the chipmakers, OEMs, and secondary tool companies include the inability to find replacement parts at a reasonable price, the struggle to get equipment documentation that includes part specifications and equipment schematics, and the difficulty in notifying customers when a part is being discontinued because of the large number of parts to keep track of. In addition to the general issue of parts obsolescence, other underlying causes can be tracked back to the OEMs use of subcontractors and subsequent loss of control over their spares inventory, as well as the general trend of consolidation among the process equipment manufacturer ranks and premature exit from active 200mm development and production. One industry group, the Fab Owners Association, has come up with a method to alleviate spare parts shortages, by maintaining a network of fab managers who share parts when they can with other members of the group who can’t wait for new parts to be produced and delivered.

table1
Table 1: Legacy fab equipment issues (Source: Semico Research, 200mm Equipment Obsolescence Study).

The used semiconductor equipment sector has evolved significantly in recent years. Texas Instruments’ purchase of Qimonda’s 300mm fab equipment for dimes on the dollar in 2009 and subsequent conversion and qualification of tools originally designed for memory chip production for use on its own analog RFAB lines forced competitors and others in the industry to look more seriously at making the 200- to 300mm wafer-size transition in their own operations. Duke characterized the 200mm secondary market as “the new 150mm,” as fewer new systems are made, and engineering and sourcing efforts become more difficult to keep legacy parts available.

Mix and match, ‘more than Moore’ and more
Despite the challenges of equipment and parts availability and obsolescence, some industry experts are bullish on the potential for using refurbished equipment at more demanding technology nodes, seeing used tools as capable of playing a key role in converting a 130nm LSI line into one that processes 60nm and even 45nm devices. Kato provided a step-by-step explanation of his “mix-and-match” philosophy, where he stated that 180 used tools, or 67% of a total toolset, could be deployed to produce 60nm requiring 29 masks. A dozen tools would require remanufacturing upgrades and 82 tools (30%) would need the latest technology only available on new tools. He noted that certain metal layers and N- and P-well implantation could be done with used tools, while other layers requiring fine patterns would need new equipment, and several steps could be carried out with a blend of new, used, and remanufactured tools. Many of the processing steps in his 60nm example can be accomplished with readily available secondary CMP, CVD, etch, and wet processing systems. 3-D interconnect and packaging lines also provide a market for repurposed wafer-processing gear.

Bignell discussed how STMicro has evolved and repurposed older fabs for “more than Moore” chip designs using “derivative technology.” In cases where process steps were similar, an existing toolset could be deployed, modified or upgraded, such as the example of converting an older wet bench to a new process chemical mix. Equipment from other sites has been transferred to the repurposed fabs, such as the case where a decommissioned front-side PVD system was used for backside metallization. In addition to adapting and optimizing fab layouts and facilities, the purchase of 200- and 300mm second-hand tools whenever possible as well as the acquisition of new equipment featuring new capabilities continue to be central tenets of the manufacturer’s life-cycle extension strategy.

An area of future growth in the secondary equipment market will come from customers, many in regions of the world with little or no domestic semiconductor manufacturing base, that want to establish at least an R&D, pilot, or other start-up facility and may seek a complete fab. An integrated “super turnkey,” soup-to-nuts solution for this kind of project features an experienced secondary equipment company that can leverage a large 200mm tool inventory, an engineering, procurement, and construction partner that that can design and build a new facility or retrofit an existing one, and highly trained equipment and process engineering teams that provide infrastructure and other support functions.

Conclusion
As more of the secondary equipment market segues from 200mm to 300mm demand and applications, the lessons learned over the past few years will help ease the transition, lowering engineers’ anxiety levels and providing a cost-effective, process-centric strategy for extending fab and product lifetimes.

Acknowledgment
The authors would like to thanks Joanne Itow of Semico Research for her valuable insights to this article. •

Bibliography
Bignell G, “Extending the Life of 200mm Fabs and the Re-Use of Second Hand Tools,” presented at Secondary Equipment and Technology session, Semicon Europa 2012.
Chappell J, “Trickle Down Equipment Economics,” Semiconductor Manufacturing & Design, May 2013.
Duke D, “Used Equipment Market,” presented at Productivity Innovation: Reducing Cost and Improving Performance at 200mm/300mm Wafer Fabs forum, TechXpot, Semicon West 2013.
Gates J, “2013: Outlook for Secondary Equipment,” Solid State Technology, January 2013.
Itow J, Semico Research, private interview, August 2013.
Kato T, “New Dynamics Changing the Secondary Equipment Market,” presented at Used Equipment business seminar, Semicon Japan 2009.
Ploss W, “300mm for Analog Technologies,” presented at Secondary Equipment and Technology session, Semicon Europa 2012.
Semico Research, “200mm Equipment Obsolescence” study for ISMI.

CHRISTIAN GREGOR DIESELDORFF, SEMI Industry Research & Statistics Group, San Jose, CA.

Some unexpected underdogs spur spending spree

Next year could be a golden year for the industry. While GDP in 2013 is generally about the same as in 2012, it is expected to rise in 2014, to 3.8 percent from 3.1 percent. Semiconductor revenue has improved in 2013 compared to 2012 and early forecasts for 2014 project revenue growth averaging about 8 percent. Semiconductor companies have adjusted their capital expenditure accordingly, and the SEMI World Fab Forecast data now indicates fab equipment spending for 2014 will reach historic highs.

The SEMI World Fab Forecast report tracks over 200 projects, with details revealing that fab equipment spending declines by 1 percent in 2013, but will increase 25 percent in 2014, including new, used and in-house equipment.

Overall fab spending in the first half of 2013 was slower, especially for fab equipment spending. Excluding a large purchase by GLOBALFOUNDRIES for used 300mm equipment from Promos (NT$20 to NT$30 billion) the decline in 2013 would have been -3.4 percent instead of -1 percent. Fab equipment spending is expected to be stronger in the second half of 2013, with a 30 to 40 percent increase over the first half, though the year will end with an overall equipment spending decrease of -1 percent.

SEMI’s data show a different outlook for fab construction projects, forecasting a 25 percent increase in 2013 and then a drop of 16 percent in 2014. Fabs being built this year will begin equipping next year which affects fab equipment spending.

Semiconductor device revenues did not grow in 2012 (dropped by about 2.7 percent), thus many companies slowed down capacity additions last year. With some improvement in the market, the SEMI data indicate that more capacity will be added in the 2nd half of 2013 and even more in 2014, for overall capacity growth of about 4 percent (FIGURE 1).

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FIGURE 1. More capacity will be added in the 2nd half of 2013 and even more in 2014.


Underdog DRAM surges to the front of the pack
Fab equipment spending for dedicated foundries remains strong in 2013 ($12B) and in 2014 ($13B) — a growth rate of 5 percent in 2014. Foundry equipment spending growth rates have been more controlled and not changing as dramatically as in other industry segments. In the years prior to the economic downturn, fab equipment spending for DRAM was the highest spending industry segment. Since 2011, however, the dedicated foundry sector replaced DRAM as the leading industry sector (FIGURE 2).

Fab equipment spending growth for DRAM turned negative in 2011 and 2012, as companies consolidated or diverted memory capacity into other products such as System LSI. DRAM equipment spending dropped by double digits in 2011 and 2012 (-35 percent and -25 percent respectively). SEMI’s data show that this will change dramatically, with DRAM fab equipment spending surging by 17 percent in 2013 and at least 30 percent in 2014. Driven by increased average selling prices (ASPs), up by about 40 percent in 2013, companies will begin to see profit on DRAM and slowly invest in new capacity (FIGURE 3).

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FIGURE 2. Since 2011, however, the dedicated foundry sector replaced DRAM as the leading industry sector.
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FIGURE 3. Companies will begin to see profit on DRAM and slowly invest in new capacity.

An increase of about 2 to 3 percent for installed capacity for DRAM in 2014 is small but remarkable, given that the industry has not added any new DRAM capacity for years, and actually decreased capacity between 2011 and 2013.

The sector with largest growth rate for fab equipment spending in 2014 is expected to be Flash with 40 percent to 45 percent (YoY). Over the last few years, with fears of oversupply and price collapse, capacity additions for the Flash sector also stagnated. Some companies even stopped or reduced adding new capacity (for example, Sandisk in 2012 and in 2013), leading to a tight supply, but a rebound in capacity is expected in the 2nd half of 2013 and through 2014. SEMI’s reports show detailed predictions for robust spending in DRAM and Flash by several large companies.

For example, Micron, which officially acquired Elpida and Rexchip in July 2013, will dedicate almost half of its total 2014 capital expenditure to DRAM. After converting several fabs from memory to System LSI, rival Samsung is also expected to change tactics, spending less on System LSI and more on Memory in 2013 and 2014. Samsung’s Flash facility in China is expected to ramp to phase 1 by end of 2014. (The World Fab Forecast report reveals more detail on this and other surprising changes for S1 facilities and Line 16.) Overall fab equipment spending for Flash alone is expected to hit a record of almost $8B in 2014. The largest contributors are the Samsung fab in China and Line 16, Hynix M12 and M11, Flash Alliance fabs and Micron fabs.

MPU Joins DRAM as the next underdog
After Flash and DRAM, MPU is expected to show the next largest growth in 2014, with fab equipment spending growing by over 40 percent (YoY). While MPU languished in 2011 and 2012, and even dipped into negative growth in 2013, with low utilization in some fabs, Intel is now preparing for 14nm, kicking off an MPU surge for 2014. The World Fab Forecast report gives insight into Intel’s preparations for 14nm.

Semiconductor companies appear to have mastered the art of fast adaptation to chip prices and business developments. With improving prices for DRAM, similar changes steer various sectors of the industry into unprecedented growth. With GDP predictions around 3 to 4 percent, revenue expectations in upper single digits, and historic numbers for equipment spending, next year could be a golden year for many semiconductor companies and equipment manufacturers.

SEMI World Fab Forecast report
Since the last fab database publication at the end May 2013 SEMI’s worldwide dedicated analysis team has made 242 updates to 205 facilities (including Opto/LED fabs) in the database. The latest edition of the World Fab Forecast lists 1,147 facilities (including 247 Opto/LED facilities), with 66 facilities with various probabilities starting production this year and in the near future. We added 14 new facilities and closed 8 facilities.

The SEMI Worldwide Semiconductor Equipment Market Subscription (WWSEMS) data tracks only new equipment for fabs and test and assembly and packaging houses. The SEMI World Fab Forecast and its related Fab Database reports track any equipment needed to ramp fabs, upgrade technology nodes, and expand or change wafer size, including new equipment, used equipment, or in-house equipment. •

CHRISTIAN GREGOR DIESELDORFF is the Senior Analyst, Director, Industry Research & Analysis Industry Research and Statistics Department at SEMI, San Jose, CA.