Category Archives: 3D Integration

(November 10, 2010) — Package-on-package (PoP), implemented with flip chip package assembly, is meeting a lot of the requirements for next-generation mobile devices. Challenges remain, namely using fine pitch underfill, brittleness of ultra low-k (ULK) dielectrics, and shorting between adjacent bumps. Craig Mitchell, Tessera, examines the lucrative 3D packaging step and how to face the aforementioned challenges.

For years, the mobile phone market has been driving the development of the advanced semiconductor packaging industry. This is primarily due to the desire of original equipment manufacturers (OEMs) to accommodate the end user’s insatiable demand for functionality, performance and miniaturized form factors. The mobile phone market’s influence was first seen through the demand and subsequent adoption of chip scale packaging (CSP), followed closely by multi-chip packaging and now package-on-package (PoP) structures for manufacturing. This trend is most notable in the smart phone segment, where applications, baseband and multimedia processors are increasingly adopting flip chip packaging to satisfy size, performance, and, in some cases, cost requirements. The smart phone market is the fastest-growing segment of the 1.3-billion-unit mobile phone market, anticipated to grow at a CAGR of 25% through 2014, according to Gartner. It also tends to be the most profitable segment of the market and is gaining increased attention from wireless carriers, handset manufacturers, semiconductor manufacturers and subcontract assemblers alike.

The growing functionality and complexity of these handheld devices is driving the need for more advanced packaging interconnect technologies that are capable of efficiently and cost-effectively delivering the performance design to the chip and the end-product. Flip chip has been identified as a solution and, when combined with a PoP approach, is meeting many of the demands facing the semiconductor market. With that said, the global technical community still faces challenges in implementing flip chip, including fine pitch underfill, brittleness of ultra low-k (ULK) dielectrics and shorting between adjacent bumps. Here, we’ll explore some of these challenges that are currently being considered.

The first challenge relates to underfill, a widely used process in which a liquid material is dispensed to fill the gaps between the flip-chipped die and the associated package substrate. Its primary purpose is to reduce stress in the solder bumps interconnecting the die and the package substrate as a result of differences in coefficients of thermal expansion (CTE) and exposure to a range of temperatures through the lifetime of the package assembly. As the pitch of the flip chip bumps continues to decrease, it simply becomes more difficult to use conventional underfill processes and materials. Reduced bump pitch results in smaller gaps between adjacent flip chip bumps and lower stand-off height between the chip and the package substrate. Both result in increased resistance to the flow of the underfill material itself. This, combined with the trend toward increased chip size, makes it increasingly difficult to ensure void-free, high-throughput underfill. Consequently, the industry is pursuing advanced encapsulation techniques such as capillary underfill, no-flow underfill, vacuum underfill and mold underfill, in addition to continually refining the rheology and various other mechanical and thermal properties of the underfill materials themselves. Although much progress has been made, further development of equipment, materials, and the associated processes is required.

Another challenge relates to the use of ultra low-k dielectrics. As the wafer process node for manufacturing semiconductor devices migrates from micron to submicron to deep submicron levels, the need for thin, low-k insulative layers to separate and isolate adjacent on-chip conductors grows. At the 32nm process node and below, ULK dielectrics provide the required isolation while minimizing the parasitic capacitance to enable the desired switching speed within the semiconductor chip. To achieve the required dielectric constant of these insulating layers, voids are often introduced into the material, increasing its porosity. As air has a dielectric constant of one, introducing air into the dielectric is an effective means to decrease the dielectric constant. However, it can also substantially increase the material’s brittleness, so it becomes critical to minimize stress on this fragile dielectric layer. Several solutions are being considered, including increasing top metal layers’ thickness, increasing passivation layer thickness, and, in most if not all cases, very carefully selecting the underfill material to balance the mechanical properties, such as CTE and Young’s modulus, with those of the ULK dielectric. Also read, "Low-k family introduced by SBA Materials" by Dr. Phil Garrou

A third challenge relates directly back to the flip chip interconnect itself and the requirement to have both fine pitch and sufficient stand-off height (typically, above 60µm) between the chip and the package substrate for underfill. For the past 40 years, balls of solder, either tin/lead or lead-free, have been used as the primary flip chip interconnect. Reductions in bump pitch are pushing the limits of conventional assembly processes, resulting in lower substrate and package assembly yields, reduced manufacturing throughput and higher packaging costs. A common failure relates to electric shorting between adjacent solder bumps. This is due to the spherical nature of each solder mass, which results in roughly equal height and width of the solder mass. One solution is to take a more columnar approach, in which the height-to-width ratio is greater than one.

One approach that is gaining traction uses a copper column or pillar, either directly on the chip itself or on the package substrate. The copper pillar approach provides scalability to very fine pitch: 100µm-pitch area array. The columnar shape allows for taller stand-off height as well as greater gaps between adjacent contacts, eliminating shorting and reducing flow resistance to underfill, allowing for void-free underfill. Using a copper pillar on the package substrate in particular allows for solder, a lower modulus material than copper, to remain at the interface to the bond pad, helping address the ULK dielectric brittleness described earlier. Also watch: "Leveraging 3D packaging technologies: Tessera shares its latest work"

Conclusion

In summary, the demand for electronic products with higher functionality, higher performance, and smaller form factor is unlikely to abate anytime soon. The mobile phone market will continue to lead the charge, pushing the limits of advanced packaging technologies for years to come. With the number of connections to the chip growing, and the allowable package footprint shrinking, flip chip technology is increasingly employed for various processors in mobile handsets. Although conventional flip chip interconnect has proven sufficient for the current generation of devices, new approaches, processes, materials, and structures will need to be developed to address the challenges of the future.

Craig Mitchell is senior vice president of the Interconnect, Components and Materials (ICM) division at Tessera. Mitchell is named as inventor on 32 patents. He received a bachelor’s degree in electrical engineering from Manhattan College, New York City, USA.

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(November 8, 2010) — Advanced Packaging asked our readers where — at the foundry, in a dedicated semiconductor assembly and test services (SATS) house, or on the SMT line — package-on-package (POP) assembly should take place.

The majority vote goes to the packaging house (about 53% of votes), with respondents stating that the testing capability and experience gives SATS providers the edge. SATS companies offer full turnkey solutions providing not only packaging solutions, but also test services on individual units and on stacked packages, said one reader. Another noted that the packaging house provides the lowest-cost solution without impacting SMT assembly time or technology. Chip fab and SMT line both garnered approximately equal votes.

Still another respondant states, "If everything comes from a single chip fab that is equipped for PoP assembly, then the fab is suitable. Commonly, however, PoP is used to mix standard and custom silicon, or silicon from different product lines. In this case, either the package-assembly house or the SMT line may be appropriate, depending on the technologies. The SMT line has advantages if the resolutions and solder technologies are compatible with the line, which is not always the case; sometimes you also want POP to be pre-sealed. This will leave space for a separate packaging-assembly line — though this does not necessarily imply a dedicated packaging-assembly house."

You can still take the survey and let us know what you think, here: http://www.surveymonkey.com/s/packageonpackage

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(October 28, 2010) — Andrew Smith, Ventmark Technology Solutions, presents a 3D die stacking technology to address package miniaturization. Using bare die and vertical interconnect structures, this stacking technology permits the design of ultra-thin, near-chip-scale packaging (CSP) solutions without TSVs. Designers lacking custom integrated circuits (ICs) should look to new chip stacking technology to meet size and performance needs of integrating a range of devices into a small space.

Packaging technology’s evolution — from single-chip surface mount technology (SMT) packages to chip-on-board (COB) multi-chip modules and, most recently, package-on-package (POP) solutions — has greatly increased electronics density. Increasing demands for reduced size and increased functionality, however, often require higher levels of integration than current technologies support.

Figure 1. a) Wire bond fan out from a multi-level stack; b) staggered die stack with spacers and wire bond; c) die stack with vertical interconnects and top side passive devices.

With traditional stacked die structures, diminishing returns in real estate size are experienced as ever greater areas are consumed to accommodate the wire bond fan out from increased die count (Fig. 1a). Offset die and spacers (Fig. 1b) can also pose cost and complexity burdens.

The large upfront costs of developing a POP device make this technology most suitable for volume production applications, and leave other system designers with few options for downsizing.

3D integration with through-silicon via (TSV) technology offers the highest level of integration, but TSV is several years away from full commercial adoption. Currently, only CMOS image sensors are in volume TSV production, and integration of heterogeneous memory and microprocessors chips may not be available until 2014 [1]. Issues of cost reduction, thermal management, design and design for test must be overcome for complete TSV acceptance [2].

Bare die stacking using interposers and vertical interconnect structures (Fig. 1c) provides tight integration without TSV technology, or the upfront costs of a POP. Using traditional materials and processes in a non-traditional way, this approach leverages advances in wafer thinning, die bumping and flip-chip processes, in conjunction with high-density thick film ceramic to achieve a miniaturized system-in-package (SiP) solution at low cost.

Bare die stacking

As a flexible packaging technology, bare die stacking allows for the simple co-packaging of both identical and off-the-shelf heterogeneous die, as well as the incorporation of discrete and integrated passive devices. Applications include co-packing of microprocessors and memory (reduced size, improved performance), and custom memory stacks (greater memory/mm²). This die stacking concept also provides a highly scalable architecture, in X/Y and Z dimensions. As with other SiP approaches, functional design changes can be made at the SiP level without motherboard or other system-level redesigns, maintaining flexibility through the product life cycle. Creating a functional building block in a SiP device provides for device reuse across product lines, reducing front-end design effort in the product development cycle.

 

Figure 2. a) Vertical interconnect structure; b) Ayre hybrid with vertical interconnects and top side passive devices.

Vertical interconnect (VI) structures are a key element in the architecture of 3D die stacks, providing mechanical support within the stack and electrical connectivity between layers within the stack (Fig. 2). Using VI structures and eliminating wire bonds enables highly compact SiP devices in a variety of geometries created at low cost. These micro-miniature VI structures are interconnects fabricated from ceramic, and are fully customizable to the pin count and geometry required.

Because of increased power consumption/mm3, high thermal conductivity aluminum nitride materials provide additional benefits for the increased heat dissipation needed in SiP devices. VI structures can also be utilized to improve heat dissipation through the device with the addition of thermal vias, and offer an excellent temperature coefficient of expansion (TCE) match for improved reliability over a wide temperature range.

Vertical die stack case study

Vertical die stacking has application across a broad spectrum of system requirements, particularly where size and weight are at a premium, offering system designers a straightforward method to co-package critical elements of a design in a custom SiP to meet specific needs.

With materials inherently suited to high-temperature environments, vertical die stacking technology also provides a robust solution where size and ruggedness are critical, such as aero-engine instruments and down-well monitoring and logging. Typical applications include implantable medical devices, headsets, hand-held radios, wireless sensors, energy harvesting devices, body-worn devices, specialty memory product, harsh environment instruments, and hearing aids.

One such application is the Ayre Hybrid from On Semiconductor (Fig. 2). This micro hearing instrument packages a complete wireless audio system with DSP, near-field magnetic induction (NFMI) transceiver chip, memory and associated passive components into a device form factor of 1.85 × 36.8 × 6.48mm.

Packaging options

Vertical die stacks can be provided in a variety of formats to suit user needs. Finished parts can be epoxy-encapsulated, JEDEC-compatible SMT devices suiting standard pick-and-place assembly, or “raw” die stacks to be direct mounted into a hybrid package or COB assembly.

Multi-level die stacks are assembled in panel arrays before dicing into individual stacks. Building multi-level stacks in parallel minimizes lead times and provides opportunity for in-process testing at the sub-assembly level, improving first pass yield.

Conclusion

Vertical die stacking is a 3D technology available today, offering high integration without TSVs. System designers can benefit from the technology’s flexibility, size and weight, and integration. Vertical die stacking provides a simple means to co-package off-the-shelf die and passives devices in a mature production environment.

Acknowledgment
Ayre is a trademark of On Semiconductor.

References
1. Jan Vardaman, “3D TSV Markets: Infrastructure Requirements for Growth,” p. 13 RTI 3D Integration Conference Dec. 2009
2. Phil Garrou, Ph.D., “The 4 Horsemen of 3D IC, Perspectives from the Leading Edge,” Oct. 16, 2009

Andrew Smith studied mechanical engineering at Abertay U., Dundee, Scotland and is an independent contractor working in microelectronics packaging. He is currently the principal at Ventmark Technology Solutions, 211 Giant Oak Avenue, Thousand Oaks, CA 91320 USA; ph.: 805-795-3968; [email protected].

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(October 27, 2010) — The barriers and potential for voltage and density scaling of different memory devices beyond the 22nm is one of hot topics for current memory R&D. While speculation abounds about what will be the next generation of memories and their applications, CNRS, a French government-funded research organization, has 4 new concepts of memories in 2010. The organization is actively recruiting collaborators on RE-RAM, A-RAM, MS-DRAM, and MELRAM memory technologies.

RE-RAM researchers include Marie-Paule Besland and Laurent Cario from IMN (Institut des Matériaux Jean Rouxel CNRS). RE-RAM is a based on a new family of compound. Non-volatile reversible electric-pulse-induced resistive switching were indeed recently uncovered on AM4X8 (A = Ga, Ge ; M = V, Nb, Mo, Ta ; X = S, Se) single crystals at the IMN (Institut des Matériaux Jean Rouxel CNRS). In these chalcogenide compounds, 500ns voltage pulses (<10kV/cm) applied at Room temperature on a simple MIM device (Metal/AM4X8/Metal), yielding a non-volatile resistive switching between a high and a low resistance state. This effect was also demonstrated on GaV4S8 polycrystalline thin films that exhibit a reversible resistive switching at room temperature with writing/erasing times lower than 10µs and ΔR/R values higher than 25%. The resistive switching observed in the AM4X8 system corresponds neither to a phase change nor to any of the phenomena (thermal, electronic injection or ionic diffusion) proposed so far to explain the resistive switching effect in materials envisioned for RE-RAM applications. This memory based on Mott transition insulators offers Write Time (Twr) to 10µs at 1V, Access Time (Tacc) to <50ns at 0.4V and retention time > 1 year. Current density in write operation is better than the best RRAM solution (<3.103 A.cm-2).

A-RAM is a new type of capacitor-less 1T-DRAM. This memory introduces a totally novel 1T-DRAM device based on the coupling of majority and minority carriers in highly-scaled Fully Depleted SOI transistors (FD-SOI), but also compatible with bulk substrates. A-RAM is compatible with single-gate SOI, double-gate, FinFETs and multiple-gate FETs (MuFETs) and is believed a promising candidate for scaled memory applications. The team, A-RAM researchers Francisco Gamiz, Noel Rodriguez and Sorin Cristoloveanu, have developed an absolute original concept of architecture/design/operation which enables the physical separation of majority and minority carriers. Easy to control, State ‘1’ is defined by the presence of majority carriers which leads, via electrostatic coupling, to the formation of a minority carrier channel. State ’0’ corresponds to the absence of such a channel. Deep scaling compatible, the strengths of the A-RAM memory are: single-gate operation (no mandatory need for back gate biasing), high read margin (over a factor of 100) and low power consumption. In addition, A-RAM can be combined with double/multiple-gate FETs, introducing a new paradigm in DRAM technology: multiple bit memory in a single transistor. The A-RAM architecture has been developed in collaboration between the University of Granada (Spain) and the IMEP-LAHC laboratory (Grenoble, France).

MS-DRAM is an innovative memory cell based on the Meta-Stable Dip (MSD) effect. Meta-Stable DRAM was developed at the UCL and investigated in collaboration with the IMEP CNRS laboratory (INPG, France). Current CNRS researchers include Maryline Bawedin and Sorin Cristoloveanu. The MSDRAM is dedicated to multiple-gate SOI technology. MSDRAM takes advantage of the double-gate operation in fully depleted SOI. One gate is used to adjust the body potential and the other gate reads the corresponding current values in ‘0’ and ‘1’ states. The MSDRAM displays improved performances such as the retention time and Ioff current level. Furthermore, with this specific memory array configuration and operation, the programming time and voltage are competitive leading to significant reduction in power consumption. This device is aggressively scalable as demonstrated by numerical simulations down to 30nm gate length. In comparison with other memories using only one transistor, the MSDRAM exploits the full depletion and double-gate action (for enhanced scaling capability). This results in very long retention time up to 20sec at room temperature, high Ion/Ioff (103 with I1=20μA/μm and I0=10nA/μm), and low-power consumption.

The International laboratory LEMAC, part of the IEMN (UMR CNRS 8520), led by Nicolas Tiercelin, proposed a concept for a non-volatile magneto-electric memory, or MELRAM, based on the effect of an anisotropic piezoelectric stress on the magnetization of a giant magnetostrictive material embedded in a piezoelectric matrix (patent pending). Thanks to an internal biasing field, the magnetization of the magnetic element has two quasi-perpendicular equilibrium states. A positive voltage across surrounding electrodes leads for instance to a positive stress that sets the magnetization to one of the two states, and a negative voltage sets the magnetization in the other position, regardless of the previous state. For 100nm cell sizes, less than 1V is required to write the information. The writing current should be as low as in the ferroelectric memories, as well as the switching time. The readout can be made via spin-valve or GMR effects, which avoids destruction of stored information. This element could be used for RAM, non-volatile storage as well as in FPGA types components. Given the low energy consumption, this type of memory is a serious contender for 3D integration of memory cells, allowing a dramatic increase of the memory density.

The use of these emerging technologies will change chip design. Non-volatile memories such as magnetic random access memories (MRAMs) will help to overcome the drawbacks of classical programmable logic (as FPGAs) without significant speed penalties. Beyond the obvious advantage of power saving during the standby mode, it also will benefit the configuration time since there is no need to load the configuration data from an external non-volatile memory. Furthermore, during circuit operation, the magnetic tunnelling junction (MTJ) can be written, which allows a dynamic configuration and further increases the flexibility. Instant on/off power is the most important feature allowed by this kind of technology, suitable for many embedded systems from processor architecture to application specific integrated circuits (ASICs). LIRMM laboratory, under Lionel Torres, is currently working on emerging memories applications.

To become involved with any of these CNRS research projects, contact FIST SA, which is responsible for the licensing and the transfer of technologies from CNRS to the commercial sector. Learn more at www.frinnov.fr, e-mail [email protected].

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(October 27, 2010) — Xilinx Inc. (Nasdaq: XLNX) debuted a stacked silicon interconnect technology for breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package. The stacked silicon package suits applications that require high-transistor and logic density, as well as intense computational and bandwidth performance.

Podcast interview with Xilinx about stacked silicon interconnect

In an interview with Debra Vogler, senior technical editor, Liam Madden, corporate VP, FPGA development and silicon technology at Xilinx, describes the details of the silicon interposer. Madden explains that the TSVs only carry power and I/O signals from the package through the interposer to the FPGA. Madden also explains that using an interposer simplifies the CAD flow. Another unintended advantage of using the interposer is the stress relief provided to the low-k dielectric at the surface of the FPGA.

Podcast: Download or Play Now

By embracing 3D packaging technologies and through-silicon vias (TSV) for its 28nm 7 series FPGAs, Xilinx’s Targeted Design Platforms can address systems with resource requirements that are more than double the reach of the largest single-die FPGAs. This innovative platform approach enables Xilinx to overcome the boundaries of Moore’s Law with power, bandwidth and density optimization for the large-scale-integration. Insights from the Leading Edge blogger, Dr. Phil Garrou, says that "the true 3D aficionado has been waiting for the first true commercial product announcement," and assesses the technology announcement on these grounds here.

“One of the ways the 28nm Xilinx 7 series FPGAs extend the range of applications programmable logic can address is by offering industry-leading capacity of up to 2 million logic cells, with use of stacked silicon interconnect packaging,” said Vincent Tong, Xilinx SVP.

The 3D packaging approach was developed over 5 years with internal Xilinx resources as well as technology from Amkor (AMKR) and TSMC. The device is made possible by micro-bump assembly by Amkor, advanced technology from TSMC and patented FPGA architectural innovations from Xilinx that deliver lower levels of power consumption, system cost and circuit board complexity compared to using multiple FPGAs, each in their own package, for the same application. “Compared with traditional monolithic FPGAs, multi-chip packaging approach is an innovative way to deliver large-scale programmability with favorable yield, reliability, thermal gradient, and stress tolerance characteristics,” said Shang-yi Chiang, SVP of R&D at TSMC. “By using through-silicon via technology and silicon interposer to implement a stacked silicon interconnect approach, Xilinx expects to reduce risks and is on the way to volume production with well-designed test vehicle runs that meet the company’s criteria for design enablement, manufacturability validation, and reliability assessment.”

With software support available in ISE Design Suite 13.1,which is currently available to beta customers, the 28nm Virtex-7 LX2000T device will be a multi-die FPGA that provides more than 3.5× the logic capacity of the largest current-generation Xilinx 40nm FPGA with serial transceivers and 2.8× the logic capacity of the largest competing 28nm FPGA with serial transceivers. The technology’s ultra high-bandwidth, low-latency and low-power interconnect allows customers to implement applications applying the same approaches used for large monolithic FPGA devices, using the software’s built-in auto partitioning capabilities for push-button ease-of use, or hierarchical and team-based design techniques for the highest performance and productivity.

Within the Xilinx stacked silicon interconnect structure, data flows between a set of adjacent FPGA die across more than 10,000 routing connections. Compared with having to use standard I/O connections to integrate two FPGAs together on a circuit board, stacked silicon interconnect technology provides over 100X the die-to-die connectivity bandwidth per watt, at one-fifth the latency, without consuming any high-speed serial or parallel I/O resources. By having die sit adjacent to each other and interfaced to the ball-grid-array, Xilinx can avoid the thermal flux and design tool flow issues that would be introduced had a purely vertical die-stacking approach been taken. Xilinx’s choice of 28nm HPL (high-performance, low-power) process technology for the base FPGA device provides a comfortable power budget in the package for integrating FPGA die.

“The availability of proven TSV technology along with low-latency interposer structures is being used effectively by Xilinx to expand the capabilities of their FPGA products,” said Dr. Handel H. Jones founder and CEO of IBS, Inc (Los Gatos, CA). “The technologies used by Xilinx have been used in the high-volume manufacturing environment, with the expectation that the quality and reliability of the finished products will be high, where customer risks are very low.”

Software support will be available in ISE Design Suite 13.1, which is currently available to beta customers. Initial devices will be available in H2 2011. For more technical information including white papers, visit http://www.xilinx.com/stacked-silicon.

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(October 26, 2010) — Nanoplas, supplier of HDRF plasma processing equipment for MEMS, 3D through-silicon via (TSV), IC packaging and III-V compounds, introduced a fully automatic dry-processing batch system for high-volume 200mm production. The DSB 9000A is based on Nanoplas’s High Density Radical Flux (HDRF) technology.

The DSB 9000A performs key production steps in microelectronic manufacturing, including removal of Bosch-process polymers, residues and photoresist from 80-250°C; isotropic etching of organic sacrificial layers; and pre-wafer bonding activation.

The DSB 9000A outperforms conventional radio-frequency (RF) plasma and microwave systems, while greatly reducing the risk of surface damage, said Gilles Baujon, CEO of Nanoplas. With 100 percent gas disassociation, the DSB 9000A ICP source produces free-radical concentration levels of up to 1,000 times greater than conventional plasma sources, thus providing enhanced process performance, including higher cleaning performance for high aspect ratio structures. The system’s proprietary technology eliminates the charging effects and UV radiation normally associated with conventional plasma, allowing stiction-free processing and low-temperature operation.

HDRF offers 3 modes of operation covering a wide range of processes, from ultra-sensitive surface cleaning to removal of non-reactive residues. Typical throughput for photoresist stripping is 60-70 WPH, and greater than 100 WPH, per process module, for post-Bosch cleaning and surface activation.

Nanoplas is an innovator of specialized production solutions that deliver low-cost, green alternatives for treating wafer surfaces in next-generation devices, advanced MEMS, 3D TSVs, advanced packaging, power ICs, optoelectronic components and III-V compounds. Visit www.nanoplas.eu for more information.

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(October 14, 2010) — The 7th International Conference "3-D ARCHITECTURES FOR SEMICONDUCTOR INTEGRATION AND PACKAGING" will take place December 8-10, 2010 at the Hyatt Regency San Francisco Airport Hotel. Check out the planned keynotes and topics of the conference.

3D integration and packaging is now well known to all in the semiconductor industry. Today the focus has shifted away from trying to understand the technology opportunity to one of understanding the practical challenges of technology adoption and commercialization, including who is getting there first, how, and at what cost.

3D integration and packaging, of both devices as well as systems, represents an industry inflexion point, not just an evolutionary change — thus there is a natural degree of uncertainty as companies scramble to secure market share, obtain new process and design tools, and of course, new customers and new applications.

This conference continues to give a broad, yet thorough perspective on the technomarket opportunity and challenge offered by building devices and systems in the vertical dimension. Industry leaders from around the world are invited to speak at this conference, on a wide range of topics important to the emerging and ongoing 3-D integration and packaging efforts. The format of the conference and its presentations enables speakers to present the most up-to-date and forthright perspectives as possible. 3-D Architectures for Semiconductor Integration and Packaging targets senior-level technologists, managers, and executives as speakers and attendees from leading companies and organizations around the world. The result is a unique forum where one can gain the latest insights to bring clarity in the direction of their own efforts.

This year’s conference sessions include:

  • Meeting the 3-D Opportunity
  • Toward the Frontline of Manufacturing
  • 3D Interposers — Where, When, and Why?
  • Critical Perspectives on 3D IC Standards
  • Facilitating Design of 3D Interposers and Die
  • 3D IC Advancements and the Systems Approach
  • Handling, Bonding, and TSV Manufacturing Capabilities
  • New Routes to Logic

Keynote speakers:

  • Subramanian Lyer, IBM Fellow, IBM
  • Douglas Chen-Hua Yu, Senior Director of Integrated Interconnect and Packaging Division, TSMC R&D Group
  • Ho-Ming Tong, Chief R&D Officer & General Manager of Group R&D, ASE Group
  • Antun Domic, Senior VP and General Manager Implementation Group, Synopsys

Pre-Conference Symposium: Key Topics in Going 3-D
The Evolving 3-D IC Infrastructure
Test in the Third Dimension
Thermal Management of 3D Architectures: Challenges and Opportunities
Taiwan R&D for 3-D ICs

Visit http://techventure.rti.org/Winter2010 for more details

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by James Montgomery, news editor

October 12, 2010 – A daylong series of presentations, facility tour, and one-on-one discussions at a recent SEMI-hosted seminar at the U. of Albany College of Nanoscale Science and Engineering (CNSE) spurred intense discussion about the state of leading-edge chipmaking technologies, including 3D ICs and new device structures, and why Wall Street and roadmaps are hampering true technology innovation.

Everyone’s working on new devices, structures

With rising design costs and R&D costs vs. sales, it’s a world of "bigger bets" as design starts taper off for all but higher-volume apps, noted David Bennett, VP of alliances for GlobalFoundries. But for those successful advanced technologies, the revenue payback climbs steeply at 4Xnm vs. 65nm, he said. Notably, GF is making such a bet with its forthcoming Fab 8 in nearby Malta, NY, which Bennett called the "critical mass" center of the company’s manufacturing plans (while keeping "significant modules" in Dresden and Singapore).

A day at Albany CNSE:
Leading-edge techs, innovation vs. efficiency
Mapping EUV’s progress
Drilling down into packaging
Nanofab tour, future plans, and unearthing Washington

SEMATECH, meanwhile, is addressing the growing need for better-mobility materials by combining silicon with III-V’s 100× faster mobility, reported Bill Taylor, program manager for SEMATECH’s frontend process integration and characterization. Current work (in Austin, TX) on 200mm wafers has addressed tool cross-contamination, and achieved >75% yields with "good" uniformity, and resulting devices comparable or better than most reported surface channel devices, he said. Eventually SEMATECH will "bring it to the 300mm world," maybe six or eight years from now. He also described work in nanowire FETs (the evolution of standard FinFETs), starting with a simple transistor but also making more complex structures, e.g. NEMS switches, ring oscillators, and complex memory structures (1T1R).

CNSE also has work on III-V transistors, including figuring out how to incorporate magnetic tunnel junctions which are contaminants to silicon, as part of its "derivative development" for proof-of-concept technologies on an IBM flow, according to Michael Liehr, AVP for business/alliances/consortia at CNSE. He also described a broad collaboration among CNSE, SEMATECH, and the Semiconductor Research Corp. (SRC) in a range of areas, some with immediate impact (e.g. equipment infrastructure, metrology, process development) and others 10-20 years out (novel materials and device concepts, e.g. graphene-based). This includes CNSE’s Center for Advanced Interconnect Science and Technology (CAIST) charged with developing interconnect technology down to 11nm (e.g. C4), a post-CMOS switch consortium, focused on processes and standards for using graphene around the 6-8nm generation, and a connectivity center (led by Georgia Tech) focused on <65nm "more than Moore" technologies, e.g. system-level 3D integration.

Included in discussion of new semiconductor technologies and structures is the next wafer size upon which to put them. ISMI continues to coordinate 450mm work; after initial testbed/prototype work in 2008 and metrology and process equipment development in 2009, final steps in 450mm development for 2010 and beyond show fewer, yet ultimately the most important, work: equipment prototypes, demonstrations, and equipment readiness.

Why roadmaps are hurting innovation

Peter Wright, research director at Tradition Equities, shone the light onto discussion of leading-edge technologies from a different angle: the potential drawbacks of a focus on efficiency and emphasis on development over research, including (and possibly exacerbated by) the adherence to an industry roadmap.

Wall Street and industry views don’t see things the same way, he explained. Where the Street thinks optimistic metrics are risky divergence from average trends, the industry understands its usual inherent ebbs and flows — e.g., higher capital spending is supported by more than a dozen new fab projects, but the Street wants to get out ahead of the next downward curve. The most recent cyclical upswing was longer and more pronounced than a typical upswing, say Street watchers, while to industry this is irrelevant since this is the first demand-driven cycle in a while. Record profits are unsustainable, says the Street — but industry says profits will improve thanks to improved operational efficiencies. Wright showed a number of charts illustrating a sectorwide lack of enthusiasm from investors, even though fundamentals have outperformed, from growth to profits to capital intensity.

The real problem, Wright claims, is that manufacturing is the true source of innovation, but has been usurped by worship of efficiency, taken form as the industry’s technology roadmap. Manufacturing is being driven by quarter-to-quarter economics and moving away from vertical integration, he said, but innovation is highly dependent upon integrated feedback, especially during manufacturing. Outsourcing and depending upon others’ processes limits design optimization and makes second sourcing of manufacturing difficult — e.g. a HKMG gate-first design is highly unlikely to be second-sourced to someone who uses a gate-last approach. (An audience member during the Q&A pointed out that the trap of being a foundry, even TSMC, is always being a fast follower. GlobalFoundries’ Bartlett noted that advanced technology is driven by advanced designs, e.g. MPUs — but zinged that he would not dispute that point regarding his Taiwanese competitor!)

And while industry roadmaps get everyone proverbially on the same page to pursue efficiently manufacturable technologies, this promotes the very standardization and consolidation that shuts out innovations (and investments) in disruptive technologies that drive sustainable industry growth, Wright argued. "The roadmap is the biggest hindrance to research," he stated. "R&D is becoming D." In the Q&A, David Bennett, VP of alliances for GlobalFoundries, offered that stifled innovation blamed on roadmaps is not necessarily a bad thing, but the trick is how to apply it to R&D. Roadmapping is essential to stay on the leading-edge of manufacturing, but "fewer companies are playing that game," added Michael Liehr, AVP for business/alliances/consortia at CNSE. The ITRS‘ vagueness in areas like 3D leaves room for innovation to happen, he added and opens up the field to more players with "no limit to creativity."

Wright suggested future sources of manufacturing innovation will be fleshed out from efforts to optimize the supply side of the industry: e.g. decreasing wafer lots vs. making bigger wafers, fab optimization vs. new fabs, reduced cycle times vs. squeezing the supply chain, and standardization vs. centralization — and even economic savvy vs. pricing power (think ASML and lithography tools).

(October 7, 2010) — austriamicrosystems Full Service Foundry business unit introduced its “More Than Silicon” initiative, a comprehensive service and technology package that goes beyond standard foundry services. Foundry customers receive access to leading-edge technology add-ons, advanced packaging services, and dedicated support engineers to enable first-time-right designs.

The “More Than Silicon” offering provides austriamicrosystems’ foundry customers access to leading edge 3D IC integration using austriamicrosystems’ patentedthrough silicon via (TSV) technology. This advanced TSV technology enables the smallest form factors and addresses a variety of markets demanding 3D integration of CMOS ICs, photo sensors, power devices or MEMS components required in automotive, industrial & consumer applications. Foundry customers using the austriamicrosystems TSV concept immediately benefit from a significantly reduced form factor, systems cost reduction and utmost flexibility in IC and sensor arrangement. The leading edge technology add-on package also features a broad memory portfolio, including SRAM, ROM, BIST structures, One-Time-Programmable (OTP) and fully automotive qualified high reliability non-volatile memories (EEPROM and FLASH).

The “More Than Silicon” package comprises dedicated customer support for specialty foundry projects throughout the entire product value chain, including project definition, design, tape out, prototyping and high volume production. Highly skilled and experienced engineers provide consulting services such as design and layout reviews, ESD and EMC consultancy, Place & Route and test program development for wafer sort and final test. Wafer Level Chip Scale Packaging (WL-CSP) is now available as well as assembly services for commonly used ceramic and plastic packages.

“Requirements for leading-edge analog products have gone beyond the first-time right silicon design. The integration of the IC with advanced analog packaging and post-processing technologies is a must to bring a new breed of analog products to the market. austriamicrosystems’ “More Than Silicon” initiative uniquely supports these requirements and provides fabless design houses with access to special libraries and IP blocks, leading edge technology add-ons and dedicated support engineers,” said Thomas Riener, Senior Vice President and General Manager of austriamicrosystems’ Full Service Foundry business unit. “Foundry customers instantly benefit from our new “More Than Silicon” initiative, which is a clear commitment to our customers to help them with manufacturing their complete analog IC product.”

austriamicrosystems’ business unit Full Service Foundry offers RF CMOS, High-Voltage CMOS, BiCMOS, SiGe-BiCMOS and embedded EEPROM processes to fabless customers. austriamicrosystems designs and manufactures standard and customized high-performance analog ICs in the areas of power management, sensors & sensor interfaces and mobile infotainment. austriamicrosystems is listed on the SIX Swiss Exchange in Zurich (ticker symbol: AMS). For more information, visit www.austriamicrosystems.com

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(October 6, 2010) — CEA-Leti and SPP Process Technology Systems (SPTS) have agreed to develop advanced 300mm through-silicon via (TSV) 3D IC processes at CEA-Leti’s 300mm facilities in Grenoble, France. The agreement defines their collaboration on a range of 3D TSV processes to optimize etch and deposition technologies used to create next-generation high aspect ratio TSVs.

The partners will research alternative hardware and processes to address the need for new methods of cost-effective via fill. In some via-middle applications, where the via is created between contact and first back-end-of-line (BEOL) metal layer, via aspect ratios may extend beyond 10:1, and these very high aspect ratios require a new approach to current etch and deposition techniques. 

"3D-IC technology plays a key role in enabling cost-effective performance for the entire micro-electronics industry. Whether for nomadic devices, data centers, MEMS or optical devices, 3D-ICs form the basis of building cost-effective, high performance chips with multiple functionalities. Combining Leti’s advanced research and development knowledge with the technical expertise from an equipment manufacturer with proven production capabilities will cover the complete range of Copper-based TSV processes," said Dr. Laurent Malier, CEO of CEA-Leti. SPTS is encouraged by the possibilities in this joint equipment-and-process development with CEA-LETI, added Kevin Crofton, managing director, SPTS UK Division, and executive vice president, SPTS. “Our etch, physical vapor deposition (PVD) and chemical vapor deposition (CVD) systems are acknowledged technology leaders in the field of TSVs. Leti and SPTS understand the importance and value of creating an optimized TSV solution, and both acknowledge that it is most effective when the wafer-processing-technology and device experts are working together on integrated process flows.”

TSV technology is quickly gaining industry prominence as this method of 3D integration facilitates a thinner interconnect layer between stacked devices, allowing higher density interconnectivity to produce better electrical performance, all resulting in increased functionality and cost-efficiencies, say the partners.

CEA is a French research and technology public organization, with activities in four main areas: energy, information technologies, healthcare technologies and defense and security. Within CEA, the Laboratory for Electronics & Information Technology (CEA-Leti) works with companies to increase their competitiveness through technological innovation and transfers. CEA-Leti is focused on micro and nanotechnologies and their applications. For more information about Leti, please visit www.leti.fr.

SPP Process Technology Systems was established in October 2009 as the vehicle for the merger of Surface Technology Systems and to acquire assets of Aviza Technology. The company is a wholly owned subsidiary of Sumitomo Precision Products Co., LTD, and designs, manufactures, sells, and supports advanced semiconductor capital equipment and process technologies for the global semiconductor industry and related markets. For more information on SPTS please see www.spp-pts.com

Sumitomo Precision Products Co., Ltd, expanded from their core field of aerospace products into such diverse areas as heat-exchangers and heat-control systems, industrial machinery employing hydraulic control, equipment for semiconductor and flat panel display production, ozone generators for protecting the environment and unique motion sensors. For more information about SPP, please visit www.spp.co.jp

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