Category Archives: 3D Integration

By Francoise von Trapp, contributing editor
3D embedded technologies just got closer to volume manufacturing. We’ve been hearing variations on the embedding theme for quite some time, what with GE’s “chips first” approach newest version, which uses a solderless process called embedded chip build up (ECBU), to achieve high performance capabilities with advanced copper / low-k devices; the Fraunhofer IZM’s chip-in-polymer (CiP) technology moving into the industrialization phase with the Hermes Project; and IMEC’s recent contribution to embedded technologies, the ultra-thin chip package (UTCP), which addresses known good die issues. However, none of these have made it to high volume manufacturing as of yet. However, one embedded solution, Imbera’s integrated module board (IMB) technology appears to be on its way, after the company’s announcement of successful Series B funding, which the company expects will take it into high volume production by Q4 of this year.

Risto Tuominen, co-founder and CTO of Imbera Electronics oversees R&D, and technology licensing, and is responsible for the task of taking IMB into high-volume production. He says it’s well known that the cost of packaging has been increasing over the years. “We believe embedding technology is one of the most powerful solutions,” says Tuoiminen, adding that the success of bringing embedded technologies to volume production is to “keep things very simple”. He says this is what has thus far prevented other embedded processes from breaking out of R&D.

Tuominen’s relationship with IMB technology extends back to his university days and the technology’s earliest version. “The early version worked, but it wasn’t suited to high-volume production,” he explained. The solution was to go back to the drawing board to focus on developing a product geared to high-volume production. Third-generation IMB reportedly does just that.

The process itself (Figure 1) begins with active and passive component attachment to the base substrate, followed by core board stack-up in which the PCB core is built up around the components. The core has copper on both sides. The next step is core pressing and via formation using laser technologies to clean and form vias. Final PCB processing involves plating and pattering. In the final plating process, vias are filled with copper to form the electrical connections, eliminating the need for wire bonds. The process is suited to an assortment of applications from low-cost / low-complexity QFN and BGA type packages (what Imbera has dubbed iQFN, and iBGA); system-in-package modules (SiP) from those that embed actives with few passives, up to more complex configurations such as full-array package on package (PoP) with integrated EMI shielding; to the most complex system-in-mother board (SiB).

Figure 1: IMB’s process flow.

Tuominen says the simplicity of the structure lends itself to more freedom in the designs. Thermal issues are virtually nonexistent because thermal vias can be designed into the front and back side of the components to improve heat conductivity. Additionally, the manufacturing process uses standard materials and equipment to enable scalability to high volume at low cost. For example, rather than requiring costly flip chip placement equipment for assembly, a high-speed chip shooter can be used.

With technology solutions firmly in place, Imbera will use this latest round of financing to set up a high-volume manufacturing operation in Sangsong-ri, South Korea, while continuinge its embedded technology evolution into the 4th generation through R&D activities located in Espoo, Finland. Production at the new South Korean facility is scheduled to begin in Q4 2009. Successfully achieving funding in this economy is an achievement to be applauded. Something tells me we’ll be hearing a lot more from this company.

For more on how Imbera plans to take on the supply chain for 3D packaging, visit Francoise in 3D.

Contact Francoise von Trapp

The Riley Report


April 14, 2009

Non-traditional Applications of Jet Dispensing
by George A. Riley, Contributing Editor

While jetting of fluids has become common in semiconductor packaging, it is finding new applications in emerging fields. At the recent SMTA Pan Pacific Symposium, Alec Barbiarz of Asymtek described jetting opportunities in medical analytics, high-intensity lighting, active-matrix displays, green energy, and 3D assemblies. In most of these applications, the jetted materials are not just part of the packaging, they are an essential component of the device.

For example, the growing life sciences field of on-chip blood analysis requires depositing chemicals into wells in each die of a semiconductor wafer. Both the amount dispensed and the location must be carefully controlled, while the large number of die per wafer calls for high-speed dispensing. That combination &#151 carefully controlled, high speed &#151 defines the territory of today’s jetting.

The blue LED has lighted the way to high-brightness white illumination, but to produce white light, the blue must first be covered by a yellow filter. The color temperature of the resulting white light is critically dependent upon the composition, thickness, and the yellow phosphor layer’s uniformity of distribution. Slurry-dispensing leaves a thicker coating of phosphor granules at the LED’s center, thinning towards the edges as the granules settle. Jetting gives a uniform, repeatable layer.

A future replacement for our ubiquitous liquid-crystal flat panel displays may be active-matrix organic light-emitting diodes (AMOLED). A fluid sealant must be dispensed around each display element before glass lamination, so the largest current AMEOLED display requires nearly 900 individually-dispensed seals.

The higher speed of jet dispensing substantially lowers seal dispensing costs by replacing multi-head needle dispensers with a single jet dispenser. An even greater time and cost saving results from jetting filler material inside the seals. The piezoelectric jet dispenses multiple small drops uniformly spaced inside the seal boundary before lamination, saving hours compared with needle-dispensed fluid penetrating along an edge.

Green energy applications of fluid dispensing include both photovoltaics and fuel cells. Photovoltaics require fluid dispensing from beginning to end. The wafers must be uniformly sprayed with a dopant before entering the drive-in furnace. The backside coating of the wafers is also printed or sprayed.

Electrically conductive “buss bars” may be jet dispensed across the wafer to join the cell conductor traces and form a panel. This application is similar to the replacement of bond wires with jetted conductive adhesive edge connections on 3D parallel or offset chip stacks, as shown in my October, 2008 Advanced Packaging article “How 3D is Stacking Up.”

Direct methanol fuel cells (DMFC) are a challenging emerging application for jetting, since they must handle both volatile and corrosive fluids. Holes etched in a silicon wafer permit water and methanol (the fuel) to reach an anode-side catalyst layer where they are reduced, allowing protons to pass through a permeable proton exchange membrane to the cathode side. A counter-current of electrons flows externally from anode to cathode, completing the electrical circuit.

The proton exchange membrane is a DuPont perfluorosulfonic acid polymer, which can be jet-dispensed with a volatile solvent. The catalyst layer may be carbon black, dispensed as an ink. Complications include that the carbon black can settle and clog a jet, the ink may not properly wet the surface, and the carbon forms a brittle layer when it dries. The polymer solvent may evaporate, sealing the jet nozzle, and the wetted portions of the jet must resist attack by sulfonic acid.

The automated dispenser includes a mass flow calibration function. When operated in a dam-and-fill mode it has produced uniform dry film thicknesses of 40µm +/- 5.

In summary, the enhanced capabilities of fluid jetting are opening up new, non-traditional electronic and semiconductor assembly applications.

Contact George Riley

By Paul Enquist and Chris Sanders, Ziptronix, Inc.

In 3D IC technology, thinned, planar circuits are stacked and interconnected using through silicon vias (TSVs). 3D vertical interconnect will be used for stacked, inter-chip connections and to repartition chip designs into smaller multiple layers that will form the required circuit. 3D ICs have the potential to alleviate scaling limitations, increase performance by reducing signal delays, and reduce cost.1 Enabling technologies for 3D IC include TSV formation, thinning, and alignment and bonding

AMAT Joins EMC-3D Consortium


February 24, 2009

Applied Materials, Inc. has joined the international EMC-3D semiconductor equipment and materials consortium. Applied offers process and integration capabilities in the fields of etching, dielectric and metal deposition, chemical-mechanical polishing, metrology, and inspection. These capabilities will be used for developing a cost-effective and manufacturable for 3D chip stacking and MEMS integration.

Through-silicon via technology is a new method of combining integrated circuits in a vertical stack to enable higher functionality and lower power consumption in a small footprint. While employing many standard chip processes, TSVs present several new technical challenges for production-worthy manufacturing: maintaining wafer structural and edge integrity of thin wafers, stress and thermal profile control, via processing and device reliability.

“Applied Materials sees the TSV approach as an important enabling technology for tomorrow’s sophisticated image sensors, memory and mixed-signal applications,” said Hans Stork, group vice president and CTO of Applied’s Silicon Systems Group. “Joining forces with other leading equipment and materials suppliers is an effective way to qualify contiguous processes, drive down the cost and enable the widespread adoption of TSV technology. By deploying fabrication equipment, materials and process technology from the EMC-3D member companies, our customers can take advantage of a complete, validated process flow, greatly reducing their own development time and initial investment.”

“We’re very pleased to bring Applied Materials into this consortium and look forward to a productive relationship in developing cost-effective TSV solutions for chip stacking applications,” said Paul Siblerud, EMC-3D chairman and vice president of marketing at Semitool. “EMC-3D is currently at the mid-point of a 3 year objective to bring cost-effective TSV to market. Each member is addressing the technical integration challenges of TSV technology for chip stacking and advanced MEMS/sensors packaging.”

The original goal of the consortium was to create a robust integrated process flow at a cost of less than $200USD per wafer. That goal has expanded to include both a via-first (iTSV™) and via-last (pTSV™) process flow at a total cost of ownership of under $150USD.

Silberud added “There are few bright spots in the semiconductor market currently, however, chip stacking TSV has both technical and cost advantages and are still finding research and development investment and priority. The consortium is actively working on 300mm integration of a Cu-TSV suitable for both iTSV and pTSV (via-first interconnect and via-last packaging). Currently the members are showing a $189/wafer total CoO with a clear roadmap to sub-$150/wafer CoO.”

L


February 23, 2009

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By Gail Flower, Editor-at-Large

This article provides a broad review of the issues affecting socket usage: lead-free challenges, finer pitch adjustments, cost control, standardization, practical customer concerns, and improvements needed for 3D packages and other innovations on the horizon. Through conversations with industry experts, we explore a few common themes from this year’s Burn-in and Test Socket Workshop (March 8 -11, 2009) in Mesa, AZ.

The life of a socket begins when designer sits in a workstation modeling a finite element analysis for the force required to make stable electrical contact between the socket used in test and the device under test (DUT). The designer takes into consideration the information at hand: pad pitch, pad composition, and I/O count. The designer then refers to past data, and, depending on this, the hit-or-miss approach continues until the right results are obtained. The design represents the first step in a series of challenges to modern socket production.

Lead-free Changes
When lead-free was added into the mix, the designer’s job became more complex. RoHS mandates became effective on July 1, 2006, and from that point on sockets needed to be able to test lead-free components made with harder, more forceful contacts. Unlike tin/lead 63:37 solders, the historical data was not applicable to new contacts. Variation in probe tip geometries, spring parameters, DUT metallization, and design differences had to be taken into consideration.

Electrical, mechanical, and cost of ownership remain the constant concerns of test hardware engineers, but the hardness of lead-free materials such as nickel-palladium-gold can wear contact pins quickly and transfer excessive force to load boards, adding to maintenance and replacement concerns. One solution mentioned is to use a crown tip on a spring pin to balance off the hardened stress of lead-free materials. As more force is required to make solid contact, wear issues become more critical.

A lead-free oxide-rich matt tin solder causes increased and variable resistance. Matt tin solder builds up on contact pins, causing a fall in yields. Frequent cleaning solves this problem, but causes a drop in throughput.
One manufacturer designs and builds spring probes for lead-free testing using new alloys, hardening procedures, and surface finishes, as well as different test socket engineering design sets and mechanical properties (geometries, force, bias, internal pin capture). Next, they validated changes through testing using modified IC test handlers and pin cycling machines with test coupons plated with different lead-free finishes. They test with customer applications using lead-free devices.

Though some problems with lead-free have been solved, questions still remain. For example, some customers are still experimenting with different lead-free BGA formulations with varying ratios of tin, silver, and copper. However, the quality of the interconnect is still in question. It is clear that there is not “one” solution to lead-free. For instance, an optimized contacting solution for a pure-tin IC device lead is not the same for a nickel-palladium-plated device. Some probe styles, as mentioned earlier, prove to be suited to hardened connections, depending on the device metallurgy and the way contact is applied in a test environment. Research continues as lead-free contacting solutions are still being developed and optimized.

At 2008 BiTS workshop, Nick Langston Jr. presented “An Examination of the Causes of Cres Degradation Which Affect the Life of a Test Socket.” He looked at the SAC alloys 105, 305, and 405, the lead-free formulations most often associated with BGAs. SAC 105 is easy to use because it requires little transition from SnPb. However, Au-Sn intermetallic compounds form at Au/snAgCu interfaces, and these cause Cres degradation, which in turn affect the life of a test socket. Other problems that lead-free introduces is the need to use a stab-like contact with a “crown” headed probe. The need to clean contact pins repeatedly is another necessary issue with lead-free.

Each package type and terminal geometry (solder ball and pad size) introduces its own set of variables to be taken into account. The number of solutions matches the number of lead-free solders (NiPdAu, NiAgCu, matte Sn, etc.). Solutions must consider all variables: package type, test application, terminal type, terminal geometry, device type (digital, RF, high-speed digital, high-power).

The Standards Issue
What standards are needed for sockets? In a user’s eyes, the industry has done a poor job establishing standards. Measurement methods for electrical signal integrity and insertion loss should be standardized. Suppliers should know how customers will use their sockets. If a supplier says that one million cycles represent socket life, what does that mean exactly? Both supplier and user should use the same approach to determine a number for socket life.

Pin-life specifications need to state resistance level at insertion count and test conditions. In many testing cases, once pins exceed 100 mO or so of internal resistance, they are worn out. In others, the test can tolerate even 1 O of pin resistance, so a specification that states a statistically reasonable resistance level at X number of insertions would be much more illustrative of the useable pin life.

Traditional IC packages have been quite standardized already to some degree. Leaded packages (2- or 4-sided) already have very standardized pitches: 1.27mm, 1mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, for instance.
“Each leaded package generation pretty much is just a scaled-down version of its predecessor,” said Valts Treibergs, R&D engineering manager, Everett Charles Technologies

The j360 Silicon PathFinder 3D Platform from Javelin Design Automations supports 3D stacked IC design using through silicon vias (TSV). The design tool reportedly extends the Javelin PathFinding methodology and j360 Silicon PathFinder platform to support virtual chip design for co-optimization of system design and 3D interconnect-packaging technologies.

Designers of 3D ICs are now empowered to rapidly explore many potential 3D design implementations for their technical value propositions, and to identify and mitigate risks-benefits and optimize value. Javelin Design Automation Saratoga, CA. www.javelin-da.com

by Debra Vogler, senior technical editor, Solid State Technology

In a bid to expand applications for 3D packaging, NEC has developed a 3D chip-stacked flexible memory to support large-scale high-performance systems-on-chip (SoC). The new SoC’s architecture consists of separate logic (excluding embedded memory cores) and memory chips (chip-stacked flexible memory) that are closely stacked. The company presented results of its development work at the International Solid-State Circuit Conference (ISSCC) 2009 (San Francisco, CA, USA, Feb. 8-12).

Although 3D packaging technology is now applicable to multi-stacked general-purpose DRAM, multi-stacked flash memory, and small-packaged imagers, there is no suitable 3D packaging technology application for SoC, according to Yasunori Mochizuki, GM of NEC’s device platforms research laboratories. The company anticipates that by developing these technologies, new applications using 3D packaging will come about to realize large-scale SoCs.

Embedded memory area reduction cannot enjoy the benefits of traditional scaling because of process variations, Mochizuki told SST. Additionally, the required embedded memory size increases more rapidly as the logic size (number of logic gates) increases.

The chip-stacked flexible memory developed by NEC is a third kind of memory that features both fast access in the embedded memory and large memory size in the general-purpose memory. It also enables dynamic memory allocation during LSI operation that is effective for an SoC’s multiple functional IP-cores (functional blocks), thereby reducing SoC design and fabrication costs. These features are enabled by having separate logic and memory chips — memories are placed on top of the logic IP cores, as well as network-on-chip (NoC) technology and 3D packaging.

According to Mochizuki, flexible memory configurations are enabled because the NoC connects the multiple memories to each other through an interconnect on-chip network that determines how memory tiles are bundled and assigned to logic.

The chips containing the “flexible memory” and logic chip are stacked closely (3D packaging) by using multi-layered LSI wires that are connected without solder-ball bumps. This type of 3D packaging allows for a chip gap to be in the sub-micron range and the wire pitch to be as small as 10μm. — D.V.


Chip-stacked flexible memory chips (top) and logic-chip (bottom). (Source: NEC)