Category Archives: 3D Integration

3D Jargon


February 16, 2009

By Yann Guillou, ST-Ericsson Wireless and Eric Saugier, STMicroelectronics
3D Integration, through silicon via (TSV), 3D packaging, 3D TSV, 3D system-in-package (SiP), 3D system-on-chip (SoC), and 3D system-on-package (SoP) are some of the hottest topics presented at conferences to standing-room only audiences or read about in popular tech magazines. All of these are definitively trendy terms; no one would argue to the contrary. So it’s about time to take a serious look at 3D in its broadest meaning.

Terminology is a real mess; everyone uses their own terms and often mixes them all together. The confusion mainly stems from partial understanding. We hope we can bring a bit of clarity to the chaos.

First of all, 3D configurations are not new at all. 3D configurations at the packaging level have been around for years.

Stacked dies with wire bonds in BGA are an example of this. For instance, in 2003, STMicroelectronics announced a stack of 10 dice, a world record at that time. Since then, some packaging houses and IDMs have produced stacks with up to 40 dice! No one would argue that 40 dice on the vertical axis is not 3D.

Other 3D packaging configurations are called package-on-package (PoP), or package-in-package (PiP) and other nomad devices. Some packaging evolutions of PoP and PiP still using the third dimension have been lately announced by top SATS providers (Fan-In PoP, MaPPoP, through-mold-via TMV

By Chris Sanders, Ziptronix Inc.
The momentum building around 3D IC integration technology over the past few years makes it clear that this technology is going to happen &#151 it’s just a matter of when. There are three main components to 3D IC technology: through silicon via (TSV) formation; thinning; and bonding. The numerous process flows that exist for 3D integration are all related to the sequence in which these three processes occur1.

When it comes to via formation, one of the questions that must be answered is whether to form the TSV before or after the IC is completed

DNP Develops Slim Leadframe


January 29, 2009

(January 29, 2009) TOKYO &#151 Dai Nippon Printing Co. Ltd. (DNP) developed a package leadframe to slim down the semiconductor package mounted on electronic devices, including mobile terminals and PCs. The leadframe enables semiconductor packaging with a thickness of 0.15 mm, approximately 1/20 the thickness of existing general products, according to the company.

The new packaging developed by DNP differs from existing formats created by mounting the IC chip on top of the leadframe. DNP has established a technology that leaves only the necessary circuit portion of the lead frame, removes the plate mounting for the IC chip, and, in cases where it is structurally necessary, etches the leadframe portion used for mounting the IC chip into a concave shape, into which the IC chip is then embedded. By downsizing not only the leadframe, but also slimming down the IC chip and mold to the maximum possible extent, it has become possible to create a semiconductor package that is significantly thinner than previous generations of devices.

The precision of the plated area has been improved by roughly three fold to ±0.050 mm from the existing ±0.150 mm, and it has also been possible to achieve improvements in humidity reliability at the same time.


The 0.15-mm package.

In line with the shift to more compact and increasingly high performance in a variety of electronic devices, including mobile PCs and mobile phones with PDA functions, there has been a sharp pick up in demands for downsizing, slimming down, and densification of semiconductor packages, DNP explains, adding that 3D packaging also is experiencing an uptick in demand. These include 3D packages that multi-layer the semiconductor packaging, package-on-package (PoP); and those that multi-layer the IC chips, die stacking.

In the case of multilayered-IC-chip semiconductor packaging; while it is relatively easy to achieve a slimming down of the overall package, given that it is the IC chip itself which is multilayered, other issues remain, including the fact that it is not easy to assure the quality of each individual multilayered chip (determining known good die or KGD), and also of declining yields. As a result, DNP considered the multilayered semiconductor package type, where the quality of the IC chips can be screened on an individual basis, to be the optimum type for its purposes, and has developed a lead frame for use with the slim molded semiconductor package.

The leadframe with an embedded IC chip and high-precision plating developed by DNP completed U.S. patent registration in July 2008, with Japanese patents pending. The company will also exhibit this lead frame at the DNP booth (West 6-14) at the NEPCON WORLD JAPAN (the 10th PRINTED WIRING BOARDS EXPO) to be held at Tokyo Big Sight from January 28.

For more information, visit www.dnp.co.jp.

(January 13, 2009) SAINT JEOIRE, France &#151 Smart Equipment Technology (S.E.T.), a wholly-owned subsidiary of Replisaurus Technologies, announced a collaboration with IMEC to develop die pick-and-place and bonding processes for 3D chip integration using S.E.T.’s flip chip bonder equipment. As part of the collaboration, S.E.T. will join IMEC’s Industrial Affiliation Program (IIAP) on 3D integration.

IMEC’s 3D integration program explores 3D technology and design for applications in various domains, focusing on 3D wafer-level packaging and 3D stacked-ICs, to find cost-effective uses for 3D interconnects. The joint development program will use the S.E.T. FC300, a high-accuracy (=0.5&#181m), high force (4,000N) device bonder system for D2D and D2W bonding on wafers up to 300mm. The parties will collaborate to develop highly-accurate pick-and-place and low-temperature bonding processes, which are required by advanced 3D integration schemes. The program is scheduled to begin during the first quarter of ’09.

Luc van den Hove, executive V.P. and COO of IMEC, says both Replisaurus and S.E.T. technologies are interesting for advanced packaging applications, and that S.E.T.’s FC300 device bonder system will help complete IMEC’s program.”The integration of the FC300 will be a welcome addition to our 3D program, as is the participation of S.E.T. and Replisaurus,” said van den Hove.

The FC300 is complimentary to electrochemical pattern replication (ECPR) technology, which is well-suited for advanced 3D integration and related applications, notes James Quinn, CEO of Replisaurus. “IMEC’s installation of the FC300 is fully in line with Replisaurus’ product and technology portfolio, which offers game-changing opportunities to the global chip market,” he said.

(January 7, 2009) ST. FLORIAN, Austria and ROLLA, MO&#151 In response to a call for localized support and increased demand of 3D IC process development in Asia Pacific, EV Group (EVG) and Brewer Science, Inc. have set out to outfit an ultra-thin wafer bonding lab in Taiwan. To this end, the companies announced the installation of an EVG 500 series wafer-bonding system at Brewer Science’s Taiwan applications lab in Hsinchu Science Park.

This move is reportedly set to continue the momentum of the two companies’ joint development efforts to speed commercialization of through-silicon via (TSV) technology and leverage their bonding and materials expertise for thin wafer handling in Taiwan. Stefan Pargfrieder, EVG’s business development manager, explained that the leading adopters of novel processes, such as TSV, are based primarily in the Asia Pacific region. “The move to jointly manage customer process development locally is a logical progression in advancing our partnership efforts with Brewer Science,” he said. “By leveraging Brewer Science’s facility and equipping them to handle temporary bonding demonstrations, it allows us to have faster cycle times and a more centralized hands-on lab to collaborate closely to adapt the process to our Asia-Pacific customers’ requirements.”

“Adding EVG’s 500 series bonder to the laboratory in Taiwan will help accelerate the adoption of TSV and 3D packaging technology in the region.” predicts Mark Privett, product manager of bonding materials at Brewer Science, Inc. He said that by equipping the lab with the bonder also provides local engineers with a regional location for process training.

EVG and Brewer Science first announced ultra-thin wafer handling capability for TSV creation to enable 3D chip stacking in December 2007. EVG’s 500 series wafer bonding system was integrated in the applications lab in December 2008. To formally initiate the joint efforts in Taiwan, the companies will host a technology workshop in Hsinchu on January 15, 2009, featuring presentations by EVG and Brewer Science specialists on solutions for 3D interconnects using thin-wafer handling technology.

3D Interconnection Cube


December 5, 2008

The 3D interconnection chip carrier from Microcertec S.A.S 3-D combines precision-grinding of ceramics with thin-film metallization and laser micromachining to create a 3D package option for chips and ICs. Ceramics reportedly offer better heat dissipation, electrical insulation, and dimension stability at extreme temperatures than plastics and metals. This carrier is said to enable reduced package weight and size while assuring precision in positioning the electrode array.

Manufactured from a 3D ceramic body that is fully machined to required shape and tolerances, a thin metal layer is then deposited onto it by vacuum thin-film deposition technology. Finally, laser ablation is used to micro-machine the metal layer, revealing the IC.

When compared with photolithography techniques for 2-D surfaces, laser micromachining is said to enable the manufacturing of monolithic 3D interconnection devices with more flexibility and no expensive tooling. This technology may be a cheaper solution for prototypes and low-quantity batches of 2-D or 2.5-D formats because it only requires NC programming and laser-processing setting. Single parts can be treated and there is usually no need for expensive fixtures. Changing a circuit pattern only requires a programming modification. Microcertec S.A.S; Coll

December 1, 2008: Applied Materials, Inc. is leading a major effort to enable the widespread adoption of through-silicon vias (TSVs), a rapidly-emerging approach for vertically stacking integrated circuits (ICs) to boost chip performance and functionality in a smaller area. TSVs will be critical to satisfying consumers’ demands for faster, smaller electronics, enabling applications such as DDR4 DRAM memories and future communications and mobile internet chips. Since the biggest roadblock to implementing TSVs is cost, Applied Materials is working internally and with other equipment suppliers to develop an integrated, high-performance on-wafer process flow to lower the cost, reduce the risk and accelerate time to market for customers.

Three-dimensional (3-D) IC integration is a new way for chip designers to deliver higher density, lower power consumption devices in a smaller footprint — without necessarily scaling the technology node. By modifying conventional wafer processing and packaging steps, multiple layers of similar or varying 2-D devices are stacked and interconnected using TSVs so they function as a single device — thus avoiding the cost, space and performance issues associated with combining multiple functions on one chip.


Applied Materials is working internally and with other equipment suppliers to develop an integrated, high-performance on-wafer TSV process flow to lower the cost, reduce the risk and accelerate time to market for customers. (Photo: Business Wire)

The value of TSV-enabled products is expected to increase significantly based on their enhanced performance that will in turn offset the increased cost of manufacturing. The EMC-3D Consortium of equipment suppliers estimates this cost target to be $190 per wafer; Applied’s goal is to reduce this cost to less than $150 per wafer.

“TSV technology will revolutionize chip designs and has great potential to expand into more sophisticated integrated memory/logic applications. Our collaboration with other equipment suppliers is an innovative way of doing business that is beneficial for the industry and can solve our customers’ problems,” said Hans Stork, group vice president and CTO of Applied’s Silicon Systems Group. “The capability to validate complete process flows at our Maydan Technology Center gives us a unique window into how we can lower the cost and mitigate customer risk in adopting TSV processes. By providing the technology and key supplier relationships, we can help accelerate the adoption of TSVs for mainstream manufacturing.”

by Debra Vogler, Senior Technical Editor, Solid State Technology

Dec. 1, 2008 – Sizing up a TSV market beyond the early adopters — e.g., image sensors, server DRAM, and communication/mobile Internet devices — Applied Materials is collaborating with material and equipment suppliers (and others) to ensure the full readiness of TSV implementation with a target cost <$150/wafer. Only two collaboration partners, Semitool and IMEC, have been made public, though other Applied partners span each segment of the TSV cost "pie" and end users' requirements (e.g., EDA tools, reliability, and design).

The company believes end-user adoption of TSV technology will be accelerated if it acts as the “glue” — working with the relevant players instead of waiting an indeterminate amount of time for the gaps in TSV technology to be filled. Statements made by Hans Stork, group VP and CTO of Applied’s silicon systems group, underscore the importance of this approach. “TSV technology will revolutionize chip designs and has great potential to expand into more sophisticated integrated memory/logic applications,” he says in a related news release. “By providing the technology and key supplier relationships, we can help accelerate the adoption of TSVs for mainstream manufacturing.”

Work with Semitool has resulted in an integrated TSV process sequence comprising TSV etch, PECVD oxide and PVD barrier/seed, and ECD copper steps, according to Sesh Ramaswami, senior director of SSG strategy in Applied Materials’ silicon systems group, in an interview with SST.


Figure 1. Applied-Semitool TSV integrated process sequence. (Source: Applied Materials; shown with permission, wafers from ITRI/Ad-STAC)
CLICK HERE to view larger image

Doing its part to contribute to lowering the total cost of TSV implementation, Applied has launched its Silvia etch tool. Brad Eaton, global product marketing manager in Applied’s etch/cleans business unit, told SST the new tool is a kind of “Swiss Army knife,” tailored to meet a wide range of integration schemes — for example, it can work with via CD and aspect ratio ranges of 1μm-100μm, and 1:1 to >25:1, respectively. Processes supported span via first (pre-CMOS silicon and post-CMOS, pre-BEOL oxide and silicon) and via last (pre-bonding metal, oxide and silicon, and post-bonding oxide and silicon). The tool is able to etch silicon and oxide in the same chamber.

Eaton said that Applied’s proprietary version of the time-multiplexed gas modulation process (TMGM, also known as the “Bosch” process) overcomes the poisoning of the etch reaction that accompanies the standard approach. In the standard Bosch process, the etch rate degrades as the etching goes deeper, resulting in a scalloped sidewall. To compensate for the scalloping, the etch rate is slowed down (or poisoned) in traditional TMGM — but cost-of-ownership is thereby degraded. Conversely, he noted, Applied’s proprietary RF and gas modulation technology has a minimal trade-off in etch rate vs. the amount of “scalloping” that occurs.


Figure 2. Minimal tradeoff in etch rate vs. scallop with Applied’s proprietary TMGM process. (Source: Applied Materials)

Besides the technical performance — a silicon etch rate that supports profile control — the new etch tool requires no consumable process kit. Two systems are at customer sites (DRAM manufacturers) in pilot production. — D.V.