Category Archives: 3D Integration

By Gail Flower, Editor-in-Chief
This year’s IMAPS International Symposium, held Nov 3-6, 2008, in Providence, RI had great international participation, good attendance, and excellent presentations from keynoters to the technologically cutting-edge educational papers. It was election day when the IMAPS conference began, and by the second day of the conference, a new president entered the picture. Therefore, the first day proceeded without a rush of attendees as expected, but the second perked up with lively conversation and fuller aisles.

John C. Zolper, Ph.D., of Raytheon, formerly of DARPA, gave a broad keynote with lots of technical information on the challenges facing our industry, starting with a bit of history and ending with the latest frontiers. One goal he identified is to develop design process technology for true 3D ICs with multiple active layers. He also talked about getting more power out of the same footprint, and ending up with a thermal management challenge. Zolper set an agenda of items including: nanostructure materials and their flexible, lightweight ability to change material properties that will be used in the future. He reviewed the integration of MEMS devices in all types of applications from air bag accelerators to Wii consumer games and ink jet printers. Zolper indicated that businesses in the U.S. need collaborations with those doing leading-edge technology research to stimulate the marketplace.

The hottest topic in our industry right now seems to be how to get on board the alternative energy wagon, and here IMAPS had it covered as well with an end-of-day event called Alternative Energy Options: Supply Chains and Industry Trends. Many talked about how distributed the solar energy market seemed and how the lack of policies and incentives to develop this area is holding the U.S. back from what it could be producing.
Alan J. King of Evergreen Solar said that he was encouraged that President-elect Obama has already identified energy independence as a goal for the U.S.

Right now this is where the world stands as controlling the solar market: Germany leads at 45% of the global market; Spain has 25%; Japan holds approximately 15%; and the U.S. trails at 8%. Continual change in government regulations has hindered U.S. market growth in this area; however, in Germany for the last 15 years the market has been subsidized for those investing in solar cells. “We can drill as much as we want, but there is not enough sustainable fuel to support the need,” said King. “Yet enough sunlight reaches the earth every hour to provide the earth’s needs for a year,” he added. Many of the other presenters talked about what the electronics industry is doing to progress the technology and create new jobs in this field in which the market is expanding at 40%/year.

The Global Business Council session focused on how organization fits in with various industry roadmaps. The International Technology Roadmap for Semiconductors (ITRS) concentrates on front-end wafer fabs with a focus on top-level industry segments, but dedicates a chapter on semiconductor assembly and packaging. iNEMI focuses mainly on board-level assembly roadmapping with a chapter on semiconductor assembly and packaging. ITRS and iNEMI are working together to align their semiconductor and packaging roadmaps with many of the same people on both teams. IMAPS focuses on semiconductor assembly and packaging.

According to Laurie Roth, co-chair of IMAPS Global Business Council, IMAPS will address the gaps in these roadmaps, supporting the ITRS and iNEMI updates with input, and communicate back to IMAPS on both issues and trends to recommend areas of focus including developing feasible embedded components, developing enhanced materials to enable wafer-level packaging (WLP), resolving thermal management issues, developing new materials to deliver necessary performance, closing the gap between chip and substrate interconnect density, and resolving the issues that low-k materials and Cu bring to packaging. In many instances, today packaging costs often exceed die fabrication costs. Profit margins must be maintained so that the industry can thrive.

We left IMAPS this year packed with new ideas and filled with a determination to go through the conference technical papers in detail. Here’s where the new ideas abound. All in all, IMAPS was a gem.

The WDF 12DP is designed to address increased demand for probing ultrathin and diced wafers, and wafer-level testing of chip-scale and wafer-level packaging, stacked, and 3D technologies, as well as KGD testing of ultra-hin wafers, singulated wafers, and strips on a dicing frame. It uses on-axis alignment and N-shot alignment, offering “superior” accuracy and the ability to test in parallel. The system can also be used as a standard wafer prober. Tokyo Electron America, Austin, TX; www.ph.com.

October 30, 2008: SEMATECH, in partnership with the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, has received a 300mm Telius SP UD system from Tokyo Electron Ltd (TEL).

The Telius SP UD system is a through-silicon-via (TSV) etch tool that can investigate various chemistries to etch vias ranging from sub-1μm to tens of μm wide. The TSV RIE tool, which is a critical component of all 3D TSV integration schemes, will be used in SEMATECH’s 3D R&D Center at CNSE’s Albany NanoTech Complex in Albany, NY.

“TEL was the first associate member of the 3D program and has been a valued partner of the Interconnect division for many years. Given their experience in deep silicon etching, we are very pleased to partner with TEL on this critical aspect of developing 3D interconnects,” said John Warlaumont, SEMATECH’s VP of advanced technology. “Leveraging CNSE’s pilot line to establish a 300mm 3D R&D center is a unique opportunity. It allows our researchers to address the technical and manufacturability issues of creating 3D interconnects within a state-of-the-art CMOS environment.”

Michael Tittnich, associate VP for technical operations at CNSE, said, “The strategic partnership between the UAlbany NanoCollege and SEMATECH continues to demonstrate global leadership in accelerating cutting-edge nanoelectronics education, research, development and deployment for the benefit of a growing number of worldwide industry partners. This latest acquisition of Tokyo Electron’s next-generation TSV RIE tool expands CNSE’s state-of-the-art 300mm line, while also illustrating the success of SEMATECH’s 3D R&D program and its growing presence and partnerships at CNSE’s Albany NanoTech Complex.”

Issues which have restricted 3D interconnects from entering high-volume manufacturing encompass the front-end, assembly and packaging, and design and test. In an effort to transcend these barriers, SEMATECH’s 3D program has been working jointly with chipmakers, equipment and materials suppliers, and assembly and packaging service companies from around the world on early development challenges, including cost modeling, technology option narrowing, technology development, and benchmarking, while also building industry consensus.

by Gail Flower, Editor-in-Chief, Advanced Packaging
IMEC remains on the forefront of research in many areas including nanotechnology, RF MEMS packaging, flip-chip, substrates, organic electronics, CMOS-based research, solar cells, and 3D stacked integrated circuits. In 3D stacked packages , an area of predicted high-growth, IMEC has announced notable achievements.

This October, IMEC engineers demonstrated the first functional 3D integrated circuits made by die-to-die stacking using 5μm Cu through-silicon vias (TSVs). Die stacking was done using 200mm wafers in IMEC’s reference 0.13μm CMOS process with added on Cu TSV steps. Before stacking, the top die was thinned to 25μm and bonded to the landing die using Cu-Cu thermocompression. The next stage is to migrate the process to a 300mm platform.

Tests confirmed that circuit performance does not degrade by adding Cu TSVs to interconnect the layers. To evaluate the impact of the 3D-SIC flow on the characteristics of the stacked layers, both top and landing wafers contained CMOS circuits. To see how the stacked 3D layers performed, ring oscillators with varying configurations were distributed over the two-chip layers and connected to the Cu TSVs. These circuits were tested after the TSV stacking process to confirm that the signal does not degrade by the addition of copper TSVs , and these circuits demonstrated excellent integrity. Detailed technical results will be presented at the IEEE-IEDM conference in San Francisco this December.


3D stacked IC with die-to-die stacking using copper through silicon vias (TSVs).

CLICK HERE to view larger image

With these tests we have demonstrated that our technology allows designing and fabricating fully functional 3D-SIC chips. We are now ready to accept reference test circuits from our industry partners,” said Eric Beyne, program director of IMEC’s Advanced Packaging and Interconnect Research Center (APIC). IMEC’s program on 3D system integration includes partnering for cost-effective research with several other companies, including equipment and materials suppliers Applied Materials, Disco, EV Group, ICOS, Lam Research, and NEXX. Others include SATS provider Amkor; foundry SMC; ICOS Vision Systems for EDA work; fabless company Qualcomm; Panasonic, Intel, NEC, Texas Instruments, ST, and Infineon for logic; and Samsung, Micron, and Qimonda for memory.

Key features of IMEC’s 3D-SIC Cu-nail platform approach includes the realization of a Cu-nail after the FEOL, but before the actual BEOL. It takes advantage of the high-aspect-ratio Cu damascene technique as opposed to traditional front-end interconnect via processing, and uses a single litho step. Slightly larger features and pitches and a higher aspect ratio are the result. To accomplish the TSV interconnection, Cu-Cu thermo compression bonding is used with simultaneous polymer bonding.

“Achieving coplanar and particle-free surfaces still presents processing challenges,” said Beyne. New cleaning steps will be included in the future.


Eric Beyne, Ph.D., scientific director advanced packaging and interconnect center (APIC).

IMEC is working with the International Technology Roadmap for Semiconductors (ITRS) and Jisso packaging standards group on 3D technology classification. Beyne added that IMEC proposes a classification of the 3D technology based on the interconnection hierarchy, or the level at which the 3D interconnects are made. The industry is debating terminology and who will perform the interconnection steps for 3D integration — fab, packaging, or board-level assembly. The different 3D interconnect types include 3D-SIP, which uses traditional packaging interconnect technologies with wire-bonded stacked die, stacked packages or 3D interconnects at the 2nd and 3rd Jisso packaging identified levels. Another flavor is called 3D-WLP for 3D interconnects made post IC passivation or those at the 1st Jisso level. Finally, 3D-IC and 3D-SIC could happen at the IC foundry level, Jisso’s level 0. These would be 3D-SIC with 3D interconnects at the global or intermediate level of the chip wiring hierarchy. Or they could be 3D-IC which interconnects at the immediate chip level.

Finding the 3D technology design sweet spot with the best of power, cost, performance, and content remains a challenge. With IMEC’s recent advancements, the technology has matured and the next step is to provide a clear roadmap for bringing these packages to the marketplace. IMEC engineers are using PathFinding, a virtual design flow process to help optimize and evaluate critical points for TSV alignment, electro migration, yield, and test process steps.

by Gail Flower, Editor-in-Chief, Advanced Packaging

Oct. 27, 2008 – IMEC remains on the forefront of research in many areas including nanotechnology, RF MEMS packaging, flip-chip, substrates, organic electronics, CMOS-based research, solar cells, and 3D stacked integrated circuits. In 3D stacked packages and photovoltaics, two areas of predicted high-growth, IMEC has announced notable achievements.

This October IMEC engineers demonstrated the first functional 3D integrated circuits made by die-to-die stacking using 5μm Cu through-silicon vias (TSVs). Die stacking was done using 200mm wafers in IMEC’s reference 0.13μm CMOS process with added on Cu TSV steps. Before stacking, the top die was thinned to 25μm and bonded to the landing die using Cu-Cu thermocompression. The next stage is to migrate the process to a 300mm platform.

Tests confirmed that circuit performance does not degrade by adding Cu TSVs to interconnect the layers. To evaluate the impact of the 3D-SIC flow on the characteristics of the stacked layers, both top and landing wafers contained CMOS circuits. To see how the stacked 3D layers performed, ring oscillators with varying configurations were distributed over the two-chip layers and connected to the Cu TSVs. These circuits were tested after the TSV stacking process to confirm that the signal does not degrade by the addition of copper TSVs , and these circuits demonstrated excellent integrity. Detailed technical results will be presented at the IEEE-IEDM conference in San Francisco this December.


3D stacked IC with die-to-die stacking using copper through silicon vias (TSVs).
CLICK HERE to view larger image

With these tests we have demonstrated that our technology allows designing and fabricating fully functional 3D-SIC chips. We are now ready to accept reference test circuits from our industry partners,” said Eric Beyne, program director of IMEC’s Advanced Packaging and Interconnect Research Center (APIC). IMEC’s program on 3D system integration includes partnering for cost-effective research with several other companies, including equipment and materials suppliers Applied Materials, Disco, EV Group, ICOS, Lam Research, and NEXX. Others include SATS provider Amkor; foundry SMC; ICOS Vision Systems for EDA work; fabless company Qualcomm; Panasonic, Intel, NEC, Texas Instruments, ST, and Infineon for logic; and Samsung, Micron, and Qimonda for memory.

Key features of IMEC’s 3D-SIC Cu-nail platform approach includes the realization of a Cu-nail after the FEOL, but before the actual BEOL. It takes advantage of the high-aspect-ratio Cu damascene technique as opposed to traditional front-end interconnect via processing, and uses a single litho step. Slightly larger features and pitches and a higher aspect ratio are the result. To accomplish the TSV interconnection, Cu-Cu thermo compression bonding is used with simultaneous polymer bonding.

“Achieving coplanar and particle-free surfaces still presents processing challenges,” said Beyne. New cleaning steps will be included in the future.


Eric Beyne, Ph.D., scientific director advanced packaging and interconnect center (APIC).

IMEC is working with the International Technology Roadmap for Semiconductors (ITRS) and Jisso packaging standards group on 3D technology classification. Beyne added that IMEC proposes a classification of the 3D technology based on the interconnection hierarchy, or the level at which the 3D interconnects are made. The industry is debating terminology and who will perform the interconnection steps for 3D integration — fab, packaging, or board-level assembly. The different 3D interconnect types include 3D-SIP, which uses traditional packaging interconnect technologies with wire-bonded stacked die, stacked packages or 3D interconnects at the 2nd and 3rd Jisso packaging identified levels. Another flavor is called 3D-WLP for 3D interconnects made post IC passivation or those at the 1st Jisso level. Finally, 3D-IC and 3D-SIC could happen at the IC foundry level, Jisso’s level 0. These would be 3D-SIC with 3D interconnects at the global or intermediate level of the chip wiring hierarchy. Or they could be 3D-IC which interconnects at the immediate chip level.

Finding the 3D technology design sweet spot with the best of power, cost, performance, and content remains a challenge. With IMEC’s recent advancements, the technology has matured and the next step is to provide a clear roadmap for bringing these packages to the marketplace. IMEC engineers are using PathFinding, a virtual design flow process to help optimize and evaluate critical points for TSV alignment, electro migration, yield, and test process steps.

Photovoltaic research

Jef Poortmans, program director of photovoltaics and professor at Katholieke Universiteit Leuven, reviewed what IMEC has to offer in crystalline Si and organic solar cells. Crystalline Si will remain the material of choice for solar cells for the next decade, but to support market growth at the present rate, the cost of cells will have to go down and efficiencies must improve. These are IMEC’s goals, along with developing the next generation of water-based bulk silicon solar cells and epitaxial cells.


Jef Poortmans, Ph.D., department director solar and organic technologies, IMEC.

Today the photovoltaic market is growing at an annual rate of 40%, and of that market, crystalline Si solar cells have a 90% share. The amount of silicon used will have to be reduced by a factor of 2 while efficiencies improve by 25%, going from 16% to 20% for industrial crystalline Si solar cells. Other components, such as metallization layers, surface and contact passivation, should be produced more efficiently as well and with cheaper materials.

“Since we started working on solar cells in 1984, R&D on crystalline Si solar cells has formed the backbone of our activities,” says Poortmans. At present, IMEC is working with wafer-based bulk silicon solar and epitaxial cells. The roadmap aims to reduce active silicon layer thickness from 150μm down to 40μm by 2020. Efficiencies should reach 20% if meeting future goals. Looking at the big picture, IMEC plans to follow several macro trends, he said: “Reduce the grams of Si/W, reduce the wafer loss and thickness, increase efficiency by 20%; reduce manufacturing costs by equipment scaling, fab scaling, reduce expensive materials, standardize, integrate cell manufacturing; speed up the learning curve with new technologies, accelerated the reduction of feed-in-tariffs, and develop PV-dedicated equipment.”


Large area i-PERC solar cell on a thin wafer.

Besides research using generic bulk silicon for solar cells, epitaxial thin-film silicon solar cells on low-cost silicon carriers will also be developed. Epitaxial thin-film silicon solar cell technology is expected to be the intermediate step before mainstream fabs switch from bulk to thin film-like solar cells. Whereas the process is similar, the epi-process can be implemented with limited equipment investment. To improve the optical confinement of light in the active part of the cell, a buried porous Si reflector will be integrated in this future thin-film solar model.

In organic solar cells, IMEC’s associated laboratory, IMOMEC on the campus of Hasselt U., developed a method to stabilize the morphology of organic solar cells. With these stabilized solar cells, efficiencies were achieving that compare with state-of-the-art solar at 4% efficiency. Under long-term operation, all solar cells based on a mixture of organic semiconductors deteriorate due to the segregation of the mixture of compounds, thus reducing the conversion of light into electricity. However, in the latest method, IMEC has fixed the nanomorphology of the polymers and prolonged operational lifetime of the cell. — G.F.


Transmission electron microscopy for polymer/PCBM 1:1 active layers after degradation at 100°C for 2hrs, showing phase segregation for the Rieke P3HT polymer (left), but a stable morphology for the novel polymer organic solar cell.
CLICK HERE to view larger image

by Françoise von Trapp, managing editor, Advanced Packaging

Oct. 21, 2008 – Throwing its hat in the ring with a host of semiconductor companies (R&D labs, fabs, foundries, equipment/material manufacturers, IP companies, and packaging houses) in search of low-cost 3D integration processes, Ziptronix Inc. revealed technical details on its direct bond interconnect technology (DBI), which is said to enable low-cost wafer-to-wafer or chip-to-wafer bonding without high-temperature compression.

Companies and consortiums have been lining up with processes to solve different parts of the equation for some time, such as with the EMC3D Consortium’s achievement of a via-first process flow for TSVs at $189/wafer. Dan Donabedian, CEO, Ziptronix, says he has observed a growing consensus across the semiconductor supply chain that a low-cost high-throughput, reliable bonding process is necessary to bring 3D IC integration into the mainstream. What is well-established, he noted, is that TSVs are going to be part of any large-scale 3D IC process, and that metal-to-metal bonding offers clear advantages. Ziptronix’s contribution is what Donabedian defines as the final part of the equation; a high-throughput, low-temperature oxide bond technology that achieves a metal connection without requiring low-throughput, high-temperature thermal compression.

In a comparison study done by Yole Développment, DBI proved to have a lower bonding cost per wafer than either copper-to-copper thermocompression or adhesive bond process. For a typical fab running 500,000 300mm wafers per year using 1×20μm vias, the bonding costs/wafer level (including CMP) were: $57 for Cu-Cu, $22 for adhesive, and $12 for DBI. Addressing the latter, Chris Sanders, Ziptronix’ director of business development, cited several key elements to cost savings with the company’s proprietary Zibond and DBI processes, including use of nickel as an interconnect metal; elimination of thermocompression and its associated tool requirements (bond chambers, thin wafer/die handling); increased throughput due to reduced cycle time (no adhesive, pressure, or temperature requirements); and the ability to batch process.

Cost per wafer level for different bonding technologies. (Source: Ziptronix/Yole Développement)

Sanders explained that batch processing can’t be done with thermo-compression because of the need for heat. However, the Zibonding oxide bonding process allows wafers to be bonded at room temperature and stored before completing the final interconnect processes; “then in DBI you add heat to achieve the electrical connection between the nickel pads.” The processes accommodate TSVs, but interconnects can be achieved without them, he added.

Initially developed as a way to assemble 3D subsystems (by bonding and interconnecting bare die directly onto a board-mountable substrate), it was a technology whose market was not yet ready for it. However, the market has now caught up, according to Donabedian, citing a demographic shift in attendees at 3D symposiums and conferences — rather than engineers, he’s noticing more business development and marketing executives in the audience, as they educate themselves on these technologies.

Military contractors have been the first to incorporate Zibond and DBI, and Sanders identified CMOS image sensors, focal plane arrays (FPAs), and memory-logic stacks as the next target applications. Although Ziptronix is not part of any consortium targeting 3D integration processes, Sanders and Donabedian said the company is working with tool vendors such as EV Group and Suss MicroTec to enable their technology, and have formed an affiliation with Tezzaron to establish roadmaps for 3D stacked memory.

While most industry analysts still point to 2011 for TSV production, Donabedian predicts earlier adoption in mid-2010. “Those who want to take the lead in the market will find the value-add,” he noted. The logistics chain is different from 12 months ago, when foundries and customers were tossing technology limitations back and forth, he explained. He says he now he sees them working together to understand the dynamics, and that most of the end customers have roadmaps for 3D.

Despite the downturn in the economy, Donabedian is enthusiastic about bringing Zibond and DBI to market, because companies are interested in new technologies that might give them an advantage. “They are opening their doors to Ziptronix right now,” he says. “The timing is perfect.” — F.v.T.

The AltaCVD chemical vapor deposition (CVD) and atomic layer deposition (ALD) tool from Altatech combines a unique vaporizer technology, chamber design, and gas/liquid panel integration. The combination of a proprietary reactor design and precursor introduction path with a pulsed liquid injection and vaporization is said to enable nanoscale control of thickness, uniformity, composition, and stoichiometry in complex materials. These depositions are reportedly unavailable today with existing techniques.

AltaCVD is suited for plasma-enhanced MOCVD and ALD processes of a range of materials used in logic and memory devices, Microsystems, and 3D integration such as high-K gate dielectrics, metal electrodes, high-K coupling dielectrics and electrodes in MIM and DRAM capacitors, ferroelectric materials, chalcogenide alloys for PCRAM, seedless and self-forming copper diffusion barriers, copper seed layers for TSV metallization, transparent conductive oxides, thin film batteries, electrodes and electrolyte. Altatech Grenoble-Monbonnot, France; www.altatech-sc.com

Oct. 6, 2008 – Suss MicroTec has replaced board member and CEO Stefan Schneidewind with Christian Schubert effective immediately, citing “differing views regarding the future strategy of the company.” A search for a new permanent CEO will take place.

Schubert has held senior executive positions at high-tech companies Kontron, cognatec, and Intica Systems, Suss noted in a brief statement posted on the company’s Web site. A lengthier statement posted to general newswires notes that Shubert’s role will essentially be that of a COO, focusing on operations, structures, and processes; in the medium-term a new board member with a more technical background will be appointed.

While short-term goals are to “intensify our operations” and “examine all of the processes within the company and make them significantly more dynamic,” according to Schubert, the company’s basic strategic orientation will be unchanged focusing on “presumably” high-growth markets in sluggish general industry and macroeconomic environments: MEMS, advanced packaging, 3D integration, and compound semiconductors (LED).