Category Archives: 3D Integration

The new, higher-speed DDR4 DRAM generation gained significant marketshare in 2016, representing 45% of total DRAM sales. Previously, DDR3 DRAM, including low-power versions used in tablets, smartphones, and notebook PCs, accounted for 84% of total DRAM sales in 2014 and 76% in 2015, but in 2016, DDR4 price premiums evaporated and prices fell to nearly the same ASP as DDR3 DRAMs. A growing number of microprocessors, like Intel’s newest 14nm x86 Core processors, now contain DDR4 controllers and interfaces.  As a result, IC Insights expects DDR4 to become the dominant DRAM generation in 2017 with 58% marketshare versus 39% for DDR3 (Figure 1).

Figure 1

Figure 1

The Joint Electron Devices Engineering Council (JEDEC) officially launched the fourth generation of DDR in 2012.  In 2014, DDR4 memories first began appearing on the market in DRAM modules for powerful servers and a small number of high-end desktop computers, which had souped-up motherboards or the “extreme” versions of Intel’s 22nm Haswell-E processors for high-performance gaming software and PC enthusiasts, but volume sales remained low until 2015, when data centers and Internet companies began loading up servers with the new-generation memories to increase performance and lower power consumption. In 2016, DDR4 memories quickly spread into more data center servers, mainframes, and high-end PCs, accounting for about 45% of total DRAM sales versus 20% in 2015.  In 2017, DDR4 will move into more notebook PCs, high-end tablets, and smartphones and is expected to hold a 58% share of DRAM sales.

The DDR4 standard contains a number of features that are expected to speed up memory operations and increase SDRAM storage in servers, notebook and desktop PCs, tablet computers, and a wide range of consumer electronics.  The DDR4 standard supports stacked memory chips with up to eight devices presenting a single signal load to memory controllers.  Compared to DDR3, DDR4 can potentially double the module density, double the speed, and lower power consumption up to 20%, thereby extending battery life in future 64-bit tablets and smartphones.

Meanwhile, the DRAM average selling price has been increasing very rapidly since mid-2016.  Figure 2 shows that the DRAM ASP increased 54% from $2.41 in April 2016 to $3.70 in February 2017.  As a result of this big increase, IC Insights raised its 2017 DRAM market forecast to $57.3 billion, which is a 39% increase over 2016.  IC Insights believes that DRAM ASPs will continue to trend upward through most of the first half of 2017, though probably not as rapidly as they did between the period from April 2016 to February 2017.

Figure 2

Figure 2

In its latest quarterly financial conference call, Micron indicated its DRAM outlook through the balance of its fiscal year 2017 (ending August 31) was very encouraging, with solid demand coming from PC, server, communication, automotive, and several other applications.

However, the bigger question for Micron and other top DRAM suppliers is available supply and whether (more accurately, when will) prices plateau and begin trending downward.  One indication that DRAM prices could soften in the second half of the year is the fact that Samsung and SK Hynix are bringing additional DRAM capacity online that features smaller process geometries. Samsung is slated to begin operations at its new Fab 18, in Pyeongtaek, South Korea in 2Q17.  Fab 18, with capacity of 300,000 300mm wafer starts per month, features five production lines that are dedicated primarily to making DRAM.  The company plans to begin DRAM operations at the fab using an 18nm process technology.

SK Hynix has transitioned most of its South Korean-based DRAM output from Fab M10 to Fab M14. With Fab M14 and its dedicated DRAM fab in Wuxi, China, SK Hynix has DRAM capacity of about 280,000 300mm wafer starts per month.  SK Hynix is manufacturing most of its DRAM at the 21nm node, but expects to begin using sub 20nm process technology later this year, thereby helping to reduce costs and increase the number of chips on a wafer.

Following a year of extraordinary gains in pricing, a boost to DRAM supply in the second half of 2017 could lead to reduced ASPs and the inevitable start of a cyclical slowdown in the DRAM market.

Participating in the DRAM market has always been a big challenge for suppliers.  Hot or cold, boom or bust—the DRAM market is rarely moving along in a steady, predictable manner.  For at least the first half of 2017, it appears that DRAM market will be very favorable for these top three suppliers.

“In 2016, the MOSFET market recovered, after a minor downturn in 2015,” announced Yole Développement (Yole) in its latest power electronics report, Power MOSFET: Market & Technology Trends. With stable growth, mainly in automotive and industrial sales in 2016 the overall silicon power MOSFET market size surpassed 2014’s performance.

“We expect the market to grow steadily thanks to increasing demand for efficient electronics, in which power MOSFETs play a vital role”, explains Zhen Zong, Technology & Market Analyst, Power Electronics at Yole. Overall market revenue neared US$6.2 billion. From 2016 to 2022 Yole estimates a 3.4% CAGR.

mosfet market

Under this dynamic ecosystem, Yole reinforces its market positioning within the power electronics industry. The “More than Moore” market research and strategy consulting company is covering step by step the whole power electronics supply chain: from substrates with innovative WBG materials including GaN , SiC , Bulk GaN… to devices (IGBT, MOSFET, gate drivers IC …), modules and systems. In parallel, the company also enlarges its core expertise towards batteries and energy management sector. Yole’s strategy is clearly to propose a deep understanding of the overall power electronics industry by taking into account technical innovations such as WBG technologies, analyze the impact on the supply chain and identify business opportunities.

Yole’s power electronics team attends PCIM Europe with a booth and its annual powerful Power Electronics Market Briefing. During this briefing, the consulting company is inviting industrial leaders to speak and proposes detailed presentations focused on the power semiconductor industry.

Power MOSFET report is one of the key 2017 reports proposed by Yole’s team. It provides an overview of the entire market, with a comprehensive analysis of the players in each market segment with their product range and technologies.

“Under this new report, our aim is to propose our vision of the power electronics industry, from an end-users perspective,” explained Dr Pierric Gueguen, Business Unit Manager at Yole. “Our analysis highlights the corresponding impact on MOSFET technologies and the introduction of WBG technologies which represent only less than 2% of the overall power electronics market today but are showing a real growth potential in a near future.”

In 2016, 25 million electrified vehicles were sold. Power MOSFET sales in automotive applications have surpassed computing and data storage, now representing more than 20% of the total market. As vehicle numbers increase worldwide and people adopt electrified vehicles, this sector’s rapid growth will continue at 5.1% CAGR between 2016 and 2022.

Power MOSFETs are widely used in various automotive applications involving braking systems, engine management, power steering and other small motor control circuits, in which a low conduction loss and high commutation speed device is very much appreciated. Silicon power MOSFETs are also becoming increasingly popular in EV/HEV converters, depending on their electrification level. For battery chargers MOSFETs can handle roughly 3-6 kW, which is perfect for small size plug-in EVs or full EVs. They are also used for 48V DC/DC converters and other micro inverters in the start/stop function module. With the trend of EV/HEV adoption led by Tesla, Yole’s analysts believe this market segment will become increasingly important in the next 5-10 years.

Computing and storage market segment which includes desktops, laptops, as well as different kinds of servers in the datacenters comes to the second largest market. With the declining sales number of personal PCs this market segment is slowing down and has been surpassed by automotive part in 2016. However with the increasing demand for servers and datacenters, the whole segment is still having a steady increase, posting a 2.8% CAGR for the 2016-2022 period.

Power electronics market future may depend on governmental decisions concerning electrified vehicles as well as renewable energies applications. It includes CO2 reduction targets, energy efficiency increases… Both markets could be the most important in 2030, announces Yole in its MOSFET report. On the other hand, other large volume applications may come, such as 5G, drones or robots. All those applications, demanding power supply, will clearly pull the MOSFET market.

Today it is not possible to get a comprehensive understanding of the MOSFETs market without taking into account the impact of the innovative WBG technologies including SiC and GaN.
Silicon power MOSFETs have been developing for 20 years. Ceaseless improvement and technology innovations from planar to trench structure and today’s super junction, have reduced silicon MOSFET device sizes and costs dramatically. They have been massively used in various application segments – but today, device performance has reached silicon’s theoretical limit.
Chasing better performance and even smaller devices size, today the power electronics industry is at the beginning of SiC and GaN’s adoption. Ever more new companies are promoting SiC and GaN solutions and new designs. At Yole, analysts believe this will be the next technology evolution stage. However, this does not necessarily mean doom for silicon power MOSFETs.

“Looking back at the development of bipolar transistors and power MOSFETs in the past 20 years in different applications, we expect that there will still be a very solid market share reserved for silicon power MOSFETs”, analyzes Zhen Zong from Yole. With increasing need in the end applications, the overall market size for MOSFETs will not necessarily decline.

Over the next 5-10 years, Yole envisions some GaN devices coming out and being implemented for high frequency switch applications in the low-to-mid voltage 100-200V range, but remaining a small portion. Both SiC and GaN devices will penetrate the high frequency market around 600V, but will probably only be popular in particular markets, like EV on-board chargers and data center power supply units. The majority of the market will still use silicon power MOSFETs, thanks to their proven reliability and good cost performance ratio.

Cadence Design Systems, Inc. (NASDAQ:  CDNS) today announced the release of the new Virtuoso Advanced-Node Platform supporting advanced 7nm designs. Through collaboration with early 7nm FinFET customers, Cadence has expanded the Virtuoso custom design platform with innovative new capabilities to manage design complexity and process effects introduced with this advanced-node process. The Virtuoso Advanced-Node Platform update supports all major advanced FinFET technologies with proven results, while improving designer productivity at 7nm.

To address the many technical challenges of 7nm design, the Virtuoso Advanced-Node Platform offers a variety of layout capabilities, including advanced editing with multi-pattern color awareness, FinFET grids, and module generator (ModGen) device arrays. Additionally, customers can take advantage of variation analysis in their circuit design flows utilizing Monte Carlo analysis across corners to address variability with the Spectre® Accelerated Parallel Simulator, the Virtuoso ADE Product Suite and the Virtuoso Schematic Editor.

“As a leader in mobile computing, we require the highest performance, lowest power and highest density possible to deliver innovative, advanced-node designs,” said Ching San Wu, general manager of Analog Design and Circuit Technology at MediaTek. “Through our strong collaboration and continued partnership with Cadence, we have been able to develop and deploy a custom design methodology based on the Virtuoso Advanced-Node Platform. With our recent successful tapeout, we took advantage of its many unique capabilities designed to manage the challenges presented at 7nm.”

Key features in the updated Virtuoso Advanded-Node Platform include:

  • Multi-patterning and color-aware layout: Provides essential new support of a variety of fully colored “multi-patterned” custom design flows, which are a baseline requirement for the 7nm process and enable users to be more productive in their designs.
  • ModGen device arrays: Offers designers a set of modules that have been co-developed in close collaboration with key partners to improve designer productivity and mitigate layout complexities at the 7nm process node.
  • Automated FinFET placement: Provides automatic FinFET grid placement that simplifies the overall FinFET-based coloring design methodologies needed at 7nm. By adhering to 7nm process constraints, the Virtuoso Advanced-Node Platform greatly simplifies layout creation and minimizes errors that can be pervasive when designing at 7nm, while decreasing layout design time by up to 50 percent on custom digital and analog blocks.
  • Variation analysis: Enables high-performance Monte Carlo analysis targeting FinFET technology and high-sigma analysis, which can reduce the overall time to run simulations by a factor of 10.

“Through constant innovation and strategic partnerships with industry leaders, Cadence has solidified its leading role in providing advanced-node custom design tools,” said Tom Beckley, senior vice president and general manager, Custom IC & PCB Group at Cadence. “Through our extensive work with customers such as MediaTek, we’ve been able to validate that our approaches greatly reduce the overhead inherent in designing at 7nm in order to help deliver the best possible silicon. We currently have many customers that have completed successful tapeouts and delivered production designs using the Virtuoso Advanced-Node Platform.”

A recent study, affiliated with UNIST has created a three-dimensional, tactile sensor that could detect wide pressure ranges from human body weight to a finger touch. This new sensor with transparent features is capable of generating an electrical signal based on the sensed touch actions, also, consumes far less electricity than conventional pressure sensors.

The breakthrough comes from a research, conducted by Professor Jang-Ung Park of Materials Science and Engineering and his research team at UNIST. In the study, the research team presented a novel method of fabricating a transistor-type active-matrix pressure sensor using foldable substrates and air-dielectric layers.

This image shows the transistor-type active-matrix 3-D pressure sensors with air-dielectric layers. Credit: UNIST

This image shows the transistor-type active-matrix 3-D pressure sensors with air-dielectric layers. Credit: UNIST

Today, most transistors are created with silicon channel and silicon oxide-based dielectrics. However, these transistors have been found to be either lacking transparency or inflexible, which may hinder their utility in fabricating highly-integrated pressure sensor arrays and transparent pressure sensors.

In this regard, Professor Park’s team decided to use highly-conductive and transparent graphene transistors with air-dielectric layers. The sensor can detect different types of touch-including swiping and tapping..

“Using air as the dielectric layer in graphene field-effect transistors (FETs) can significantly improve transistor performance due to the clean interface between graphene channel and air,” says Professor Park. “The thickness of the air-dielectric layers is determined by the applied pressure. With that technology, it would be possible to detect pressure changes far more effectively.”

A convantional touch panel, which may be included in a display device, reacts to the static electrical when pressure is applied to the monitor screen. With this method, the position on screen contacted by a finger, stylus, or other object can be easily detected using changes in pressure, but can not provide the intensity of pressure.

The research team placed graphene channel, metal nanowire electrodes, as well as an elastic body capable of trapping air on one side of the foldable substrate. Then they covered the other side of the substrate, like a lid and kept the air. In this transistor, the force pressing the elastic body is transferred to the air-dielectric layer and alters its thickness. Such changes in the thickness of the air-dielectric layer is converted into an electrical signal and transmitted via metal nanowires and the graphene channel, expressing both the position and the intensity of the pressure.

This is regarded as a promising technology as it enables the successful implementation of active-matrix pressure sensors. Moreover, when compared with the passive-matrix type, it consumes less power and has a faster response time.

It is possible to send and receive signals only by flowing electricity to the place where pressure is generated. The change in the thickness of the air dielectric layer is converted into an electrical signal to represent the position and intensity of the pressure. In addition, since all the substrates, channels, and electrode materials used in this process are all transparent, they can also be manufactured with invisible pressure sensors.

“This sensor is capable of simultaneously measuring anything from lower pressure (less than 10 kPa), such as gentle tapping to high pressure (above 2 MPa), such as human body weight,” says Sangyoon Ji (Combined M.S./Ph.D. student of Materials Science and Engineering), the first co-author of the study. “It can be also applied to 3D touchscreen panels or smart running shoes that can analyze life patterns of people by measuring their weight distribution.”

“This study not only solves the limitations of conventional pressure sensors, but also suggests the possibility to apply them to various fields by combining pressure sensor with other electronic devices such as display.” says Professor Park.

2016 was the year of strong consolidations in the semiconductor industry. Yole Développement (Yole) highlights many mergers and acquisitions with several billions of dollars transactions.

“And 2017 seems to be following the same path,” said Jérôme Azemar, Technology & Market Analyst, Advanced Packaging at Yole.

Year after year, the advanced packaging industry has attracted more and more of the spotlight.

ic market forecast

“According to our estimates, advanced packaging revenues represented more than US$22 billion in 2016 and will increase to almost US$30 billion by 2020”, confirmed Jérôme Azemar from Yole.

What is the status of the advanced packaging industry? Who is leading the market today? What are the platforms that will drive the tomorrow’s industry? What could we expect in term of technology evolution? NCAP China and Yole propose you a 2-day conference to answer these questions and get the opportunity to meet the advanced packaging leaders. They announced today the 3rd Advanced Packaging & System Integration Technology Symposium. The 2017 edition takes place in Wuxi, China, on April 20 & 21.
   • Click program & registration to discover schedule, list of speakers, abstracts, and much more.
• The 2017 symposium is sponsored by BESI, Plasma-Therm, SPTS Technologies, UnitySC and Simco-Ion
   • This year again, ASTRI is a partner of the Advanced Packaging & System Integration Technology Symposium.

Created in 2014, the Advanced Packaging & System Integration Technology Symposium is attracting more and more attendees each year. The powerful program designed by Yole and NCAP China gathers numerous valuable discussions, meetings and business collaborations.

 This year again, both partners are excited to welcome the leaders of the advanced packaging industry and are expecting a great success. They have announced an impressive list of executive speakers including:
   • Tetsukazu Sugiya, Group Leader, Technology Solutions Group at DISCO Corp.
   • Lianming Tong, Lead Marketing Manager at Dow Electronics Materials
   • Kenji Kawada, Staff Engineer at Infineon Technologies Japan
   • Daquan Yu, CTO & VP, Kunshan Huatian Technology Electronics
   • Howard Huang, Director, Kingyoup Optronics
   • Tae-Hoon Kim, Ex. President, nepes Corporate
   • Dr David Lishan, Principal Scientist at Plasma-Therm
   • Richard Barnett, Etch Product Manager, SPTS, an Orbotech Company …

And much more. List of speakers, biographies and abstracts are available on i-micronews.com website. To download the PDF version, click Program. 2017 edition also includes two keynote speakers from Huawei and Brewer Science.

Partnership between both organizations, NCAP China and Yole has been signed 3 year ago and all benefits of this collaboration are serving the development of the advanced packaging industry in China and all around the world. Based on a strategic thinking, NCAP China and Yole combined their expertise and their brand to support the development of this dynamic industry. Both organizations became indispensable players. And as strong influencer, the NCAP China and Yole Symposium is today the relevant indicator of the status of advanced packaging industry.

“We are very pleased to have the opportunity this year again to host the “Advanced Packaging & System Integration Technology Symposium,” saidDr Cao LiQiang, NCAP’s CEO. And he adds: “Mixing together worldwide companies and laboratories, all experts in the advanced packaging arena is just key for the development of the industrial activities in China. It is a relevant contribution to shape the future of the advanced packaging ecosystem. Under this context, we are looking forward to welcome advanced packaging leaders and get powerful presentations and debates during the Symposium.”

Advanced packaging revenue in China is expected to reach US$4.6 billion in 2020 at an impressive 16% CAGR .

“Indeed we are experiencing a key momentum in the semiconductor industry,” announced Thibault Buisson, Business Unit Manager, Advanced Packaging & Semiconductor Manufacturing at Yole. “Lot of technical challenges are now being transferred from the chip to the package itself. This is why industrial companies from different business models are willing to get involved in the exciting advanced packaging field. Under a highly competitive landscape, innovative platforms such as FO packages, 3D & 2.5D interposers and SiP are getting more and more interest from the end users and therefore are changing the packaging ecosystem. NCAP China & Yole Symposium is the place to get a clear understanding of the status of this industry and get answers to future market evolutions, the industry will face tomorrow.”

The symposium represents an exciting opportunity for advanced packaging companies to develop, exchange and expand their activities in China and also in all other countries. NCAP and Yole are very enthusiastic about this 3rd edition. Make sure you will attend the Symposium and book your place right now on i-micronews website or click: Registration. To see the full schedule, please click here: Program.

IEEE, the world’s largest technical professional organization dedicated to advancing technology for humanity, this week announced the next milestone phase in the development of the International Roadmap for Devices and Systems (IRDS)—an IEEE Standards Association (IEEE-SA) Industry Connections (IC) Program sponsored by the IEEE Rebooting Computing (IEEE RC) Initiative—with the launch of a series of nine white papers that reinforce the initiative’s core mission and vision for the future of the computing industry. The white papers also identify industry challenges and solutions that guide and support future roadmaps created by IRDS.

IEEE is taking a lead role in building a comprehensive, end-to-end view of the computing ecosystem, including devices, components, systems, architecture, and software. In May 2016, IEEE announced the formation of the IRDS under the sponsorship of IEEE RC. The historical integration of IEEE RC and the International Technology Roadmap for Semiconductors (ITRS) 2.0 addresses mapping the ecosystem of the new reborn electronics industry. The new beginning of the evolved roadmap—with the migration from ITRS to IRDS—is proceeding seamlessly as all the reports produced by the ITRS 2.0 represent the starting point of IRDS.

While engaging other segments of IEEE in complementary activities to assure alignment and consensus across a range of stakeholders, the IRDS team is developing a 15-year roadmap with a vision to identify key trends related to devices, systems, and other related technologies.

“Representing the foundational development stage in IRDS is the publishing of nine white papers that outline the vital and technical components required to create a roadmap,” said Paolo A. Gargini, IEEE Fellow and Chairman of IRDS. “As a team, we are laying the foundation to identify challenges and recommendations on possible solutions to the industry’s current limitations defined by Moore’s Law. With the launch of the nine white papers on our new website, the IRDS roadmap sets the path for the industry benefiting from all fresh levels of processing power, energy efficiency, and technologies yet to be discovered.”

“The IRDS has taken a significant step in creating the industry roadmap by publishing nine technical white papers,” said IEEE Fellow Elie Track, 2011-2014 President, IEEE Council on Superconductivity; Co-chair, IEEE RC; and CEO of nVizix. “Through the public availability of these white papers, we’re inviting computing professionals to participate in creating an innovative ecosystem that will set a new direction for the greater good of the industry. Today, I open an invitation to get involved with IEEE RC and the IRDS.”

The series of white papers delivers the starting framework of the IRDS roadmap—and through the sponsorship of IEEE RC—will inform the various roadmap teams in the broader task of mapping the devices’ and systems’ ecosystem:

“IEEE is the perfect place to foster the IRDS roadmap and fulfill what the computing industry has been searching for over the past decades,” said IEEE Fellow Thomas M. Conte, 2015 President, IEEE Computer Society; Co-chair, IEEE RC; and Professor, Schools of Computer Science, and Electrical and Computer Engineering, Georgia Institute of Technology. “In essence, we’re creating a new Moore’s Law. And we have so many next-generation computing solutions that could easily help us reach uncharted performance heights, including cryogenic computing, reversible computing, quantum computing, neuromorphic computing, superconducting computing, and others. And that’s why the IEEE RC Initiative exists: creating and maintaining a forum for the experts who will usher the industry beyond the Moore’s Law we know today.”

The IRDS leadership team hosted a winter workshop and kick-off meeting at the Georgia Institute of Technology on 1-2 December 2016. Key discoveries from the workshop included the international focus teams’ plans and focus topics for the 2017 roadmap, top-level needs and challenges, and linkages among the teams. Additionally, the IRDS leadership invited presentations from the European and Japanese roadmap initiatives. This resulted in the 2017 IRDS global membership expanding to include team members from the “NanoElectronics Roadmap for Europe: Identification and Dissemination” (NEREID) sponsored by the European Semiconductor Industry Association (ESIA), and the “Systems and Design Roadmap of Japan” (SDRJ) sponsored by the Japan Society of Applied Physics (JSAP).

The IRDS team and its supporters will convene 1-3 April 2017 in Monterey, California, for the Spring IRDS Workshop, which is part of the 2017 IEEE International Reliability Physics Symposium (IRPS). The team will meet again for the Fall IRDS Conference—in partnership with the 2017 IEEE International Conference on Rebooting Computing (ICRC)—scheduled for 6-7 November 2017 in Washington, D.C. More information on both events can be found here: http://irds.ieee.org/events.

IEEE RC is a program of IEEE Future Directions, designed to develop and share educational tools, events, and content for emerging technologies.

IEEE-SA’s IC Program helps incubate new standards and related products and services, by facilitating collaboration among organizations and individuals as they hone and refine their thinking on rapidly changing technologies.

A coalition of leaders from the global tech, defense, and aerospace industries, led by the Semiconductor Industry Association (SIA) and Semiconductor Research Corporation (SRC), today released a report identifying the key areas of scientific research needed to advance innovation in semiconductor technology and fulfill the promise of emerging technologies such as artificial intelligence (AI), the Internet of Things (IoT), and supercomputing. The report, titled Semiconductor Research Opportunities: An Industry Vision and Guide, also calls for robust government and industry investments in research to unlock new technologies beyond conventional, silicon-based semiconductors and to advance next-generation semiconductor manufacturing methods.

“Semiconductor technology is foundational to America’s innovation infrastructure and global technology leadership,” said John Neuffer, president and CEO of SIA, which represents U.S. leadership in semiconductor manufacturing, design, and research. “Our industry has pushed Moore’s Law to levels once unfathomable, enabling technologies that have driven economic growth and transformed society. Now, as it becomes increasingly challenging and costly to maintain the breakneck pace of putting more transistors on the same size of silicon real estate, industry, academia, and government must intensify research partnerships to explore new frontiers of semiconductor innovation and to foster the continued growth of emerging technologies. Taking swift action to implement the recommendations from the Vision report will help usher in a new era of semiconductor technology and keep America at the head of the class in technological advancement.”

Neuffer also noted concern in the tech, research, and academic communities about proposed cuts to basic scientific research outlined in the Trump Administration’s fiscal year 2018 budget blueprint. Basic scientific research funded through agencies such as the National Science Foundation (NSF), the National Institute of Standards and Technology (NIST), the Defense Advanced Research Projects Agency (DARPA), and the Department of Energy (DOE) Office of Science has yielded tremendous dividends, helping launch technologies that underpin America’s economic strength and global competiveness. The U.S. semiconductor industry invests about one-fifth of revenue each year in R&D – the highest share of any industry. Neuffer expressed the semiconductor industry’s readiness to work with the Administration and Congress to enact a budget that embraces the strategic importance of research investments to America’s continued economic and technological strength.

“Continued and predictable advancements in semiconductor technology have fueled the growth of many industries, including those historically based on mechanics such as automotive,” said Ken Hansen, president & CEO of SRC. “As the rate of dimensional scaling has slowed, the need to reinvigorate the investment in semiconductor research has become increasingly clear. Now is the time for industry, government, and academia to double down their resources and efforts to ensure the pace of renewal continues. Alternative strategies and techniques to the traditional scaling for performance are now being explored by SRC. Furthermore, with the support of SIA, SRC is building research programs that align with the Vision report, including complimentary technologies such as advanced packaging and communications. An infusion of funding is vital to expand the research breadth beyond the historical focus areas, enabling the industry to keep its promise of a continuous stream of products with improved performance at reduced cost. As industries look to future areas of growth and innovation, SIA and SRC are laying the groundwork for new discoveries through fundamental research.”

The Vision report is the culmination of work by a diverse group of industry experts and leaders, including chief technology officers at numerous leading semiconductor companies, who came together over a nine-month period in 2016-2017 to identify areas in which research is essential to progress. The report, which will be updated periodically moving forward, has active participation from the industry’s leading chip makers, fabless companies, IP providers, equipment and material suppliers, and research organizations. It will serve as a foundational guide for defining the semiconductor industry’s future research paths in 14 distinct but complimentary research areas. These areas, outlined in the Vision report, are as follows:

1. Advanced Devices, Materials, and Packaging2. Interconnect Technology and Architecture

3. Intelligent Memory and Storage

4. Power Management

5. Sensor and Communication Systems

6. Distributed Computing and Networking

7. Cognitive Computing

8. Bio-Influenced Computing and Storage9. Advanced Architectures and Algorithms

10. Security and Privacy

11. Design Tools, Methodologies, and Test

12. Next-Generation Manufacturing Paradigm

13. Environmental Health and Safety: Materials and Processes

14. Innovative Metrology and Characterization

 

IC Insights has raised its worldwide IC market growth forecast for 2017 to 11%—more than twice its original 5% outlook—based on data shown in the March Update to the 20th anniversary 2017 edition of The McClean Report. The revision was necessary due to a substantial upgrade to the 2017 growth rates forecast for the DRAM and NAND flash memory markets.

IC Insights currently expects DRAM sales to grow 39% and NAND flash sales to increase 25% this year, with upside potential from those forecasts.  DRAM market growth is expected to be driven almost entirely by a huge 37% increase in the DRAM average selling price (ASP), as compared to 2016, when the DRAM ASP dropped by 12%. Moreover, NAND flash ASPs are forecast to rebound and jump 22% this year after falling by 1% last year.

The DRAM market started 2017 the way it ended 2016—with strong gains in DRAM ASP.  In April 2016, the DRAM ASP was $2.41 but rapidly increased to $3.60 in January 2017, a 49% jump.  A pickup in DRAM demand from PC suppliers during the second half of 2016 caused a significant spike in the ASP of PC DRAM.  Currently, strengthening ASPs are also evident in the mobile DRAM market segment.

With total DRAM bit volume demand expected to increase by 30% this year and DRAM bit volume production capacity forecast to increase by 20%, IC Insights believes that quarterly DRAM ASPs could still surprise on the upside in 2017. Furthermore, DRAM output is also being slowed, at least temporarily, by the ongoing transition of DRAM production to ≤20nm feature sizes by the major DRAM producers this year.

At $57.3 billion, the DRAM market is forecast to be by far the largest IC product category in 2017, exceeding the expected MPU market for standard PCs and servers ($47.1 billion) by $10.2 billion this year.  Figure 1 shows that the DRAM market has been both a significant tailwind (i.e., positive influence) and headwind (i.e., negative influence) on total worldwide IC market growth in three out of the past four years.

Figure 1

Figure 1

Spurred by a 12% decline in the DRAM ASP in 2016, the DRAM market slumped 8% last year.  The DRAM segment became a headwind to worldwide IC market growth in 2016 instead of the tailwind it had been in 2013 and 2014. As shown, the DRAM market shaved two percentage points off of total IC industry growth last year.  In contrast, the DRAM segment is forecast to have a positive impact of four percentage points on total IC market growth this year. It is interesting to note that the total IC market growth rate forecast for 2017, when excluding the DRAM and NAND flash markets, would be only 4%, about one-third of the current worldwide IC market growth rate forecast including these memory devices.

The March Update to the 2017 edition of The McClean Report further describes IC Insights’ IC market forecast revision, updates its 2017-2021 semiconductor capital spending forecast, and shows the final 2016 top 10 OSAT company ranking.

Synopsys, Inc. (Nasdaq:  SNPS) today announced that its IC Validator physical verification product has been successfully used for signoff on more than 100 tapeouts at advanced FinFET nodes. These tapeouts were completed with process technologies from multiple foundries at 16nm, 14nm, 10nm and 7nm. IC Validator’s massively parallel scalability to more than 200 CPUs has proven a critical factor in its ability to deliver overnight run times for today’s highly complex technology rules and very large designs. Synopsys has cooperated closely with foundries for several years to ensure the uncompromising accuracy of IC Validator’s results. This dependable accuracy has been key to IC Validator’s growing list of successful adoptions by industry leaders in many markets ranging from top CPU and GPU design companies in the US to leading fabless SoC designers in Taiwan and Japan.

IC Validator, part of the Synopsys Galaxy Design Platform, is a comprehensive and highly scalable physical verification tool suite including DRC, LVS, programmable electrical rule checks (ERC), dummy fill and DFM enhancement. IC Validator is configured to meet the challenges of today’s extremely large designs by enabling 8 CPUs with a single license. It uses both multi-threading and distributed processing over multiple machines to provide scalability benefits that extend to more than 200 CPUs. IC Validator enables coding at higher levels of abstraction and is architected for near-linear scalability that maximizes utilization of mainstream hardware, using smart memory-aware load scheduling and balancing technologies.

IC Validator is a companion product to the IC Compiler II place-and-route system for In-Design physical verification. In-Design is enabled by the intelligent integration of IC Validator and IC Compiler II place-and-route, making it possible for engineers to perform independent signoff-quality analysis earlier, before the design is finalized and while correction can be automated. In-Design technology also enables new high-productivity functionality within the place-and-route environment, including automatic DRC repair, improved quality of timing results with timing-aware metal fill, and rapid ECO validation. In-Design physical verification eliminates expensive iterations with downstream analysis tools and maintains a convergent design flow to physical signoff.

“As manufacturing complexity is placing increased challenges on designers to deliver within schedule, it is extremely important that we continue to collaborate closely with leading foundries to deliver high-performance solutions,” said Bijan Kiani, vice president, product marketing, Design Group at Synopsys. “This milestone confirms our mature ecosystem strategy that has led to strong growth in IC Validator’s market share.”

ATTOPSEMI Technology, Ltd. today announced that it has joined GLOBALFOUNDRIES’ FDXcelerator Partner Program, to provide a scalable, non-volatile one-time programmable (OTP) memory IP to be compatible with GF’s 22FDX technology. ATTOPSEMI’s I-fuse OTP IP offers increased reliability, smaller cell size, low programming voltage/current, and high data security enabling customers and designers the ability to utilize an advanced OTP for harsh applications such as automotive, 3D IC, and IoT applications.

The opportunity for advanced OTP memory technology is greater than ever. As the volumes and technical demands increase for Internet of Things (IoT), processing performance grows and memory intensive applications advance, ATTOPSEMI’s I-fuse fills the need. Consumer, communications, automotive and wireless markets require smaller sizing, ease of programmability and high levels of reliability. With its patent-proven structure, the I-fuse can guarantee zero-program defect giving customers the needed knowledge of reliability and execution.

“ATTOPSEMI’s new offering should benefit our 22FDX customers in all the key market segments we address, especially for IoT and processor intensive applications,” said Alain Mutricy, senior vice president of product management at GF. “Their commitment continues to demonstrate strong industry interest in GF’s FDXcelerator program and the 22FDX value proposition.”

“We are excited to expand our engagements with GF and believe that our technology will help their customers deliver the functionality the market has been asking for,” said Chung Shine, Chairman, ATTOPSEMI. “We believe that our development has given us the ability to generate a smaller cell size and more reliability than our competitors along with a very scalable solution.”

ATTOPSEMI’s I-fuse is a fuse-based OTP technology that offers up to 100x reliability, 1/100 the cell size, and 1/10th the program current than traditional e-fuse technologies. Highlights of the I-fuse include:

  • Limited program current below a catastrophic breaking point
  • Use of junction diode, instead of MOS, as a program selector in an OTP cell
  • Smaller cell improving program efficiency enabling program current reduction