Category Archives: 3D Integration

In microelectronic devices, the bandgap is a major factor determining the electrical conductivity of the underlying materials. Substances with large bandgaps are generally insulators that do not conduct electricity well, and those with smaller bandgaps are semiconductors. A more recent class of semiconductors with ultrawide bandgaps (UWB) are capable of operating at much higher temperatures and powers than conventional small-bandgap silicon-based chips made with mature bandgap materials like silicon carbide (SiC) and gallium nitride (GaN).

In the Journal of Applied Physics, from AIP Publishing, researchers at the University of Florida, the U.S. Naval Research Laboratory and Korea University provide a detailed perspective on the properties, capabilities, current limitations and future developments for one of the most promising UWB compounds, gallium oxide (Ga2O3).

Gallium oxide possesses an extremely wide bandgap of 4.8 electron volts (eV) that dwarfs silicon’s 1.1 eV and exceeds the 3.3 eV exhibited by SiC and GaN. The difference gives Ga2O3 the ability to withstand a larger electric field than silicon, SiC and GaN can without breaking down. Furthermore, Ga2O3 handles the same amount of voltage over a shorter distance. This makes it invaluable for producing smaller, more efficient high-power transistors.

“Gallium oxide offers semiconductor manufacturers a highly applicable substrate for microelectronic devices,” said Stephen Pearton, professor of materials science and engineering at the University of Florida and an author on the paper. “The compound appears ideal for use in power distribution systems that charge electric cars or converters that move electricity into the power grid from alternative energy sources such as wind turbines.”

Pearton and his colleagues also looked at the potential for Ga2O3 as a base for metal-oxide-semiconductor field-effect transistors, better known as MOSFETs. “Traditionally, these tiny electronic switches are made from silicon for use in laptops, smart phones and other electronics,” Pearton said. “For systems like electric car charging stations, we need MOSFETs that can operate at higher power levels than silicon-based devices and that’s where gallium oxide might be the solution.”

To achieve these advanced MOSFETs, the authors determined that improved gate dielectrics are needed, along with thermal management approaches that will more effectively extract heat from the devices. Pearton concluded that Ga2O3 will not replace SiC and GaN as the as the next primary semiconductor materials after silicon, but more likely will play a role in extending the range of powers and voltages accessible to ultrawide bandgap systems.

“The most promising application might be as high-voltage rectifiers in power conditioning and distribution systems such as electric cars and photovoltaic solar systems,” he said.

Lattice Semiconductor Corporation (NASDAQ: LSCC), a provider of customizable smart connectivity solutions, announced the appointment of Glenn O’Rourke as the Company’s Corporate Vice President, Global Operations, effective immediately. Mr. O’Rourke brings extensive business and technical experience, and expertise in supplier management, technology, product quality, and cost optimization to his new role. Prior to Lattice, Mr. O’Rourke was Corporate Vice President of Supplier Management, Technology & Product Cost Center at Xilinx, Inc.

Jim Anderson, President and Chief Executive Officer, said, “We are excited to welcome Glenn O’Rourke to Lattice’s leadership team, as we continue to attract key talent to our team. Glenn’s deep understanding of the FPGA industry and all facets from strategic planning through manufacturing and quality make him a perfect fit as we work to better optimize Lattice’s operations to support our strategic goals and customers’ multi-year product roadmaps.”

Mr. O’Rourke said, “I am excited to be part of Lattice’s leadership team. Having worked in the FPGA industry for many years I know the strength of the Company’s FPGA portfolio, global customer base and talented employees. I look forward to leveraging my expertise to help the Company enhance the capability, efficiency and profitability of its operations to enable exceptional growth.”

Glenn O’Rourke brings to the role 30 years of FPGA technology and semiconductor industry experience. Over the last 15 years, he has been responsible for Xilinx Inc.’s supplier strategy, management and sourcing; foundry, package, assembly and reliability engineering; and product cost center and gross margin. He most recently served as Corporate Vice President of Supplier Management, Technology and Product Cost Center at Xilinx, Inc. He was previously Vice President of Technology, Product Quality and Reliability for all Xilinx processes and products, after serving as Senior Director of Product Development Engineering. Earlier in his career Mr. O’Rourke was Senior Group Manager Product and Test Engineering at Lattice Semiconductor, and was a Product Development Manager / Program Manager at STMicroelectronics. He holds a Bachelor of Science in Electrical Engineering from Mississippi State University.

Synopsys, Inc. (Nasdaq: SNPS) announced today another milestone in its longstanding partnership with imec, a research and innovation hub in nanoelectronics and digital technologies, with the successful completion of the first comprehensive sub-3 nanometer (nm) parasitic variation modeling and delay sensitivity study of complementary FET (CFET) architectures. With the potential to significantly reduce area versus traditional FinFETs, CFET is a promising option to maintain area scaling beyond 3nm technology.

In 3-nm and 2-nm process technologies, the magnitude of variation increases significantly for middle of line (MOL) parameters, as well as interconnect, due to high resistance of metal lines, vias, and surface scattering. Therefore, modeling parasitic variation and sensitivity is a critical factor in bringing CFET to mainstream production.

Prediction at early stages of process development will allow foundries to create more robust and variation-tolerant transistors, standard cells, and methodologies for metal interconnect. Using the QuickCap® NX 3D field solver, in a close collaboration between Synopsys R&D and imec research teams, allowed for fast and accurate modeling of parasitics for a variety of device architectures and to identify the most critical device dimensions and properties. This allowed the optimization of CFET devices for better power/performance trade-offs. As part of a comprehensive set of tools that includes Raphael™ TCAD extraction to StarRC™ parasitic extraction for the largest system-on-chips (SoCs), QuickCap NX effectively helps process engineers understand the sensitivity of circuit performance to variations in process parameters and improves modeling accuracy by establishing golden reference values.

“This work has allowed us to accurately model and analyze cell and interconnect variation at advanced processes and architectures, such as Complementary FET,” said Anda Mocuta, director, Technology Solutions and Enablement at imec. “Our collaboration with Synopsys continues a legacy of successful collaborations that enable us to search for technological breakthroughs below 3 nanometers. The capabilities of Synopsys tools, such as QuickCap NX, have been key to our joint research on variability.”

“Imec is at the forefront of research into semiconductor technology. Our collaboration with imec to develop variation-aware solutions down to 2 nanometer processes will benefit the entire semiconductor industry,” said Antun Domic, chief technology officer at Synopsys. “Utilizing the flexibility of Synopsys’ QuickCap NX 3D parasitic extraction interface, engineers can better target and significantly reduce the number of trials needed to optimize circuit performance in the presence of process variation and reduce circuit sensitivity. This significantly reduces the overall turnaround time for device and circuit optimization.”

Leti, a research institute at CEA Tech, has reported breakthroughs in six 3D-sequential-integration process steps that previously were considered showstoppers in terms of manufacturability, reliability, performance or cost.

CoolCubeTM, CEA-Leti’s 3D monolithic or 3D sequential CMOS technology allows vertically stacking several layers of devices with a unique connecting-via density above tens of million/mm2. This MoreMoore technology decreases dice area by a factor of two, while providing a 26 percent gain in power. The wire-length reduction enabled by CoolCubeTM also improves yield and lowers costs. In addition to power savings, this true 3D integration opens diversification perspectives thanks to more integration of functions. From a performance optimization and manufacturing-enablement perspective, processing the top layer in a front end of line (FEOL) environment with a restricted thermal budget requires process modules optimization.

CEA-Leti’s recent 3D sequential integration results were presented Dec. 3 at IEDM 2018 in the paper, “Breakthroughs in 3D Sequential Integration”. The breakthroughs are:

  • Low-resistance poly-Si gate for the top field-effect transistors (FETs)
  • Full LT RSD (low temperature raised source and drain) epitaxy, including surface preparation
  • Stable bonding above ultra low-k (ULK)
  • Stability of intermediate back end of line (iBEOL) between tiers with standard ULK/Cu technology
  • Efficient contamination containment for wafers with Cu/ULK iBEOL, enabling their re-introduction in front end of line (FEOL) for top FET processing, and
  • Smart CutTM process above a CMOS wafer.

 

To obtain high-performance top FETs, low gate access resistance was achieved using UV nano-second laser recrystallization of in-situ doped amorphous silicon. Full 500°C selective silicon-epitaxy process was demonstrated with an advanced LT surface preparation and a combination of dry-and-wet etch preparation.  Epitaxial growth was demonstrated with the cyclic use of a new silicon precursor and dichlorine Cl2 etching. At the same time, the project paved the way to manufacturability of 3D sequential integration including iBEOL with standard ULK and Cu-metal lines.

A bevel-edge contamination containment strategy comprised of three steps (bevel etch, decontamination, encapsulation) enabled reintroducing wafers in an FEOL environment following the BEOL process. In addition, the project also demonstrated for the first time the stability of line-to-line breakdown voltage for interconnections submitted to 500°C. The work also demonstrated a Smart CutTM transfer of a crystalline silicon layer on a processed bottom level of FD-SOI CMOS devices, as an alternative to the SOI bonding-and-etch back process scheme for top channel fabrication.

Researchers from Intel Corp. and the University of California, Berkeley, are looking beyond current transistor technology and preparing the way for a new type of memory and logic circuit that could someday be in every computer on the planet.

In a paper appearing online Dec. 3 in advance of publication in the journal Nature, the researchers propose a way to turn relatively new types of materials, multiferroics and topological materials, into logic and memory devices that will be 10 to 100 times more energy-efficient than foreseeable improvements to current microprocessors, which are based on CMOS (complementary metal-oxide-semiconductor).

Single crystals of the multiferroic material bismuth-iron-oxide. The bismuth atoms (blue) form a cubic lattice with oxygen atoms (yellow) at each face of the cube and an iron atom (gray) near the center. The somewhat off-center iron interacts with the oxygen to form an electric dipole (P), which is coupled to the magnetic spins of the atoms (M) so that flipping the dipole with an electric field (E) also flips the magnetic moment. The collective magnetic spins of the atoms in the material encode the binary bits 0 and 1, and allow for information storage and logic operations. Credit: Ramamoorthy Ramesh lab, UC Berkeley

The magneto-electric spin-orbit or MESO devices will also pack five times more logic operations into the same space than CMOS, continuing the trend toward more computations per unit area, a central tenet of Moore’s Law.

The new devices will boost technologies that require intense computing power with low energy use, specifically highly automated, self-driving cars and drones, both of which require ever increasing numbers of computer operations per second.

“As CMOS develops into its maturity, we will basically have very powerful technology options that see us through. In some ways, this could continue computing improvements for another whole generation of people,” said lead author Sasikanth Manipatruni, who leads hardware development for the MESO project at Intel’s Components Research group in Hillsboro, Oregon. MESO was invented by Intel scientists, and Manipatruni designed the first MESO device.

Transistor technology, invented 70 years ago, is used today in everything from cellphones and appliances to cars and supercomputers. Transistors shuffle electrons around inside a semiconductor and store them as binary bits 0 and 1.

In the new MESO devices, the binary bits are the up-and-down magnetic spin states in a multiferroic, a material first created in 2001 by Ramamoorthy Ramesh, a UC Berkeley professor of materials science and engineering and of physics and a senior author of the paper.

“The discovery was that there are materials where you can apply a voltage and change the magnetic order of the multiferroic,” said Ramesh, who is also a faculty scientist at Lawrence Berkeley National Laboratory. “But to me, ‘What would we do with these multiferroics?’ was always a big question. MESO bridges that gap and provides one pathway for computing to evolve”

In the Nature paper, the researchers report that they have reduced the voltage needed for multiferroic magneto-electric switching from 3 volts to 500 millivolts, and predict that it should be possible to reduce this to 100 millivolts: one-fifth to one-tenth that required by CMOS transistors in use today. Lower voltage means lower energy use: the total energy to switch a bit from 1 to 0 would be one-tenth to one-thirtieth of the energy required by CMOS.

“A number of critical techniques need to be developed to allow these new types of computing devices and architectures,” said Manipatruni, who combined the functions of magneto-electrics and spin-orbit materials to propose MESO. “We are trying to trigger a wave of innovation in industry and academia on what the next transistor-like option should look like.”

Internet of things and AI

The need for more energy-efficient computers is urgent. The Department of Energy projects that, with the computer chip industry expected to expand to several trillion dollars in the next few decades, energy use by computers could skyrocket from 3 percent of all U.S. energy consumption today to 20 percent, nearly as much as today’s transportation sector. Without more energy-efficient transistors, the incorporation of computers into everything – the so-called internet of things – would be hampered. And without new science and technology, Ramesh said, America’s lead in making computer chips could be upstaged by semiconductor manufacturers in other countries.

“Because of machine learning, artificial intelligence and IOT, the future home, the future car, the future manufacturing capability is going to look very different,” said Ramesh, who until recently was the associate director for Energy Technologies at Berkeley Lab. “If we use existing technologies and make no more discoveries, the energy consumption is going to be large. We need new science-based breakthroughs.”

Paper co-author Ian Young, a UC Berkeley Ph.D., started a group at Intel eight years ago, along with Manipatruni and Dmitri Nikonov, to investigate alternatives to transistors, and five years ago they began focusing on multiferroics and spin-orbit materials, so-called “topological” materials with unique quantum properties.

“Our analysis brought us to this type of material, magneto-electrics, and all roads led to Ramesh,” said Manipatruni.

Multiferroics and spin-orbit materials

Multiferroics are materials whose atoms exhibit more than one “collective state.” In ferromagnets, for example, the magnetic moments of all the iron atoms in the material are aligned to generate a permanent magnet. In ferroelectric materials, on the other hand, the positive and negative charges of atoms are offset, creating electric dipoles that align throughout the material and create a permanent electric moment.

MESO is based on a multiferroic material consisting of bismuth, iron and oxygen (BiFeO3) that is both magnetic and ferroelectric. Its key advantage, Ramesh said, is that these two states – magnetic and ferroelectric – are linked or coupled, so that changing one affects the other. By manipulating the electric field, you can change the magnetic state, which is critical to MESO.

The key breakthrough came with the rapid development of topological materials with spin-orbit effect, which allow for the state of the multiferroic to be read out efficiently. In MESO devices, an electric field alters or flips the dipole electric field throughout the material, which alters or flips the electron spins that generate the magnetic field. This capability comes from spin-orbit coupling, a quantum effect in materials, which produces a current determined by electron spin direction.

In another paper that appeared earlier this month in Science Advances, UC Berkeley and Intel experimentally demonstrated voltage-controlled magnetic switching using the magneto-electric material bismuth-iron-oxide (BiFeO3), a key requirement for MESO.

“We are looking for revolutionary and not evolutionary approaches for computing in the beyond-CMOS era,” Young said. “MESO is built around low-voltage interconnects and low-voltage magneto-electrics, and brings innovation in quantum materials to computing.”

MagnaChip Semiconductor Corporation (“MagnaChip”) (NYSE: MX), a designer and manufacturer of analog and mixed-signal semiconductor platform solutions, today announced that volume production has commenced for an IGBT product for power module targeted to high-voltage industrial applications. IGBT is one of a MagnaChip family of Power standard products called Insulated Gate Bipolar Transistors.

The new IGBT P-series (“MBW100T120PHF”) has both high current and high voltage capabilities of 1200V and 100A, and has achieved a low saturation voltage Vce(sat) of 1.71V and low switching losses by using Field-Stop Trench technology. MBW100T120PHF allows designers to operate devices at an improved switching frequency, which enables reducing the size and cost of capacitors and inductive devices in circuits.

To product designers, this translates into high power density, small size and low material cost of products. MBW100T120PHF is operable up to four times the rated current, and with a wide SOA (Safe Operating Area) well-suited for industrial applications which require high power. In addition, by optimizing the resistance embedded inside the chip, MBW100T120PHF enables a parallel structure design, which allows multiple chips to operate simultaneously.

MBW100T120PHF is expected to improve overall system stability and energy efficiency of applications by reducing the power loss from DC-AC power conversions for high-voltage industrial applications, such as 10kW+ 3-phase motor and photovoltaic inverter systems.

“We are pleased to launch our newest IGBT P-series product for industrial power modules, with high-voltage and high-current capabilities of 1200V and 100A,” said YJ Kim, CEO of MagnaChip. “The introduction of this IGBT P-series product will further expand our IGBT power product portfolio and enhance our reputations as a market leader of high-voltage power standard products.”

Researchers at RMIT University have engineered a new type of transistor, the building block for all electronics. Instead of sending electrical currents through silicon, these transistors send electrons through narrow air gaps, where they can travel unimpeded as if in space.

The nano-gap transistors operating in air. As gaps become smaller than the mean-free path of electrons in air, there is ballistic electron transport. Credit: RMIT University

The device unveiled in material sciences journal Nano Letters, eliminates the use of any semiconductor at all, making it faster and less prone to heating up.

Lead author and PhD candidate in RMIT’s Functional Materials and Microsystems Research Group, Ms Shruti Nirantar, said this promising proof-of-concept design for nanochips as a combination of metal and air gaps could revolutionise electronics.

“Every computer and phone has millions to billions of electronic transistors made from silicon, but this technology is reaching its physical limits where the silicon atoms get in the way of the current flow, limiting speed and causing heat,” Nirantar said.

“Our air channel transistor technology has the current flowing through air, so there are no collisions to slow it down and no resistance in the material to produce heat.”

The power of computer chips – or number of transistors squeezed onto a silicon chip – has increased on a predictable path for decades, roughly doubling every two years. But this rate of progress, known as Moore’s Law, has slowed in recent years as engineers struggle to make transistor parts, which are already smaller than the tiniest viruses, smaller still.

Nirantar says their research is a promising way forward for nano electronics in response to the limitation of silicon-based electronics.

“This technology simply takes a different pathway to the miniaturisation of a transistor in an effort to uphold Moore’s Law for several more decades,” Shruti said.

Research team leader Associate Professor Sharath Sriram said the design solved a major flaw in traditional solid channel transistors – they are packed with atoms – which meant electrons passing through them collided, slowed down and wasted energy as heat.

“Imagine walking on a densely crowded street in an effort to get from point A to B. The crowd slows your progress and drains your energy,” Sriram said.

“Travelling in a vacuum on the other hand is like an empty highway where you can drive faster with higher energy efficiency.”

But while this concept is obvious, vacuum packaging solutions around transistors to make them faster would also make them much bigger, so are not viable.

“We address this by creating a nanoscale gap between two metal points. The gap is only a few tens of nanometers, or 50,000 times smaller than the width of a human hair, but it’s enough to fool electrons into thinking that they are travelling through a vacuum and re-create a virtual outer-space for electrons within the nanoscale air gap,” he said.

The nanoscale device is designed to be compatible with modern industry fabrication and development processes. It also has applications in space – both as electronics resistant to radiation and to use electron emission for steering and positioning ‘nano-satellites’.

“This is a step towards an exciting technology which aims to create something out of nothing to significantly increase speed of electronics and maintain pace of rapid technological progress,” Sriram said.

MIRPHAB, a European Commission project to create a pilot line to fabricate mid-infrared (MIR) sensors by 2020, is accepting proposals from companies that want to develop and prototype new MIR devices that operate in gas-and-liquid media.

The project produces MIR photonic devices via assembled and/or packaged devices for laser-based, analytical MIR sensors, and expert design for sensor components that are fabricated on the pilot line. The platform is organized so that development of novel sensors and sensing systems is based on MIR integrated optic components and modules already incorporated in MIRPHAB’s portfolio.

The aim of the MIRPHAB pilot line is to provide each customer with a unique chemical spectroscopic system by combining sources, photonic circuits and detectors in standard packaging.

“European industry requires more efficient control processes to gain greater productivity and operational efficiency, and this project will deliver the devices required to improve those processes,” said CEA-Leti’s Sergio Nicoletti, who is coordinating the project. “MIRPHAB also will develop new sensor technology that provides novel analytical tools for companies to help improve people’s overall quality of life via environmental monitoring (e.g to measure VOC), food quality control (e.g. food spoilage or  adulteration ) and fast clinical diagnoses (e.g. provide cancer cells images). These are some of the areas where MIR sensors will play an increasingly significant role.”

In addition to providing device-design services for customers, the MIRPHAB team will help them develop sound business cases and strong business plans to commercialize their new devices. Potential cost-and-performance breakthroughs will be shown for reliable MIR sensing products based on building blocks provided by MIRPHAB. MIRPHAB also will be a sustainable source of key components for new and highly competitive MIR sensors, and will support their successful market introduction, while strengthening the competitiveness of European industry.

Mid-infrared light interacts strongly with molecular vibrations as each molecule gives a unique absorption spectrum that provides a simple solution for sensing. The sensors’ reduced size and flexible design make them ideal candidates for integration into already existing equipment for in-line/on-line detection.

The MIRPHAB team will host a booth, #ZB24, at the Sensors USA event in Santa Clara, Calif., Nov. 14-15, 2018.

MIRPHAB is funded by the Photonics Public Private Partnership. The project brings together 18 leading European organizations and is coordinated by CEA-Leti. For more information visit the project’s website.

Micron Technology, Inc., (Nasdaq: MU) today announced at Electronica 2018 that it will collaborate with the BMW Group to further advance the development of automotive memory solutions used in vehicles. Memory and storage are key components in accelerating the intelligence and user experience of next-generation systems in vehicles, including in-cabin infotainment as well as advanced driver-assistance systems (ADAS) technology, which together play an important role in making self-driving autonomous cars a reality.

Micron and the BMW Group will intensify their existing efforts toward testing and development of automotive memory solutions at Micron’s state-of-the-art lab in Munich, Germany. Using the Test Automation Framework of the BMW Group as a car emulator platform, the two companies will work together to define and validate memory and storage solutions for next-generation platforms. The collaborative effort will leverage Micron’s memory and storage technology expertise, along with its broad portfolio of DRAM, NAND, and NOR technologies, including LPDRAM, e.MMC, UFS and SSD storage solutions.

As a proven memory partner for automotive manufacturers, Micron recognizes the importance of validating and testing new automotive memory technologies for robustness and reliability before releasing them into the market. Micron’s customer lab expertise in developing innovative automotive memory technologies will enable the BMW Group to raise the quality of the driving experience in automobiles of the future.

“The incorporation of new features and capabilities in advanced in-vehicle infotainment (IVI) and ADAS, such as voice recognition, hand gesturing and image recognition, are driving an explosive growth in both volatile and nonvolatile memory embedded in vehicles, accelerating intelligence at the edge,” said Giorgio Scuro, vice president of Micron’s automotive division. “Micron has a long-standing record working with automotive industry partners, and this joint initiative with the BMW Group is a testament to our expertise in bringing innovative automotive memory technologies to market.”

As a leading memory partner with more than 25 years of experience, Micron provides advanced automotive memory solutions that meet stringent quality, reliability and compliance requirements. Micron’s broad portfolio of volatile and nonvolatile memory products are optimized for automotive and supported by a formal product longevity program.

GLOBALFOUNDRIES and indie Semiconductor today announced the release of a new generation of customized microcontrollers on GF’s 55nm Low Power Extended (55LPx) automotive-qualified platform, which includes embedded non-volatile memory (SuperFlash®) technology. indie Semiconductor’s new Nigel products are based on ARM Cortex-M4 microcontroller cores, capable of supporting advanced functionalities in IoT, medical and automotive markets. indie Semi is already shipping products, manufactured on GF’s 55LPx process, to automotive customers in volume.

indie’s custom microcontrollers integrate in a single device mixed-signal functionality for sensing, processing, controlling and communicating. GF’s 55LPx platform, with SST’s SuperFlash® memory technology, enables the use of high-density memory and high-performance processing combined with mixed-signal functions in indie’s Nigel M4 controllers, delivering a highly integrated automotive solution at 55nm node.

“indie’s Nigel controller is designed to support high performance computing for automotive system architectures,” said Paul Hollingworth, executive vice president of sales and marketing at indie Semiconductor. “As automotive system requirements get more complex, our customers need solutions to perform complex processing while combining multiple functions into a single chip to minimize size and weight. We chose GF’s automotive-qualified 55LPx platform for its combination of density, performance and cost.”

“GF is pleased to be working with indie Semiconductor, a leader in state-of-the-art SoC technology,” said Rajesh Nair, vice president of mainstream offering management at GF. “indie Semiconductor joins our rapidly growing client base for GF’s 55LPx platform, which offers a combination of superior low-power logic, embedded non-volatile memory, extensive IP, and superior reliability for consumer, industrial and automotive grade 1 applications.”

The 55LPx RF-enabled platform provides a fast path-to-product solution that includes silicon-qualified RF IP and Silicon Storage Technology’s (SST) highly reliable embedded SuperFlash® memory. The platform is in volume production on GF’s 300mm line in Singapore. In addition to Nigel, indie Semiconductor is currently developing several products on the technology, many of which are for automotive applications.

Process design kits and an extensive offering of silicon proven IP are available now. For more information on GF’s mainstream CMOS solutions, contact your GF sales representative or go to globalfoundries.com.