Category Archives: 3D Integration

Datacenters with few other emerging applications will become a multibillion dollar market for silicon photonics by 2025. Transporting high level of data with existing technologies will soon reach its limit and photons will continue replacing step by step electrons throughout networks. Growing investments made by VCs have been identified by Yole Développements’ analysts and few startups have been created in this sector. All these indicators confirm the trend: silicon photonic technologies have reached the tipping point that precedes massive growth.

silicon photonics illustration

Yole Développement (Yole), the “More than Moore” market research and strategy consulting company releases this month the technology & market analysis titled Silicon Photonics for datacenters and other applications. Both experts Dr Eric Mounier, Sr Technnology & Market Analyst at Yole and Jean-Louis Malinge, former CEO of Kotura, now at ARCH Venture Partners combined their knowledge of the silicon photonic industry to perform a deep added-value analysis. Under this report, they examine the current status and future challenges for silicon photonics and data centers application. They detail for all applications, silicon photonic benefits as well as a comprehensive analysis of the industrial supply chain with player’s status.

What is the status of silicon photonic technologies? Could we already speak about commercial solutions? What is the market size today? What about tomorrow? How high are the current investments? Yole’s analysts offer you a snapshot of the story.

The silicon photonics market is still modest with estimated sales below US$40 million in 2015 and very few companies actually shipping products in the open market: Mellanox, Cisco, Luxtera, Intel, STMicroelectronics, Acacia and Molex are part of these leading players.

Silicon photonics has been under development for years. However now, this technology is being pushed hard by large webcom companies like Facebook and Microsoft. “Silicon photonics has reached the tipping point that precedes massive growth,” comments Dr Eric Mounier from Yole. “Indeed we estimate, the packaged silicon photonics transceiver market will be worth US$6 billion in 10 years.”

Silicon photonics is an exciting technology mixing optics, CMOS technology and advanced packaging. This combination benefits from semiconductor wafer manufacturing scalability to reduce costs.

“Silicon photonics offers silicon technology advantages including higher integration, more functionalities embedded with lower power consumption and better reliability compared to legacy optics”, analyzes Jean-Louis Malinge.

In 2020 and more, silicon photonic chips will far exceed copper cabling capabilities. Such solutions will be so deployed in high-speed signal transmission systems. In 2025 and more, the technology will be more and more used in processing such as interconnecting multiple cores with processor chips. Indeed, according to Yole’s analysts, the chip market value should score US$1,5 billion in 2025 at chip level (Estimated to be less than US$40 million in 2015). Step by step photons get closer to the chips!

Data centers are clearly the best opportunity for silicon photonics technology today. And there are also many other applications that silicon photonics can enable. These include high performance computers, telecommunications, sensors, life science, quantum computers and other high-end applications.

Two applications are particularly interesting as silicon photonics can push the integration of optical functions and miniaturization further to achieve successful products. Those applications are lidars for autonomous cars and biochemical and chemical sensors.

Lidars are costly and bulky instruments which make their integration in a car challenging. Within a promising ADAS market expected to reach US$3,9 billion in 2017 silicon photonic-based lidar will play a key role. Indeed silicon photonics allow lidar without moving elements, which can experience issues in a harsh car environment. Last august, MIT’s Photonic Microsystems Group announced a successful DARPA project using silicon photonics for lidar-on-a-chip with steerable transmitting and receiving phased arrays and on-chip Ge photodetectors.

Biochemical and gas sensors are not new, and several applications have existed for a while. Day by day, the interest in gas sensing is gaining importance due to the emergence of promising new large volume portable applications. Integration of biochemical or gas sensors into smartphones or wearables is currently on the roadmap of many companies but size, cost and sensitivity are still issues. To push optical gas sensor miniaturization further, some companies are already considering silicon photonics as an integration platform for their devices.

These non-data center applications will be about US$300 million in 2025, detail Yole’s analysts in the silicon photonics report.

Lattice Semiconductor Corporation (NASDAQ:LSCC) and Canyon Bridge Capital Partners, Inc. today announced that Lattice and Canyon Bridge Acquisition Company, Inc., an affiliate of Canyon Bridge, have signed a definitive agreement under which Canyon Bridge will acquire all outstanding shares of Lattice for approximately $1.3 billion inclusive of Lattice’s net debt, or $8.30 per share in cash. This represents a 30% premium to Lattice’s last trade price on November 2, 2016, the last trading day prior to announcement.

Darin G. Billerbeck, President and Chief Executive Officer of Lattice, commented, “We are pleased to announce the transaction today with Canyon Bridge, which will unlock tremendous value for shareholders. This transaction is the culmination of an extensive review process with our Board, financial and legal advisers, and it delivers certain and immediate cash value to shareholders while reducing our execution risk. We are excited to leverage Canyon Bridge’s resources and market connections as we enhance our focus on executing our long-term strategic plan of continued innovation. Importantly, we will operate as a standalone subsidiary after the acquisition and do not expect any changes in our operations or our unwavering commitment to continued innovation for our customers.”

Ray Bingham, Founding Partner, Canyon Bridge, noted, “Lattice’s low-power FPGA franchise, along with its video connectivity and wireless solutions, make it a compelling, strategic investment. We expect the Company will continue to leverage its existing customer relationships with major OEMs globally, while further broadening the role of its technology solutions and accelerating its strategic plans.”

Benjamin Chow, Founding Partner, Canyon Bridge, added, “Equally critical in our decision to partner with Lattice is the Company’s world-class management team and its dedicated, highly experienced employee base. Our long-term interests are aligned with Lattice’s employees and customers. We plan to build upon Lattice’s achievements and are excited to provide the resources necessary to help the Company achieve significant growth and long-term success.”

The transaction has been unanimously approved by both companies’ boards of directors and is expected to close in early 2017 subject to customary closing conditions, regulatory approvals and approval by Lattice’s shareholders. Lattice and Canyon Bridge are committed to proactive engagement with regulators to facilitate the government review process.

Upon the completion of the transaction, Lattice will be a standalone subsidiary of Canyon Bridge and Lattice’s senior management team will continue to lead the business from its current headquarters in Portland, OR.

Morgan Stanley & Co. LLC is serving as the sole financial adviser to Lattice and Skadden, Arps, Slate, Meagher & Flom LLP is serving as legal adviser. Lazard is serving as the financial adviser to Canyon Bridge and Jones Day is serving as legal adviser.

Leti, an institute of CEA Tech, and PYXALIS, a French SME specializing in high-performance image sensors, today announced a new technology that lowers readout noise for image sensors down to 0.5 electron noise and dramatically improves low-light image sensing capabilities.

The new technology, called Owly-eyed, is based on a patented electrical architecture of the pixel readout that can be integrated in image sensors. Designed to meet growing demand for more sensitive CMOS image sensors, it has been adapted for PYXALIS, which will offer it in its next-generation image sensors.

“In this common lab with PYXALIS, we’ve developed a low-noise image technology that provides state-of-the-art advanced imaging for next-generation applications in a wide range of markets and industries,” said Marie Semeria, Leti’s CEO. “This CMOS-based device, which can be adapted for multiple uses, is another strong example of how Leti’s broad technology innovations make our partners more competitive in their industries.”

“Leti’s Owly-eyed technology is a major improvement in low-noise imaging,” said PYXALIS CEO Philippe Rommeveaux. “Combined with our capacity to offer advanced sensors with high digital integration and high dynamic range, it will allow us to establish a new performance standard in image sensors that address the growing demand for low-light applications in the surveillance, biomedical, science, defense and aerospace markets.”

In the Owly-eyed technology demonstrator, a sub-0.5 e−rms temporal read noise has been achieved on a VGA format CMOS image sensor implemented in a standard CMOS process. The low-noise performance is achieved exclusively through circuit optimization without any process refinements.

Leti also is developing many other technologies for innovative sensors and image processing that perform in low-power and low-latency operating modes.

Leti will demonstrate the Owly-eyed technology and a set of advanced smart-image-processing solutions at Vision 2016, Nov. 8-10 in Stuttgart, Germany, inHall 1, booth H01. The PYXALIS team will be available in Hall 1, booth D41.

In 2015, more than US$1 billion was invested in China’s advanced packaging ecosystem, announces Yole Développement (Yole) in its report Status and Prospects for the Advanced Packaging Industry. And right now, more than 100 companies are involved in assembly & packaging activities in China. Almost all key global IDMs and OSATs have a packaging facility in China to take advantage of low costs.

But what are the strategies of these companies? How do they ensure their market positioning and their development in the Chinese advanced packaging industry? Is there a specific approach according to their business model?

advanced packaging china

“Global OSATs are working on their strategies to thwart challenges and exploit opportunities in China’s advanced packaging market,” details for example, Santosh Kumar, Senior, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing at Yole. And in parallel, Chinese players may acquire or invest in others with complimentary packaging technology/services/customers.

Status and Prospects for the Advanced Packaging Industry in China report presents the Chinese semiconductor market outlook as well as the advanced packaging ecosystem in China. This analysis details the global and local players as well as the Chinese backend equipment & materials suppliers. It also covers supply chain evolution, OSAT strategy and business opportunities for local and global players in China’s advanced packaging space. Some results will be presented by Santosh Kumar at the China International Semiconductor Executive Summit taking place from November 1 to 2, 2016 in Shanghai, China.

The advanced packaging market in China is reaching about US$2.5 billion in 2016. And Yole’s analysts expect an impressive 16% CAGR between 2016 and 2020, scoring US$4.6 billion at the end of this period. Under this imposing growth, advanced packaging companies are deploying complex strategies to ensure their business and develop their activities. For example, some companies collaborate with local IC design & foundries and invest in R&D and manufacturing capacity in China. Others invest in Chinese capital.

Technical innovation is also a priority for all China-based companies. Companies are investing a lot to secure important R&D activities and develop disruptive technologies. In parallel, advanced packaging players protect their IP and company’s core value. From a human resources point of view, they reserve key employees through incentives and educate employees to not release confidential information.

China’s advanced packaging industry took a giant leap when JCET acquired STATSChipPAC in 2015 for US$780 million. This deal propelled JCET into 4th place amongst OSAT companies. “JCET-STATS ChipPAC is clearly the game changer in China AP ecosystem,” comments Santosh Kumar from Yole. And he adds: “JCET-STATS ChipPAC results in operational, revenue & capex synergy”.
Other notable acquisitions are:

•  Huatian acquiring FCI
•  Nantong Fujitsu acquiring AMD backend facilities in China and Malaysia.

While Chinese OSATs and foundries are rapidly acquiring advanced packaging capabilities, the local equipment and materials supply chains are still far behind compared to global players, who still dominate the advanced packaging equipment and materials space.

Will this remain true over the next five years? Do global suppliers see China’s advanced packaging market as an opportunity or a threat from local supplier)? In Yole’s report’s equipment/materials section, the advanced packaging team addresses these questions as well as other issues.

The 62nd annual IEDM will be held in San Francisco December 3 – 7, 2016.

For more than six decades, the annual IEEE International Electron Devices Meeting (IEDM) has been the world’s largest and most influential forum for technologists to unveil breakthroughs in transistors and related micro/nanoelectronics devices.

That tradition continues this year with a few new twists, including a supplier exhibition and a later paper- submission deadline (August 10) of a final, four-page paper. Accepted papers will appear in the proceedings without any changes. This streamlined process will ensure that even as the pace of innovation in electronics quickens, IEDM remains the place to learn about the latest and most important developments.

The 62nd annual IEDM will be held in San Francisco December 3 – 7, 2016, beginning with a weekend program of 90-minute tutorials and all-day Short Courses taught by industry leaders and world experts in their respective technical disciplines. These weekend events will precede a technical program of some 220 papers and a rich offering of other events including thought-provoking plenary talks, spirited evening panels, special focus sessions on topics of greatinterest,IEEE awards and an event for entrepreneurs sponsored by IEDM and IEEE Women in Engineering.

“The industry is moving forward at an accelerated pace to match the increasing complexity of today’s world, and a later submission deadline enables us to shorten the time between when results are achieved in the lab and when they are presented at the IEDM,” said Dr. Martin Giles, IEDM 2016 Publicity Chair, Intel Fellow, and Director of Transistor Technology Variation in Intel’s Technology and Manufacturing Group.

Tibor Grasser, IEDM 2016 Exhibits Chair, IEEE Fellow and Head of the Institute for Microelectronics at TU Wien, added, “We have decided to have a supplier exhibition in conjunction with the technical program this year, as an added way to provide attendees with the knowledge and information they need to advance the state-of-the-art.”

Here are some of the noteworthy events that will take place at this year’s IEDM:

Special Focus Sessions

• Wearable Electronics and Internet of Things (IoT) – Wearable technology offers great promise for communica- tions, fitness tracking, health monitoring, speech therapy, elder care/assisted living and many other applications. This Special Focus Session has been organized to benchmark wearable electronics technologies, to address applications with comprehensive system demonstrations, and to learn indus- trial perspectives about the gaps, challenges and opportu- nities for wider uses of wearable and IoT technologies. Papers on flexible/stretchable electronics, MEMs, display devices, sensors, printed electronics, organic devices and 2-D material devices enabling wearables/IoT devices also will be featured.

• Quantum Computing – As traditional CMOS scaling enters the post-Moore’s Law era, quantum computing has emerged as a possible candidate for further device scaling because it exploits the laws of quantum physics and may make much more powerful computers possible. This Special Focus Session will explore relevant semiconductor-related fabri- cation issues and will brainstorm R&D directions for new materials, devices, circuits, and manufacturing approaches for the scalable integration of a large number of qubits with CMOS technology, operating at cryogenic temperatures for the realization of quantum computers.

• System-Level Impact of Power Devices – While there are forums that serve circuit experts for the exchange of ideas and the reporting of breakthroughs, there hasn’t been a suitable forum for bringing device and circuit experts together to consider impacts at the system level, even though that would be fruitful due to the interactions of circuits and devices. IEDM aims to serve as the forum for their dialogue, and so this Special Focus Session has been organized. Papers are expected to explore the system-level impact of power devices, and also to describe various types of power devices targeting the full range of power/power conversion applications such as hybrid vehicles, utility and grid control, computing/telecom power supplies, motor drives, and wireless power transfer.
• Ultra-High-Speed Electronics – There have been many advances and breakthroughs in ultra-high-speed electronics for communications, security and imaging applications, but technology gaps continue to prevent spectrum above milli- meter-wave frequencies from being fully used. This Special Focus Session has been organized to discuss, showcase and benchmark advanced ultra-high speed devices and circuits based on high-electron-mobility transistors (HEMTs), hetero- junction bipolar transistors (HBTs) and conventional CMOS devices; high-speed interconnect; antennas for ultra-high- speed systems; ultra-high-frequency oscillators; and to discuss other possible applications.

90-Minute Tutorials – Saturday, Dec. 3

A program of 90-minute tutorial sessions on emerging technologies will be presented by experts in the fields, to bridge the gap between textbook-level knowledge and leading-edge current research. Advance regis- tration is recommended.

• The Struggle to Keep Scaling BEOL, and What We Can Do Next, Dr. Rod Augur, Distinguished Member of the Technical Staff, GlobalFoundries – Looking ahead, it’s the interconnect that threatens further cost-effective scaling. The tutorial will cover challenges and trade-offs in back- end-of-the-line(BEOL)scaling,andwillevaluateemerging devices from a scaled-BEOL viewpoint.

• Electronic Circuits and Architectures for Neuro- morphic Computing Platforms, Prof. Giacomo Indiveri, Univ. of Zurich and ETH Zurich – This tutorial will cover the principles and origins of neuromorphic (i.e., brain-inspired) engineering, examples of neuromorphic circuits, how neural network architectures can be used to build large-scale multi-core neuromorphic processors, and some specific application areas well-suited for neuromorphic computing technologies.

• Physical Characterization of Advanced Devices, Prof. Robert Wallace, Univ. Texas at Dallas – This tutorial will cover the hardware, physics, and chemistry that enable modern physical characterization of novel electronic materials, and will explore how these techniques can shed light on electronic materials research and development, and on the resultant devices. In addition to introducing examples of novel electronic materials for device applications, example techniques discussed will include high-resolution electron microscopy, scanning tunneling microscopy and spectroscopy, dynamic x-ray photoelectron spectroscopy, and ion mass spectrometry. The detection limits of these techniques and how they relate to device behavior also will be discussed.

• Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation, Dr. Ben Kaczer, Principal Scientist, Imec – This tutorial will introduce the main degradation mechanisms occurring in present-day CMOS. The reliability of novel devices (SiGe, IIIV, gate-all-around nanowires, junctionless FETs, tunnel FETs), of deeply-scaled devices, and of circuits (e.g., “reliability-aware” designs) will be covered in detail. The tutorial will give attendees an overview and background in this area sufficient to allow them to follow and participate in any discussion on reliability in general, and on front-end- of-the-line (FEOL) reliability in particular.

• Spinelectronics: From Basic Phenomena to Magneto- resistive Memory (MRAM) Applications, Dr. Bernard Dieny, Chief Scientist, Spintec CEA — This tutorial will cover spintronics phenomena, magnetic tunnel junctions (growth, magnetic and transport properties), field-written MRAM (toggle and thermally assisted MRAM), STT-MRAM (principle and status of development), 3-terminal MRAM andinnovativearchitecturesthatbenefitfromthesehigh- endurance non-volatile memories.

• Technologies for IoT and Wearable Applications, Including Advances in Cost-Effective and Reliable Embedded Non-Volatile Memories, Dr. Ali Keshavarzi, Vice President of R&D, Cypress Semiconductor — This tutorial will coverarangeoftechnologyopportunitiesforIoTandwearable applications, including embedded non-volatile memories (eNVM), IPs and integrated solutions based on charge-trap memory technologies such as SONOS for low power (LP) and ultra-low-power (ULP) for advanced technology nodes. Technologies will be described for various integrated IoT, wearableandenergy-harvestingsystemsusingprogrammable systems-on-chips (SoCs) with digital and analog capabilities, along with low-energy Bluetooth radio, WiFi radio, solar cells, sensors, actuators, and power management ICs. Advanced small form-factor packaging technologies useful for system integration also will be described.

Short Courses – Sunday, Dec. 4

The Short Courses provide the opportunity to learn about important areas and developments, and to benefit from direct contact with world experts. Advance regis- tration is recommended.

1. Technology Options at the 5-Nanometer Node, organized by An Steegen and Dan Mocuta of Imec (Sr. Vice President of Technology Development/Director of Logic Device and Integration, respectively) – This course will describe the complex technological challenges at the 5nm node and explore innovative potential solutions. It begins with an in-depth discussion of patterning strategies being pursued to print critical features. Then, a pair of lectures will provide an overview of current transistor technologies and their relative strengths/ weaknesses in the context of various applications such as mobility, data centers and IoT. Strategies for effective mitigation of performance-limiting parasitic resistance and capacitance will be discussed, and advanced interconnect technologies including post- copper materials options for BEOL and MEOL appli- cations will be addressed. Lastly, metrology challenges for in-line and end-of-line process technologies will be discussed. The intent of the course is to provide a thorough understanding in process technology targets at the 5nm node and their potential solutions. Attendees will have the opportunity to learn about advanced technology options that are being actively pursued in the industry from leading technologists.

The course consists of lectures from six distinguished speakers:

• Nano Patterning Challenges at the 5nm Node, Akihisa Sekiguchi, VP & Deputy GM, SPE Marketing and Process Development Division, Tokyo Electron, Japan

• Novel Channel Materials for High-Performance and Low-Power CMOS, Nadine Collaert, Distinguished Member of the Technical Staff, imec, Belgium

• Transistor Options & Challenges for 5nm Technology, Aaron Thean, Professor of Electrical & Computer Engineering, National University of Singapore

• Low Resistance Contacts to Enable 5nm Node Technology: Patterning, Etch, Clean, Metallization and Device Performance, Reza Arghavani, Managing Director, Lam Research, USA

• Parasitic R and C Mitigation Options for BEOL and MOL in N5 Technology, Theodorus Standaert, Sr. Engineering Mgr., Manager, Process Integration, IBM, USA

• Metrology Challenges for 5nm Technology, Ofer Adan, Technologist and Global Product Manager, Member of the Technical Staff, Applied Materials, Israel

2. Design/Technology Enablers for Computing Applications, organized by John Chen, Vice President of Technology and Foundry Management, NVIDIA – This course will describe how various design techniques and process technologies can enable computing applications, beginning with the relative advantages and disadvantages of processors such as CPU, GPU and FPGA with regard to today’s high data demands. It then will cover how memory becomes a bottleneck, and will discuss various emerging memory technol- ogies to mitigate the problem. Because managing power dissipation has become critical, it also will offer a broad perspective on power efficiency in computing and how interconnect plays a pivotal role in both performance and energy efficiency. Finally, 2.5-D and 3-D advanced packaging technology is discussed for system integration.

The course consists of lectures from five distinguished speakers:

• The Rise of Massively Parallel Processing: Why the Demands of Big Data and Power Efficiency are Changing the Computing Landscape, Liam Madden, Corporate VP, Hardware & Systems Development, Xilinx, USA

• Breaking the Memory Bottleneck in Computing Applications with Emerging Memory Technologies: a Design and Technology Perspective, Gabriel Molas, PhD Engineer, Leti, France

• Power Management with Integrated Power Devices… and how GaN Changes the Story, Alberto Doronzo, Power System/Apps Engineer, Texas Instruments, USA

• Interconnect Challenges for Future Computing, William J. Dally, Chief Scientist and Sr. VP of Research, NVIDIA, and Stanford Professor, USA

• Advanced Packaging Technologies for System Integration, Douglas Yu, Sr. Director, TSMC, Taiwan

This article was originally posted on SemiMD.com and was featured in the October 2016 issue of Solid State Technology.

By Ed Korczynski, Sr. Technical Editor

3D-NAND chips are in production or pilot-line manufacturing at all major memory manufacturers, and they are expected to rapidly replace most 2D-NAND chips in most applications due to lower costs and greater reliability. Unlike 2D-NAND which was enabled by lithography, 3D-NAND is deposition and etch enabled. “With 3D-NAND you’re talking about 40nm devices, while the most advanced 2D-NAND is running out of steam due to the limited countable number of stored electrons-per-cell, and in terms of the repeatability due to parasitics between adjacent cells,” reminded Harmeet Singh, corporate vice president of Lam Research in an exclusive interview with SemiMD to discuss the company’s presentation at the Flash Memory Summit 2016.

“We’re in an era where deposition and etch uniquely define the customer roadmap,” said Singh,“and we are the leading supplier in 3D-NAND deposition and etch.” Though each NAND manufacturer has different terminology for their unique 3D variant, from a manufacturing process integration perspective they all share similar challenges in the following simplified process sequences:

1)    Deposition of 32-64 pairs of blanket “mold stack” thin-films,

2)    Word-line hole etch through all layers and selective fill of NAND cell materials, and

3)    Formation of “staircase” contacts to each cell layer.

Each of these unique process modules is needed to form the 3D arrays of NVM cells.

For the “mold stack” deposition of blanket alternating layers, it is vital for the blanket PECVD to be defect-free since any defects are mirrored and magnified in upper-layers. All layers must also be stress-free since the stress in each deposited layer accumulates as strain in the underlying silicon wafer, and with over 32 layers the additive strain can easily warp wafers so much that lithographic overlay mismatch induces significant yield loss. Controlled-stress backside thin-film depositions can also be used to balance the stress of front-side films.

Hole Etch

“The difficult etch of the hole, the materials are different so the challenges is different,” commented Singh about the different types of 3D-NAND now being manufactured by leading fabs. “During this conference, one of our customer presented that they do not see the hole diameters shrinking, so at this point it appears to us that shrinking hole diameters will not happen until after the stacking in z-dimension reaches some limit.”

Tri-Layer Resist (TLR) stacks for the hole patterning allow for the amorphous carbon hardmask material to be tuned for maximum etch resistance without having to compromise the resolution of the photo-active layer needed for patterning. Carbon mask is over 3 microns thick and carbon-etching is usually responsive to temperature, so Lam’s latest wafer-chuck for etching features >100 temperature control zones. “This is an example of where Lam is using it’s processes expertise to optimize both the hardmask etch as well as the actual hole etch,” explained Singh.

Staircase Etch

The Figure shows a simplified cross-sectional schematic of how the unique “staircase” wordline contacts are cost-effectively manufactured. The established process of record (POR) for forming the “stairs” uses a single mask exposure of thick KrF photoresist—at 248nm wavelength—to etch 8 sets of stairs controlled by a precise resist trim. The trimming step controls the location of the steps such that they align with the contact mask, and so must be tightly controlled to minimize any misalignment yield loss.

Lam is working on ways to tighten the trimming etch uniformity such that 16 sets of stairs can be repeatably etched from a single KrF mask exposure. Halving the relative rate of vertical etch to lateral etch of the KrF resist allows for the same resist thickness to be used for double the number of etches, saving lithography cost. “We see an amazing future ahead because we are just at the beginning of this technology,” commented Singh.

—E.K.

CMOS image sensor update


October 30, 2016

BY DR. PHIL GARROU, Contributing Editor

Toshiba was the first to commercially implement CMOS image sensors with backside TSV last technologies in 2007. Many of us stated in 2007 that further advances could be obtained by removing the CMOS circuitry to a separate layer and forming a true 3D chip stack, but the technology imple- mentation had to wait while the industry first converted to back side imaging technology.

With a conventional front-illumination structure, the metal wiring above the sensor’s photo-diodes impede photon gathering. A back-illuminated structure increases the amount of light that enters each pixel due to the lack of obstacles such as metal wiring and transistors that have been moved to the reverse of the silicon substrate.

The next generation, as expected, combined both BSI and stacking. Conventional CMOS image sensor technology creates the pixel function and analog logic circuitry on the same chip. The motivations for stacked chip CIS include: optimization of each function in the stack, adding function- ality to the stack and decreasing form factor.

Since the pixel section and circuit section are formed as independent chips, each function can be separately optimized, enabling the pixel section to deliver higher image quality while the circuit section can be specialized for higher functionality. In addition, faster signal processing and lower power consumption can also be achieved through the use of leading process for the chip containing the circuits.

The 2014 image sensor market was estimated by Techno Systems Research with Sony as the top seller of image sensors with 40.2% market share, followed by OmniVision (15.7%), Samsung (15.2%) and others with 28.9%.

Sony is clearly leading in commercializing the latest CIS packaging technologies. Some of the biggest names in tech use Sony sensors: The iPhone 6 camera has a Sony sensor, as does the Samsung Galaxy S6, Motorola phones, Nikon DSLRs, and Olympus mirrorless cameras.
Earlier in 2016 it was reported that there are two versions of the Samsung Galaxy S7. One has a Samsung stacked ISOCELL sensor (S5K2L1) and the other a special Sony stacked sensor (IMX260).

The recent Chipworks teardown of the Samsung Galaxy S7 with a Sony IMX 260 revealed BSI stacked technology. Furthermore, it revealed the first reported use of the Ziptronix (now Tessera) Direct Bond interconnect (DBI) technology rather than prior oxide –oxide bonding with subsequent TSVs connecting through the oxide interface. This BSI-stacked DBI technology is possibly the next step in the CIS roadmap.

The Chipworks cross-section reveals a 5 metal (Cu) CMOS image sensor (CIS) die and a 7 metal (6 Cu + 1 Al) image signal processor (ISP) die. The Cu-Cu vias are 3.0 μm wide and have a 14 μm pitch in the peripheral regions. In the active pixel array they are also 3.0 μm wide, but have a pitch of 6.0 μm.
Omnivision was the first to sample BSI in 2007 but costs were too high and adoption was thus very low. In 2015 Omnivision announced their OV 16880 a 16-megapixel image sensor built on OmniVision’s PureCel-STM stacked die technology.

Samsung’s first entrant into stacked technology with TSV was also at 16MP with the Samsung S5K3P3SX in late 2014. The CIS die is face-to-face bonded to a 65nm Samsung image signal processor die and connected with W based TSV. The CIS die is fabricated on a 65nm CMOS process with 5 levels of interconnect.

In early 2015 On Semiconductor (Aptina) introduced its first stacked CMOS sensor the AR 1335 with 1.1μm pixels. It resulted in a smaller die footprint, higher pixel performance and better power consumption compared to their traditional monolithic non-stacked designs. They announced that it would be introduced in commercial products in late 2015.

In late 2015, Olympus announced the OL 20150702-1 a new 3D stacked 16MP CMOS image sensor.

Synopsys, Inc. (Nasdaq:  SNPS) today announced that its Custom Compiler tool has been certified by Samsung Electronics Co., Ltd. to support their 10-nanometer (nm) LPP (Low Power Plus) process. This included providing and validating a Custom Compiler process design kit (PDK) in the industry-standard iPDK format. The kit is available on request from Samsung.

The newly developed Samsung 10LPP iPDK includes all technology information needed to create schematics and layout for customer designs using the Custom Compiler tool with Samsung’s 10LPP process. This comprehensive kit includes support for the groundbreaking Custom Compiler visually-assisted automation flow. Custom Compiler features enabled by the kit include full coloring for triple-patterning, fast placement of FinFET device arrays with the Symbolic Editor, in-design resistance and capacitance reporting during layout, and high-performance in-design design rule checking (DRC).

“We worked with Synopsys to include Custom Compiler support for Samsung’s foundry process offerings,” said Jaehong Park, senior vice president of the Design Service Team at Samsung Electronics. “This new 10LPP iPDK adds to our existing portfolio of iPDKs that are available for Synopsys Custom Compiler users.”

Unified with Synopsys circuit simulation, physical verification and digital implementation tools, Custom Compiler technology provides Samsung 10LPP process users with a comprehensive custom design solution that reduces FinFET layout time.

“Custom Compiler users include leading-edge customers that demand support for the latest process technologies,” said Bijan Kiani, vice president of product marketing at Synopsys. “Samsung and Synopsys worked together to enable Custom Compiler for Samsung’s 10LPP process, which can shorten layout time from days to hours.”

ams AG (SIX: AMS), a provider of high performance sensors and analog ICs, a provider of high performance sensors and analog ICs, has announced its fast and cost-efficient IC prototyping service, known as Multi-Project Wafer (MPW) or shuttle run, with an updated schedule for 2017. The prototyping service, which combines several IC designs from different customers onto a single wafer, offers significant cost advantages for foundry customers as the costs for wafers and masks are shared among all shuttle participants.

ams’ best in class MPW service offers the whole range of 180nm and 0.35μm specialty processes including the recently introduced 180nm CMOS technology (“aC18”). The aC18 process supports a large number of 1.8V and 5.0V NMOS and PMOS devices (substrate based, floating, low leakage and high threshold voltage options) and fully characterised passives including various capacitors. Area-optimised high-density and low-power digital libraries with gate densities up to 152kGates/mm², updated digital and analog I/O libraries with up to 6 metal layers as well as ESD protection cells with up to 8kV HBM level complete the offering. ams’ aC18 process is ideally suited for sensor and sensor interface devices in a wide variety of applications. All 2017 MPW runs in aC18 technology will be manufactured in ams’ state of the art 200mm fabrication facility in Austria ensuring very low defect densities and high yields.

In addition to the four aC18 MPW runs, ams will also offer four MPW runs in its advanced 180nm High-Voltage CMOS (aH18) technology supporting 1.8V, 5V, 20V and 50V devices. For its 0.35μm specialty processes a total of 14 runs are offered in 2017. ams’ 0.35μm High-Voltage CMOS process family, optimised for high-voltage designs in automotive and industrial applications, supports 20V, 50V and 120V devices as well as truly voltage scalable transistors. The advanced High-Voltage CMOS process with embedded EEPROM functionality as well as the 0.35μm SiGe-BiCMOS technology S35 are fully compatible with the base CMOS process and complete ams’ MPW service portfolio.

Overall, ams will offer almost 150 MPW start dates in 2017, enabled by co-operations with worldwide partner organisations such as CMP, Europractice, Fraunhofer IIS and Mosis. Customers located in APAC region may also participate via our local MPW program partners Toppan Technical Design Center Co., Ltd (TDC) and MEDs Technologies.

The complete schedule for 2017 has now been released and detailed start dates per process are available on the web atwww.ams.com/MPW.

To take advantage of the MPW service, ams’ foundry customers deliver their completed GDSII-data on specific dates and receive untested packaged samples or dies within a short lead-time of typically 8 weeks for CMOS and 12 weeks for High-Voltage CMOS, SiGe-BiCMOS and Embedded Flash processes.

All process technologies are supported by the well-known hitkit, ams’ industry benchmark process design kit based on Cadence, Mentor Graphics or Keysight ADS design environments. The hitkit comes complete with fully silicon-qualified standard cells, periphery cells and general purpose analog cells such as comparators, operational amplifiers, low power A/D and D/A converters. Custom analog and RF devices, physical verification rule sets for Assura and Calibre, as well as precisely characterised circuit simulation models enable rapid design starts of complex high performance mixed-signal ICs. In addition to standard prototype services, ams also offers advanced analog IP blocks, a memory (RAM/ROM) generation service and packaging services in ceramic or plastic.

Learn more about the comprehensive service and technology portfolio of Full Service Foundry at www.ams.com/foundry.

A newly-developed form of transistor opens up a range of new electronic applications including wearable or implantable devices by drastically reducing the amount of power used. Devices based on this type of ultralow power transistor, developed by engineers at the University of Cambridge, could function for months or even years without a battery by ‘scavenging’ energy from their environment.

Using a similar principle to a computer in sleep mode, the new transistor harnesses a tiny ‘leakage’ of electrical current, known as a near-off-state current, for its operations. This leak, like water dripping from a faulty tap, is a characteristic of all transistors, but this is the first time that it has been effectively captured and used functionally. The results, reported in the journal Science, open up new avenues for system design for the Internet of Things, in which most of the things we interact with every day are connected to the Internet.

The transistors can be produced at low temperatures and can be printed on almost any material, from glass and plastic to polyester and paper. They are based on a unique geometry which uses a ‘non-desirable’ characteristic, namely the point of contact between the metal and semiconducting components of a transistor, a so-called ‘Schottky barrier.’

“We’re challenging conventional perception of how a transistor should be,” said Professor Arokia Nathan of Cambridge’s Department of Engineering, the paper’s co-author. “We’ve found that these Schottky barriers, which most engineers try to avoid, actually have the ideal characteristics for the type of ultralow power applications we’re looking at, such as wearable or implantable electronics for health monitoring.”

The new design gets around one of the main issues preventing the development of ultralow power transistors, namely the ability to produce them at very small sizes. As transistors get smaller, their two electrodes start to influence the behaviour of one another, and the voltages spread, meaning that below a certain size, transistors fail to function as desired. By changing the design of the transistors, the Cambridge researchers were able to use the Schottky barriers to keep the electrodes independent from one another, so that the transistors can be scaled down to very small geometries.

The design also achieves a very high level of gain, or signal amplification. The transistor’s operating voltage is less than a volt, with power consumption below a billionth of a watt. This ultralow power consumption makes them most suitable for applications where function is more important than speed, which is the essence of the Internet of Things.

“If we were to draw energy from a typical AA battery based on this design, it would last for a billion years,” said Dr Sungsik Lee, the paper’s first author, also from the Department of Engineering. “Using the Schottky barrier allows us to keep the electrodes from interfering with each other in order to amplify the amplitude of the signal even at the state where the transistor is almost switched off.”

“This will bring about a new design model for ultralow power sensor interfaces and analogue signal processing in wearable and implantable devices, all of which are critical for the Internet of Things,” said Nathan.

“This is an ingenious transistor concept,” said Professor Gehan Amaratunga, Head of the Electronics, Power and Energy Conversion Group at Cambridge’s Engineering Department. “This type of ultra-low power operation is a pre-requisite for many of the new ubiquitous electronics applications, where what matters is function – in essence ‘intelligence’ – without the demand for speed. In such applications the possibility of having totally autonomous electronics now becomes a possibility. The system can rely on harvesting background energy from the environment for very long term operation, which is akin to organisms such as bacteria in biology.”