Category Archives: 3D Integration

SET, Smart Equipment Technology, the supplier in high accuracy die-to-die and die-to-wafer bonders, today announced its participation in the 3D integration consortium of IRT Nanoelec, which is headed by CEA-Leti.  SET joins Leti, STMicroelectronics and Mentor Graphics to develop advanced 3D die-to-wafer stacking technologies, using direct copper-to-copper bonding.

Based in Grenoble, France, IRT Nanoelec is an R&D center focused on information and communication technologies (ICT) using micro- and nanoelectronics. 3D integration is one of its core programs.

The 3D integration program was launched in 2012. It brings together, under a single roof, expertise and equipment addressing the entire 3D integration value chain: technology, circuit architecture, EDA tools, packaging and test. Mentor Graphics (EDA), ST (foundry) and Leti are the founding members of the consortium.

“All SET employees, and in particular the team involved in the 3D project, are proud and enthusiastic to join IRT Nanoelec,” said Pascal Metzger, CEO of SET. “Our integration in this program is a logical continuation of the collaboration initiated with CEA teams 35 years ago on different bonding projects, including laboratory high-precision bonder for Cu-Cu direct bonding. One of the key factors for SET joining this consortium is the opportunity to meet and discuss with experts from different specialties.”

“Maintaining high accuracy for components assembly as well as good control of the parameters, while increasing dramatically the throughput, is a real challenge, but we are eager to start the daily work together with IRT teams to reach our mutual goals,” said Nicolas Raynaud, project manager at SET.

Séverine Chéramy, director of IRT Nanoelec’s 3D integration program, said the objective is to offer designers 3D die-to-wafer stacking at an aggressive pitch – less than 10µm – at high speed, at room temperature and without pressure or underfill.

“I’m particularly proud to welcome SET, a French SME, to the program, because it shows the complementarity of the scope of work,” she said. “The collaboration with SET on die-to-wafer bonding, using copper-to-copper bonding at very high accuracy and high speed, is really exciting and challenging. The consortium’s knowledge of such bonding techniques, combined with expertise on high-accuracy SET equipment, offers many opportunities for heterogeneous 3D integration that address a wide range of potential applications. These include imaging, sensors, logic and photonics.”

Nanoelec Research Technological Institute (IRT), headed by CEA-Leti conducts research and development in the field of information and communication technologies (ICT) and, specifically, micro- and nanoelectronics

SEMI today announced the recipients of the 2015 SEMI Awards for the Americas. The awards honor Chenming Hu for the BSIM families of compact transistor models, Alex Lidow for commercialization of GaN power devices, and an Intel team for implementation of bulk CMOS FinFET production. The awards were presented at the 2016 SEMI Industry Strategy Symposium (ISS) yesterday in Half Moon Bay, Calif.

Some innovations become such an integral part of the semiconductor manufacturing industry’s infrastructure that the technology itself becomes fundamental.  2015 award recipients all share the distinction of having pioneered processes and integration breakthroughs that became ubiquitous.

For developing the Berkeley Short-channel Insulated-gate FET Model (BSIM) families of compact transistor models, enabling worldwide adoption of advanced device technologies, Professor Chenming Hu was presented with the 2015 Americas SEMI award. Analog circuit simulators, such as Simulation Program with Integrated Circuit Emphasis (SPICE), form the foundation for circuit simulators used in integrated circuit design, and compact transistor models are the heart of simulators. BSIM3 and its successors, developed in the BSIM group at University of California Berkeley under the leadership of Professor Hu, are the industry standard for transistor modeling. For the past 20+ years, all commercial circuit simulators have included BSIM models.

The Americas SEMI award was presented to Dr. Alex Lidow, Ph.D., for innovation in power device technology enabling commercialization of GaN devices with performance and cost advantages over silicon.  Silicon-based devices were reaching their limits in speed and efficiency, prompting Lidow to develop Gallium Nitride (GaN) technologies, but high cost limited its commercial success. Lidow led the GaN development activity at International Rectifier and continued that work at Efficient Power Conversion Corporation (EPC), a company he co-founded in 2007.  EPC introduced the first commercial enhancement mode GaN power transistors in 2009. Challenges from resolving packaging limitations to establishing a low-cost supply chain were overcome through persistence, paving the way for the successful commercialization of GaN power devices.

An Intel development team ─ Christopher P. Auth, Robert S. Chau, Brian S. Doyle, Tahir Ghani and Kaizad R. Mistry ─ were honored with SEMI Awards for the first development, integration and introduction of a successful bulk FinFET technology for CMOS IC production, first implemented at the 22nm node in 2011. The successful introduction of a bulk FinFET process in commercial IC logic and I/O devices, aided by support from SEMI member companies with development of advanced materials, processes and production tools, was a critically important milestone, which led to the widespread adoption of bulk FinFETs as the technology of choice of leading-edge, fully-depleted CMOS logic devices.

“It is a great privilege to present the 2015 SEMI Awards to these fine technologists, and it is an honor to recognize their contributions to the advancement of technology. It’s innovators like these that propel the industry forward and I thank them for their leadership,” said Karen Savala, president, SEMI Americas.

“The 2015 SEMI Awards recognize contributions in modeling and simulation as well as successful commercialization of new types of logic transistors and power devices,” said Bill Bottoms, chairman of the SEMI Award Advisory Committee. “These important milestones played an enabling role in maintaining the rate of progress in size, cost, performance and efficiency of semiconductor devices and accelerated the commercialization of new device types for logic and power.”

The SEMI Award was established in 1979 to recognize outstanding technical achievement and meritorious contribution in the areas of Semiconductor Materials, Wafer Fabrication, Assembly and Packaging, Process Control, Test and Inspection, Robotics and Automation, Quality Enhancement, and Process Integration.

The award is the highest honor conferred by SEMI. It is open to individuals or teams from industry or academia whose specific accomplishments have broad commercial impact and widespread technical significance for the entire semiconductor industry. Nominations are accepted from individuals of Americas-based member companies of SEMI. For a list of past award recipients, visit www.semi.org/semiaward.

The mobile sector is driving production and market growth; however a new market driver, IoT is on the horizon and is expected to have a significant impact on the advanced packaging industry.

“IoT driven semiconductor industry consolidation, is reflecting into a highly dynamic advanced packaging landscape,” commented Andrej Ivankovic, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing at Yole Développement.

And he added: “Numerous packaging options developed by the industry leaders, are being explored as new IoT applications arise.”

In parallel, Yole Développement’ analysts highlight the noteworthy demand for advanced packaging solutions and the increasing number of shipped wafers: focus is turning to integration and wafer level packages to enable a functionality driven roadmap and revive the cost/performance curve.

ap platforms

Yole Développement (Yole), the “More than Moore” market research and strategy consulting reinforces its market positioning within the advanced packaging area with the release of its first report “Status of the Advanced Packaging Industry”. This first edition brings a thorough analysis including dynamics and disruptions of the market, market forecasts per packaging platform and device type from 2014 to 2020, market shares…This analysis also presents a detailed analysis of the advanced packaging supply chain, financial evolutions and mergers & acquisitions. Yole’s advanced packaging team proposes a packaging technology segmentation and highlights with this new analysis, the impact of Internet of Things and the adoption of 2.5D/3D, Fan-Out and Fan-In solutions.

“A transformation of the semiconductor industry is under way,” said Andrej Ivankovic, Yole. “Advanced packaging is part of the scaling and functionality roadmaps.”

The latest events in the technology market indicate that 2015 marks the beginning of an exciting new era for the IT and electronics industry. At semiconductor supply chain level, the industry entered a profound consolidation phase with high M&A activity reshaping the business landscape. FEOL device scaling and related cost reduction are deviating from the path they followed for the past few decades, with Moore’s law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially.

As the smartphone market matures, new forces are appearing in the form of IoT. While the mobile sector continues to drive the market, the scent of IoT is already spreading in the consumer sector with products such as wearables and first smart home appliances. IoT market, application and technology segmentation has begun. Companies across the industry are restructuring, merging and acquiring in order to adjust their portfolio, enable a complete platform offer and establish leading positions on the market.

Yole’s advanced packaging analysts also identified other market dynamics. They announced:
•   The foundry involvement is no longer a dent in advanced packaging production.
•   Increased activity of Chinese capital on the market.
•   And more

At the level of technology, as profitability of FEOL scaling options remains uncertain and IoT promises application diversification, the spotlight is now turning to advanced packages for cost reduction, performance boost and functional integration.

In order to answer market demands, the advanced packaging segment focuses on integration and WLP. Emerging packages such as Fan-Out WLP, 2.5D/3D IC and related System-in-Package solutions aim to bridge the gap and revive the cost/performance curve.

How will the advanced packaging industry evolve, which changes in the semiconductor supply chain are taking place and which packaging technologies will be most critical in the years to come? Yole proposes with this new technology and market analysis, a deep understanding of the advanced packaging technical and market challenges. Under this new report, the market research and strategy consulting company brings a thorough analysis of the advanced packaging industry and its future development covering platforms Fan-Out WLP, Fan-In WLP, Flip Chip and 2.5D / 3D.

By Dr. Phil Garrou, Contributing Editor

At the 12th annual 3D ASIP [Architectures for Semiconductor Interconnect and Packaging] Conference, sponsored by RTI Int, in Redwood City CA last week, Professor Mitsumasa Koyanagi of Tohoku University and Dr. Peter Ramm of Fraunhofer EMFT were the conference’s first recipients of the “3DIC Pioneer Award”.

Conference Chair Dr. Phil Garrou from Microelectronic Consultants of NC commented, “Since we are now more than a decade into the concerted effort to commercialize 2.5 and 3DIC technology it seemed appropriate to look back and document who actually led the way in this technically challenging effort. After significant study, we are convinced that the research groups in Tohoku University and Fraunhoffer – Munich were not only the first in the field, but also have continued their studies to this day to help commercialize this important leading edge technology.”

Professor Koyanagi (left) and Dr. Ramm (right) accept 3DIC Pioneering Award from conference chair Garrou.

Professor Koyanagi (left) and Dr. Ramm (right) accept 3DIC Pioneering Award from conference chair Garrou.

Profesor Koyanagi’s work started back with his seminal paper “Roadblocks in achieving 3-dimensional LSI” presented at the Symposium on Future Electronic Devices in 1989. His 1995 paper “Three dimensional Integration Technology Based on a Wafer Bonding Technique Using Micro Bumps” showed a process sequence similar to todays TSV etch, thin and bond for an image sensor circuit.

Dr. Ramm began his work in the early 1990s in collaboration with Siemens under the German sponsored R&D program “Cubic Integration – VIC”. Their paper “Performance Improvement of the Memory Hierarchy of RISC-Systems by Application of 3-D Technology,” which appeared in IEEE Trans on Components, Packaging and Manufacturing Technology in 1996 woke up the larger community to the possibilities of using 3DIC. A key patent from that era was USP 5,563,084 “Method of Making a 3 Dimensional Integrated Circuits” which issued in 1996.

ORBOTECH LTD. today announced that SPTS Technologies, an Orbotech company and a supplier of advanced wafer processing solutions for the global semiconductor and related industries, has supplied CEA-Leti, one of Europe’s largest micro- and nanotechnologies research institutes, with its vapor HF etch release systems for 300mm microelectromechanical systems (MEMS) on CMOS development. Installed in 2015 at CEA-Leti’s facility in Grenoble, France, the Monarch300 joins the 200 and 300mm etch, CVD and PVD systems previously supplied by SPTS and which are already operational in CEA-Leti’s MEMS and packaging lines.

“The co-integration of MEMS and CMOS has the potential to create a new family of sensors with improved performance,” said Kevin Crofton, President of SPTS and Corporate Vice President at Orbotech. “The Monarch 300 uses our patented Primaxx vapor HF etch technology and is capable of processing thirteen 300mm wafers simultaneously. NEMS and MEMS are at the core of CEA-Leti’s activities, and we are pleased to be able to supply this highly valued partner with additional capability to support its 300mm MEMS program.”

Marie-Noëlle Semeria, CEO of Leti and President of the Nanoelec RTI board, commented: “MEMS devices co-integrated with CMOS help Leti achieve a long-standing goal of enabling smaller and more powerful sensors and actuators, without exceeding power budgets.”

“After characterizing the performance of a number of competing vapor HF etch methodologies, we selected SPTS’ Primaxx reduced-pressure, dry technology because it extends our existing process capability significantly and offers enhanced compatibility with materials of interest. Leti intends to lead the way in developing MEMS devices on 300mm formats, and to achieve this we are partnering with industry leaders such as SPTS, who have the specialist process knowledge needed to transfer our 300mm MEMS developments to high-volume production,” added Fabrice Geiger, Head of the Silicon Technologies Division of CEA-Leti.

SPTS and CEA-Leti entered into a two-year agreement that will encompass full performance characterization and process optimization of both the 200mm and 300mm vapor HF process modules. This collaboration will further extend the long-standing relationship between these partners who already collaborate on the development and optimization of a range of etch and deposition processes for next-generation 3D high-aspect-ratio through-silicon-via (TSV) solutions.

According to the newly released “Global Semiconductor Packaging Materials Outlook — 2015/2016 Edition,” the $18 billion semiconductor packaging materials will undergo steady single-digit unit volume growth for many material segments through 2019, including laminate substrates, IC leadframes, underfill, and copper wire. Segments such as wafer-level packaging (WLP) dielectrics will experience stronger unit volume growth over the same timeframe. The new report by SEMI and TechSearch International covers laminate substrates, leadframes, bonding wire, mold compounds, underfill materials, liquid encapsulants, die attach materials, solder balls, wafer level package dielectrics, and thermal interface materials.

Packaging materials are a key enabler to increasing the functionality of thinner, smaller packages consumed in smart phones and other mobile products. Many options are currently available to meet form factor requirements for mobile products such as stacked-die chip scale package (CSP), land grid array (LGA) and fine pitch ball grid array (FBGA) packages, package-on-package (PoP), wafer-level package (WLP), Quad Flat No-lead (QFN) and other packages, using both wirebond and flip chip interconnects.

Key observations include:

  • FO-WLP is emerging as a disruptive technology, changing the demand for the types of packaging materials used in the industry
  • Need for WLP dielectric materials for multi-layer redistribution layers
  • New materials for laminate substrates and underfill to pitch decreasing pitch and bump height trends in flip chip packaging
  • Improved mold compounds for warpage control and package reliability
  • For QFN packaging, cost optimization through enhanced designs and reduced plating area; higher lead counts (routable); improved power dissipation
  • Continued growth in copper and silver wire
  • Materials and processes compatible with tighter tolerances for higher density leadframes and substrate packaging, and for compact multi-die system-in-package (SiP) configurations

Constrained industry growth and the trend towards lower-cost electronics have reshaped the packaging material supplier landscape. Changes in material sets, the emergence of new package types, and cost reduction pressures have resulted in recent consolidation in various material segments. In addition, materials consumption in some segments is declining given the changes in package form factors and the trend towards smaller, thinner packaging (see Figure).

metal compound consump

Source: SEMI and TechSearch International, Global Semiconductor Packaging Materials Outlook 2015/2016 Edition

The findings in the report are based on over 150 in-depth interviews conducted with semiconductor manufacturers, fabless semiconductor companies, packaging subcontractors, and packaging materials suppliers throughout the world. The report covers details about the industry growth and trends for the various material segments. Information includes market size, regional data, unit trends, and market share. It includes previously unpublished data on revenue, unit shipments and market shares for each packaging material segment; a five-year forecast of revenue and units from 2015 to 2019; supplier rankings (for key segments) and listing (including new players); and an analysis of regional market trends and size. All of the information was derived from the SEMI Global Packaging Materials Outlook from 2015 to 2019 produced by SEMI and TechSearch International.

2016 bounce to modest gains


December 14, 2015

By Christian G. Dieseldorff, Industry Research & Statistics Group, SEMI

SEMI just published the latest quarterly update of its World Fab Forecast report.  While the year started with a positive outlook, the initial optimism has largely deflated, and the year will end largely flat. Fab equipment spending growth (new and used) for 2015 is expected to be 0.5 percent (US$ 35.8 billion). For 2016, spending is forecast to grow by 2.6 percent ($36.7 billion), with a possible continued upward trend.

Past trends prove again the close correlation of spending to global GDP and revenue.  The IMF predicted worldwide GDP to grow by 3.5 percent back in May, and has revised it down to only 3.1 percent.  Likewise, as of May, the year’s average revenue growth for the semiconductor industry was predicted to be in the mid- to high-single digits (according to ten leading market research firms).  Now these firms have revised their 2015 predictions to an average of just 1.3 percent.

Fab equipment spending (new, used and in-house) follows the same rollercoaster as revenue, and is now expected to grow by only 0.5 percent by the end of 2015, possibly 1 percent, according to SEMI.

Fab-Equipment-Spending

In 2015, 80 to 90 percent of fab equipment spending went to 300mm fabs, while only 10 percent was for 200mm or smaller.  SEMI’s recently published “Global 200mm Fab Outlook” provides more detail about past and future 200mm activities.

Cherish the Memory

Examining fab equipment spending by product type, Memory accounts for the largest share in 2015 and 2016. In 2015, DRAM spending was second in place but in 2016 3D Flash will, by far, outspend DRAM.

Most DRAM spending in 2015 went towards 21/20nm ramp.  In 2016, DRAM companies are expected to start risk production of 1xnm (for example, Samsung in 1H 2016; Hynix in 2H 2016; and Micron in 2016).

While 2015’s spending was dominated by DRAM, SEMI reports that 2016 will be dominated by Flash, mainly 3D-related architectures.  Capacity for 3D-NAND will continue to surge.  SEMI’s report tracks 10 major 3D producing facilities, with a capacity expansion of 47 percent in 2015 and 86 percent in 2016.

Foundry Segment Holds Steady

The Foundry segment is next in terms of the largest share of fab equipment spending in 2015 and 2016.  In general, the foundry segment shows steadier, more predictable spending patterns than other device product segments. The largest foundry player, TSMC, has a strong impact on the foundry industry.  In the second half of 2015, TSMC cut 2015 capex from $10.5 billion to $8 billion, due to a flagging market.  SEMI expects a stronger fourth quarter in 2015 for equipment spending for foundry as TSMC fulfills its capital expenditure for the year and we expect an increased capex in 2016.

TSMC recently announced revenue expectation for 2016 to be in double digits and expects to increase capex for 2016 as it ramps 16nm and adds initial 10nm capacity.

It’s Only Logical (and MPU)

Coming in third place in fab equipment spending, MPU had lower spending in 2015.  Intel revised its planned capex down four times, from $10 billion to $8.7 billion then to $7.7 billion, and finally to $7.3 billion, and it decided to delay the launch of 10nm products (Cannonlake) to 2H17.  Intel still announced lofty plans for 2016 capex, around $10 billion.  Especially in 2H16, spending will pick up for anticipated 10nm activities.

Meanwhile for Logic spending has been very strong in 2015, with 90 percent growth, driven by SONY’s CMOS image sensors.  This exuberant growth, however, is expected to slow down in 1H16.

Consequence of Consolidations: the End of Wild Times?

Between 2010 and 2014, change rates for equipment spending fluctuated wildly, from +16 percent in 2011 to -16 percent in 2012, -8 percent in 2013 to 15 percent in 2014. These drastic changes have been replaced by dampened spending growth rate for 2015 and into 2016.  Multiple reasons may apply: a more mature and lower growth industry, increased caution regarding capacity ramp, or perhaps the recent frenzy of consolidations further concentrating capex spending.  SEMI’s next quarterly publication, in February 2016, will give further insight into early indicators of 2017.  Will sedate, positive spending growth continue?

The SEMI World Fab Forecast Report in Excel format, tracks spending and capacities for 1,167 facilities across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities. It uses a bottoms-up approach methodology, providing high-level summaries and graphs and in-depth analyses of capital expenditures, capacities, technology and products by fab.  Learn more about the SEMI fab databases at: www.semi.org/MarketInfo/FabDatabase and www.youtube.com/user/SEMImktstats

SEMI this week announced details about the fourth annual European 3D Summit.  “SEMI European 3D Summit 2016: Above and Beyond TSV,” the advanced semiconductor summit will take place on January 18-20 at Minatec in Grenoble, France. With 3D now being much more than just TSV and subsequent stacking technologies, the summit has evolved to encompass 3D as part of the whole advanced packaging continuum.

The SEMI European 3D Summit will include a wide scope of 3D integrated circuit topics beyond Through-Silicon-Via (TSV) technology ─ with presentations on FO-WLP/ e-WLB, Embedded Die, 3D alternative technologies, new “Start-Up Pitch” session, and companion exhibition with the latest 30 products and services:

  • On 18 January, the Market Briefing session will highlight the latest business challenges and opportunities. Featured 3D and packaging industry experts will include McKinsey, System Plus Consulting, TechSearch International, and Yole Developpement.
  • On 19 January, the 3D Packaging for High-Performance session includes CEA-LETI, ATOS and a keynote from Cisco’s Li Li on “Emerging 2.5D and 3D IC Packaging Platforms for System Integration.”  In the 3D Integration Strategy for Imaging products session, experts from Invensas, Olympus, Redbelt Conseils, and STMicroelectronics will present. The New Technologies session features experts from ASE, Fraunhofer IIS/EAS, imec, and XFab. The final two sessions cover Key Enabling Technologies and Start-Up Pitches.
  • On 20 January, the focus is on “FO-WLP: 3D Options” with a keynote from Ramakanth Alapati of GLOBALFOUNDRIES, plus presentations from AMKOR, Nanium, and SPTS. The final session is on the Manufacturing of 3D Integrated Products with speakers from ams, AT&S, Mentor Graphics, and Xintec.

SEMI will provide attendees networking opportunities throughout the event.  This year, SEMI offers attendees a chance to visit the Minatec Showroom, to learn about the latest innovations being developed in the Grenoble tech hub.

The SEMI European 3D Summit consistently produces a large industry turnout receiving top satisfaction rates (97 percent overall satisfaction rate, 2012-2015).  The  European 3D Summit steering committee includes executives from: ams AG, BESI, CEA-Leti, Evatech, EV Group, Fraunhofer-IZM, imec,  Scint-X,  SPTS, STMicroelectronics and SUSS Microtec.

It is possible to fabricate copper pillars more than 100μm in height, with aspect ratios up to 6:1, using advanced packaging stepper lithography in conjunction with electroplating.

BY KEITH BEST, Rudolph Technologies, Wilmington, MA, and PHILLIP HOLMES, TEL NEXX, Billerica, MA

Recent years have seen rapid development in the area of advanced packaging. In general, advanced packaging processes are concerned with the interconnection of multiple chips in a single package to provide increased functionality and performance in a smaller volume. System Scaling Technology — the combination of front-end, middle-end and back-end to advance microelectronic systems—utilizes many different advanced packaging approaches, one of which is known as 2.5D packaging. The term “2.5D packaging” has not always been used consistently in literature. The definition used for the purpose of this paper can be summarized as follows: a 2.5D package utilizes an interposer between multiple silicon die and a system-in-package (SiP) substrate, where this interposer has through vias connecting the metallization layers on its front and back surfaces (FIGURE 1).

FIGURE 1. A 2.5D IC/SiP using an interposer and through vias.

FIGURE 1. A 2.5D IC/SiP using an interposer and through vias.

 

The development of these new packaging schemes is being driven primarily by the rapid growth in mobile handheld devices such as smartphones. Often, the manufacturing processes used are adaptations of well-established front-end processes. A number of different approaches are in development or already in production, including wafer-level chip scale packaging, copper pillar bumps on through silicon vias (TSVs), fan-out wafer level processing, and many more. Of particular interest is the replacement of solder bumps by fine pitch copper pillar bumps, which has been the subject of many new system- in-package designs. Here we investigate the lithography and plating of copper pillars, with focus on heights in excess of 100μm and diameters of 25μm, in anticipation of future SiP requirements.

The increase in the number of I/O channels required by multi-chip system designs has exceeded the density and pitch capabilities that traditional solder bump processes can deliver, so that an alternative connection scheme is required. For interposers, the key enabling technology has been the development of fine pitch copper pillar bumps to provide the high-density interconnection between the interposer and the die. Copper pillar bumps provide a number of advantages over the solder bumps they are supplanting. They can deliver finer pitches, 40μm and less have been demonstrated. They also provide superior electromigration performance in applications where high current-carrying capacity is required. However, lithography and electroplating for fine pitch copper pillar bumps can be particularly challenging. The pillars are electroplated into openings in a thick layer of photoresist which exceeds the capability of most front-end tools. Typically, today’s copper pillars range from 30-50μm in height, with height to width aspect ratios from 1:1 to around 2:1 Here we describe the lithography, resist, and electroplating systems and processes required to create 5:1 aspect ratio copper pillars with heights in excess of 100μm.

Photoresist

A negative tone photoresist (JSR THB-151N) was chosen for this work. Its acrylate groups cross-link on exposure and are developed in industry standard 2.38% TMAH developer. The photoresist was spun to a thickness of 120μm on 300mm silicon wafers with an under bump metallization (UBM) prepared seed layer. To reach the 120μm photoresist film thickness, two coatings of photoresist were required, soft baked at 130C, 300secs and 130C, 360secs respectively. After coating, the photo- resist film was allowed to rehydrate for one hour prior to exposure on a wafer stepper (Rudolph Technologies’ JetStep System).

Lithography

We used a customized test reticle that included a wide range of sizes and pitches to expose the wafer. When processing a thick photoresist, well-controlled sidewall angles are a critical requirement, especially when electroplating tall copper pillars. Most front-end tools have high numerical aperture (NA) lenses with low depth of focus (DOF) that prevent adequate exposure of thick films with sufficient image contrast to meet the sidewall angle and resolution requirements. Mask aligners also struggle with high aspect ratio imaging, not because of their NA, but because they are unable to provide the necessary focus offset required to expose the film at high resolution, ultimately limiting their aspect ratio and sidewall angle control. Although photoresist sidewall angles are primarily a function of the photoresist material and its processing (pre-bake, post-bake, developing, etc.), the exposure system plays an important role. Accurate focus control across the wafer or substrate is required to achieve consistent and accurate CD control with straight and perpendicular sidewalls.

The lithography stepper employed in this study refocuses for each exposure to ensure optimal focal plane height on advanced packaging substrates that are frequently warped by film stress and thermal cycling. The system’s 0.1 NA provides a large depth of focus to maintain image integrity and CD control through thick films. The stepper lens is achromatized and the installed “filter wheel” provides a choice of illumination wavelengths to expose the photoresist layers: “broadband” ghi (350-450nm), gh (390 to 450nm) or i-line (365nm). This study, with a photoresist thickness of 120μm, required high energy illumination of >1000 mJ/cm<sup>2</sup>, so broadband illumi- nation (g,h,i wavelengths) was employed to maintain high throughput.

The coated wafers were exposed using a focus exposure matrix wafer layout which provided a large number of programmed focus and exposure conditions at a fixed stepping distance to enable quick and efficient character- ization of the lithography process window for any pillar CD. After exposure, the wafers were developed for a total time of 180 secs, using 6 puddles in 2.38% TMAH. A number of wafers were processed in this way to provide images of the resist structures prior to the electroplating process. The SEM micrograph in FIGURE 2 shows a cross section of the photoresist via mold structures, the CD limit appears to be 25μm with this process, since the via is not open to the seed metal beyond this resolution.

lithography 2

It is interesting to note how the sidewall angle of the photoresist changes with decreasing CD suggesting that the plating will generate a “pedestal” type of copper pillar base at larger CDs, becoming progressively more vertical at smaller CDs. However, upon closer inspection of the smallest CDs, a slight “footing” can be observed at the base of the via (FIGURE 3), and this could result in slight undercut of the final copper pillar. The footing effect was most likely the result of our unoptimized develop process.

lithography 3

Electroplating

After the lithography processing, the wafers were sent to TEL NEXX for electroplating. The plating process employed the TEL NEXX Stratus P300 System, a fully automated electrochemical deposition system for advanced wafer-level packaging applications. The system deposits thick metal layers for wafer bumping, redistribution layers, TSVs, integrated passives, and MEMS.

In this study, we used a methanesulfonic acid copper chemistry with organic additives. The bath composition, operating temperature and current waveform were optimized for high speed copper plating into very thick resist features with flat bump profiles. After plating the photoresist was stripped using an immersion bath with EKC162 solution at 60 degrees. To preserve the profile of the photoresist mold the seed layer was not etched. The final copper pillar structures exhibit the inverse photo- resist mold profile (FIGURE 4).

lithography 4

The electroplating process successfully deposited copper in the photoresist via “molds” that were open to the copper seed material, producing good quality copper pillars with a final minimum copper pillar CD of 20μm, indicating a process bias of 5μm. This bias enabled the final copper pillar to reach a 6:1 aspect ratio as shown in FIGURE 5.

lithography 5

The final copper pillars exhibit excellent sidewall angle, 90 degrees for the smaller CDs. The profiles correlate well with the profiles observed in the photoresist SEM cross sections. The change in profile at the base of the photoresist for the smaller CDs did result in a slight undercut of the final copper pillar. The removal of this photoresist foot could be achieved by either increasing the de-scum time or modifying the develop recipe. The larger copper pillars tended to flare out slightly at the base (FIGURE 6) compensating for any undercut. This will benefit the structure during the removal of the copper seed layer.

lithography 6

The rheology of the copper pillar surface is very important for bonding reliability and the uniform plating of Sn solder, which was not performed during this particular study since it was not the primary objective. FIGURE 7 shows the flat top surface of a copper pillar which is free of voids and defects.

lithography 7

For advanced packaging applications, precise copper pillar height control is essential, and lithography CD control plays an important part in the plating process since CD variation directly affects plated height. The electroplating rate is proportional to current per unit area, i.e. the open area at the bottom of the photoresist openings at the beginning of the process, and the area of the evolving metal surface during deposition. Variation in CD or sidewall angle across the wafer will result in a corresponding change in copper pillar height. For example, in the case of copper pillar features a 5% change in CD can cause a 10% change in plated height.

Conclusion

The results of this study prove that it is possible to fabricate copper pillars more than 100μm in height, with aspect ratios up to 6:1, using advanced packaging stepper lithography in conjunction with electroplating. As advanced packaging requirements continue to evolve, the ability to create smaller copper pillar CDs at finer pitches in thick films will provide increased I/O density opportunities for SiP designers. Furthermore, it is clear that achieving high yield and reliability in the final package requires precise CD control throughout the entire photoresist profile to ensure consistent copper pillar height.

KEITH BEST is director applications engineering at Rudolph Technologies, Wilmington, MA. PHILLIP HOLMES is director of technology at TEL NEXX, Billerica, MA

Subtleties in thicknesses between the alternating Cu metal and dielectric layers within a build-up substrate can impact BLR performance.

BY JAIMAL WILLIAMSON, Texas Instruments, Dallas, TX

Managing an organization in an orderly and disciplined manner is known as “running a tight ship.” This mentality and discipline cannot be understated with build-up substrate supplier capability and manufacturing tolerances as it relates reliability and margin in a flip chip ball grid array (FCBGA) device. Build-up substrate technology is the backbone for flip chip packaging due to its ability to bridge high density interconnects and functionality enabling improved electrical performance in tandem with the semiconductor chip. Alternating metal and dielectric layers build up the substrate into the final composite structure. The range of thicknesses of the aforementioned metal and dielectric layers are dependent on associated substrate manufacturer design rules, which can have an impact on board level reliability (BLR). Having a keen awareness of substrate supplier design rules can aid not only troubleshooting, but improve understanding of reliability margin from a chip to package interaction standpoint for any array of commercial and automotive FCBGA applications.

Influence of copper and dielectric layers on reliability

To better understand the thickness variation impact of bottommost substrate copper (Cu) metal (15 +/- 5μm) and dielectric (30 +/-6μm) layers as it relates to strain energy density of BGA solder joint at die shadow area and package corner, a 3×3 factorial design of experiments (DoE) approach (FIGURE 1) was pursued. Through the use of finite elemental modeling, outputs of the study included both strain energy density under -40°C to 125°C and 0°C to 100°C BLR temperature cycle conditions and changes in coefficient of thermal expansion (CTE) as Cu metal and dielectric thicknesses varied. For the remainder of the article, results from the more stringent -40°C to 125°C BLR temperature cycle condition will be discussed.

FIGURE 1. 3x3 factorial DoE.

FIGURE 1. 3×3 factorial DoE.

Rationale of the study was based on a striking difference in BLR performance from two FCBGA daisy chain test vehicles having an identical substrate design, but manufactured at two different substrate suppliers (noted as supplier A and B in this article). The FCBGA daisy chain test vehicle comprises the following package attributes (see FIGURE 2 for a side view example):
• 40mm x 40mm body size
• 8-layer build-up stack (3/2/3)
• 400μm core thickness
• 1mm BGA pitch

FIGURE 2. Example of FCBGA package.

FIGURE 2. Example of FCBGA package.

Weibull analysis was generated from empirical BLR results at 5 percent and 63.2 percent cycles to failure. Specifically, at 5 percent cycles to failure supplier A exhibits ~25 percent reduced BGA solder joint fatigue life than counterparts from supplier B (as illustrated in FIGURES 3 and 4).

FIGURE 3. Weibull plot of supplier A.

FIGURE 3. Weibull plot of supplier A.

FIGURE 4. Weibull plot of supplier B.

FIGURE 4. Weibull plot of supplier B.

In a similar study focusing on component level reliability (CLR), it was observed that bottommost substrate Cu layer thickness can impact stress underneath die shadow area. For these reasons, a more detailed examination was done to measure bottommost substrate Cu layer thickness from daisy chain units of suppliers A and B. Based on package construction analysis, supplier A was found to target the nominal value of 15μm; whereas supplier B targeted the high end of specification at 20μm. These Cu thickness differences would play a significant role in the BLR results.

Stress modeling results

Outputs of the finite elemental modeling are revealed in FIGURE 5 based on inputs from the aforementioned 3×3 factorial DoE illustrated in Fig. 1. Based on the combi- nation of various Cu and dielectric layer thicknesses evaluated, thicker dielectric and Cu layers yield higher macroscopic CTE values. This is an expected trend based on CTE material properties of Cu and dielectric layers in relation to the substrate core material. Simulation results confirmed CTE in ascending order is: dielectric layer > Cu layer > substrate core. Comparing Weibull analysis from supplier A and B (figures 3 and 4), DoE legs 4 and 6 match best, respectively, to the empirical BLR results. In addition, DoE legs 4 and 6 align with the bottommost substrate Cu layer thickness values from the aforemen- tioned package construction analysis measurements. It is noted that based on modeling results, an approximately 2 percent change in CTE can swing the cycles to failure at 63.2 percent by ~11 percent. DoE leg 4 focuses on nominal Cu thickness of 15μm; whereas leg 6 focuses on the high end of the Cu thickness tolerance at 20μm. Dielectric thickness is nominal value of 30μm in both DoE cases. Improved BLR performance from supplier B is attributed to the thicker Cu providing a better CTE match to the BLR test board.

FIGURE 5. Finite elemental modeling results.

FIGURE 5. Finite elemental modeling results.

Use of JMP for statistical perspective

As a supplemental tool for data interpretation, JMP statistical analysis was performed to illustrate how nominal and extreme values of the metal and dielectric layer thickness specification affect FCBGA BLR performance. Analyzing the strain energy data outputs, the model fit well to the predicted values as shown in FIGURE 6. Similarly, CTE correlated well with predicted values as illustrated in FIGURE 7. Use of the prediction profiler function, as illustrated in FIGURE 8, shows CTE is proportional to increase in metal and dielectric thickness, which correlates with the stress modeling results.

FIGURE 6. JMP model of SED predicted vs. actual.

FIGURE 6. JMP model of SED predicted vs. actual.

FIGURE 7. JMP model of CTE predicted vs. actual.

FIGURE 7. JMP model of CTE predicted vs. actual.

FIGURE 8. CTE prediction as a function of metal and dielectric thickness

FIGURE 8. CTE prediction as a function of metal and dielectric thickness

Summary

Subtleties in thicknesses between the alternating Cu metal and dielectric layers within a build-up substrate can impact BLR performance. Two identical daisy chain substrate designs manufactured by different suppliers were compared head to head. A detailed package construction analysis revealed differences in bottommost Cu thickness layer within the substrate. This Cu thickness delta between the two substrate designs caused a change in CTE with supplier B (higher value) than supplier A due to thicker copper. Finite element modeling demon- strated relatively small macroscopic changes in CTE on the order of less than 2 percent can affect cycles to failure by 11 percent.

The key takeaway found from the head to head evaluation was supplier A producing a more stable process as it was able to meet the center point of the Cu thickness specification as compared to supplier B, which was off target. However, in essence, supplier A lost the head to head BLR comparative study with supplier B as its accuracy in meeting the Cu thickness target caused reduced solder joint fatigue life. The typical corrective action would be to work with supplier B to establish better tolerance control in their Cu plating process to stabilize Cu thickness at the center or nominal value like supplier A. However, the lesson learned was to tailor and control the Cu thickness at the higher end of the specification to improve reliability performance. Typically, in any setting the criteria of success is to hit the bullseye or target, which supplier A achieved. Conversely, supplier B missed this mark with results that were skewed to the right. Ironically, because of the skewed results off-target reliability margin was obtained. In reflection of these findings, the adage “success is in the eyes of the beholder” has never been more poignant.

JAIMAL WILLIAMSON is a packaging engineer responsible for development and qualification of Embedding Processing FCBGA devices within Texas Instruments’ Worldwide Semiconductor Packaging group.