Engineered SOI substrates are now a mainstream option for the semiconductor industry.
BY MARIAM SADAKA and CHRISTOPHE MALEVILLE, Soitec, Austin, TX and Grenoble, France
The number of mobile subscribers worldwide reached 95.5% of the world’s population in 2014 and is expected to reach 9.3B by 2019 (1). This fast growing trend is driving end markets towards satisfying stringent demands of mobile connected users. Whether it is a smartphone or a wearable device, the key requirements include low cost, extended battery life, more functionalities, smaller form factor, and fast time to market. In an effort to bring more performance, more functionality or less power consumption, innovation starting at the substrate level has demonstrated significant achievements. This includes implementing planar Fully Depleted Silicon-On- Insulator (FD-SOI) devices with full back bias capability to extend Moore’s Law beyond 28nm and meet power/ performance/cost requirements for low power SoCs. In addition, using High Resistivity SOI for integrating the RF Front End Module (FEM) providing significant die cost advantage with increased performance and functionality. In this paper, engineered substrates for next generation ultra-low power integrated digital and RF devices and other emerging applications will be discussed.
Device scaling and device functional diversification
Device scaling has been following Moore’s law for the last five decades, doubling transistor density every two years, bringing higher performance, more functionality at lower cost. To maintain this trend, the industry implemented non-classical ways to continue on the scaling path. This started with innovation at the material level, then innovation at the device structure level demonstrating improved electrostatic control enabled by fully depleted (FD) devices (FIGURE 1). FD devices include planar FD-SOI, vertical FinFET or multi-gate device structures. FD-SOI is a great example of device scaling in the substrate era, where the engineered substrate provides the fully depleted structure that solves the variability challenge and enables body bias capabilities to meet the power/performance and cost requirements for low power consumer SoCs.
![FIGURE 1. Technology migration history [2].](https://electroiq.com/wp-content/uploads/2015/07/Substrate-Fig-1-1024x388.png)
FIGURE 1. Technology migration history [2].
The semiconductor industry also has another key focus called More-Than-Moore. This new trend provides added non-digital functional diversification without necessarily scaling according to Moore’s Law. More- than-Moore technologies cover a wide range of domains, and there are numerous examples where advantages brought by substrate engineering enable better perfor- mance and more functionality. With the increasing demand for wireless data bandwidth and the emergence of LTE Advanced, new RF devices with higher levels of integration and more stringent specifications need to be developed. RF-SOI substrates are a great example of how engineered substrates play a major role in achieving the needed level of performance and integration. Two generations of High Resistivity SOI (HR-SOI) substrates compatible with standard CMOS processing were developed [3]. While Gen 1 HR-SOI is well suited for 2G and 3G requirements, Gen 2 HR-SOI enables much higher linearity and isolation meeting most stringent LTE Advanced requirements and thus is paving the way for higher levels of integration with better performance at an improved cost (
FIGURE 2).
FIGURE 2. Soitec’s RF-SOI leadership from ideas to high volume manufacturing.
UTBB FD-SOI substrates
FD-SOI with ultra-thin Box, known as Ultra-Thin-Body and Box (UTBB) substrates, are an attractive candidate for extending Moore’s Law at 28nm and beyond while keeping the cost benefit from shrinking. UTBB FD-SOI devices represent an extension of the planar device archi- tecture demonstrating several advantages essential to low power SoCs.
FD-SOI devices have excellent immunity to Short Channel Effects (SCE) leading to improved sub-threshold swing and Drain-Induced Barrier Lowering (DIBL), and minimum Random Dopant Fluctuation (RDF), thanks to the undoped channel. This ensures lowest Vt variation [4,5], improves performance at lower Vdd as well as improves SRAM and analog mismatch and analog gain, allowing superior digital/analog co-integration [6].
UTBB FD-SOI devices combine the advantage of tuning the front gate and back gate work function [4] as well as enabling effective back bias capabilities for multi-Vt options (FIGURE 3). The back bias capability is a unique feature that enables Vt modulation for better trade-off of power and performance and can be effectively applied in a static or dynamic mode. Moreover, UTBB FD-SOI back bias capabilities show no degradation with scaling and offer a wider range of biasing versus bulk at no area penalty [5].
FIGURE 3. UTBB FD-SOI with Back Bias (Courtesy of ST Microlectronics).
UTBB FD-SOI is a scalable technology supporting at least three nodes; 28nm, 14nm and 10nm (FIGURE 4A). The technology satisfies density/area, performance and power saving requirements without a disruptive change in device architecture and integration. Today, available foundry offerings demonstrate competitive performance at 28 & 22nm [1,7] and the technology is proven down to 10nm [8]. Scaling requires thinner SOI and BOX. In order to alleviate the constraints on SOI film thickness reduction, a scaling sequence based on different BOX layer thickness was proposed, FIGURE 4B [9]. SOI substrates with 25nm BOX are already in production and 10 nm BOX has been demon- strated. Furthermore, the substrate roadmap beyond 14nm includes substrate strain engineering providing the advantage of enhancing the carrier mobility independent of device pitch. This includes strained silicon directly on insulator (SSOI) or strained SiGe- On-Insulator (SGOI) [10].
![FIGURE 4. (a) UTBB FD-SOI Device integration supporting three nodes (11) (b) SOI/BOX thickness scaling ensuring a DIBL of 100 mV/V or below down to 7 nm node [9].](https://electroiq.com/wp-content/uploads/2015/07/Substrate-Fig-4-1024x480.png)
FIGURE 4. (a) UTBB FD-SOI Device integration supporting three nodes (11) (b) SOI/BOX thickness scaling ensuring a DIBL of 100 mV/V or below down to 7 nm node [9].
FD-SOI devices are planar devices that are fully compatible with mainstream CMOS processing, designs and EDA tools, providing a faster time to market solution. In addition to fully leveraging conventional CMOS processes, FD-SOI process integration is simpler than bulk (
FIGURE 5) [1, 12]. FD-SOI process saves several masks and process steps typically included for Vt tuning and for the integration of uniaxial stressors needed to boost performance in planar and FinFET bulk [13, 14]. Even with the drastically increasing lithography cost, such process simplifications more than compensate for the SOI substrate cost, resulting in a lower overall processed wafer cost [11].
FIGURE 5. 28nm FD-SOI vs. 28LP process (courtesy of ST Microelectronics).
While the vertical FinFET device features excellent gate control and high density/performance per area, it also requires a disruptive change in process and design resulting in higher cost and longer time to market. For applications that require the ultimate performance/ digital integration and large die size, vertical FinFETs are a good solution. For other applications that cannot afford the FinFET solution, such as cost sensitive low-mid end mobile consumer applications, FD-SOI is a great candidate for providing low power/high performance and more analog integration capabilities with the least process and design disruption for low cost and fast time to market. Furthermore, FD-SOI devices with back bias can operate at voltages as low as 0.35V [15,16] without area and costly design penalties making them excellent candidates for Ultra-Low Power (ULP) applications. FD-SOI devices consume less energy than bulk at the MEP (Minimum Energy Point) and maintain the smallest energy per cycle with higher operating frequency across the whole Vdd range [17, 18]. This makes UTBB FD-SOI technology a very attractive option for enabling ULP cost sensitive IoT applications.
Smart Cut enabling uniformity for Vt variability control
FIGURE 6: The Smart Cut process.
Optimization of the conventional Smart Cut process is essential for delivering ultra-thin SOI and BOX with well controlled wafer-to-wafer and within-wafer uniformity (FIGURE 6). The Smart Cut unique uniformity control relies on several key aspects of the process [19]: (a) A highly uniform thermal oxidation of a donor wafer to form the BOX (b) A conformal hydrogen implant through the oxide to define the separation plane in the Silicon (c) A high temperature anneal to eliminate the SOI roughness while keeping excellent on-wafer SOI uniformity (20). Developing an efficient smoothing process to eliminate the Si roughness is critical for ensuring low transistor Vt variability. This requires Si thickness monitoring across the entire range of the spatial frequency. As existing ellipsometry and AFM characterizations are necessary but not sufficient, Soitec developed Differential Reflective Microscopy (DRM) to address the 100um scale SOI roughness. Consequently, bridging the gap between ellipsometry and AFM and providing a complete picture of surface roughness crucial for controlling Vt variations at the transistors level (FIGURE 7).
FIGURE 7. SOI layer thickness control.
As the FD-SOI substrate plays a key role in defining the device structure, substrate local and global thickness control is very important. This is especially true for UTBB FD-SOI devices, where the BOX thickness affects the efficiency of Vt tuning through back biasing, and the channel thickness uniformity and roughness influence the electrostatics of the device and Vt variation respectively. Today, Soitec guarantees volume production of SOI 12nm ±5Å and BOX 25nm ±10Å (6 sigma value, all sites, all wafers). When benchmarking variability; planar FD-SOI exhibits the best performance compared to Bulk technologies [4, 5]. Global variability is also reduced and maximum TSi dispersion (TSi,max) obtained on 300mm wafers is already satisfying the objective for Vt variability for advanced technology nodes [4].
High resistivity SOI substrates
The rapid adoption of new wireless standards and the increasing demand for data bandwidth requires RF IC designers to develop devices with higher levels of integration, meeting more and more stringent specification levels. The engineered substrates on which those devices are manufactured play a major role in achieving that level of performance. The improved high frequency performance of CMOS with process shrinks, and the availability of CMOS foundry technol- ogies on 200 or 300mm substrates has made it possible to have high volume fabrication of integrated Si based RF systems, including high quality passive devices [21,22] and RF switches and power amplifiers on SOI substrates [23]. Historically, switches and power amplifiers were built on gallium arsenide (GaAs) substrates. Since 2008, RF-SOI has progressively displaced GaAs and silicon-on- sapphire technologies by offering the best cost, area and performance for RF switches, and thus becoming the mainstream technology solution adopted by the majority of RF foundries [24].
Gen 2 HR-SOI engineered substrates
![FIGURE 8. Silicon uniformity requirements to meet ITRS variability roadmap [4].](https://electroiq.com/wp-content/uploads/2015/07/Substrate-Fig-8-1024x751.png)
FIGURE 8. Silicon uniformity requirements to meet ITRS variability roadmap [4].
Typical SOI substrates do not have thick enough BOX to prevent the electrical field from diffusing into the substrate, inducing high-frequency signal losses, non-linearity and crosstalk which are detrimental to RF performance. To improve the insertion loss, harmonic distortion and isolation performance required for switches, the bulk base substrate of an SOI substrate was replaced by a high-resistivity base substrate known as Gen 1 HR-SOI. The adoption of Gen 1 HR-SOI wafers for RF applications has allowed monolithic integration of RF FEM, leading to smaller size, better reliability, improved performance and lower system cost [25, 26]. While first generation substrates are well suited for 2G and 3G applications, they suffer from the a parasitic surface conduction (PSC) layer induced under the BOX due to fixed oxide charges which attract free carriers near the Si/SiO2 interface. This drastically reduces the substrate effective resistivity by more than one order of magnitude, limiting the substrate capability in meeting the next step in performance for LTE advanced standards (
FIGURE 9).
FIGURE 9. Gen 2 HR-SOI Substrate.
To address this intrinsic limitation, Soitec and Université Catholique de Louvain (UCL) developed a second gener- ation (Gen 2) HR-SOI substrate with improved effective resistivity as high as 10KOhm.cm (FIGURE 10). This was achieved by adding a trap-rich layer underneath the buried oxide to freeze the PSC. These traps originate from the grain boundaries of a thin polysilicon layer added between the BOX and high resistivity substrate [27]. The high resistivity characteristics of Gen 2 HR-SOI substrates are conserved after CMOS processing, enabling very low RF insertion loss (< 0.15 dB/mm at 1 GHz), low harmonic distortion (-40dB) along coplanar waveguide (CPW) transmission lines, and purely capacitive crosstalk close to quartz substrates (FIGURE 11). It was further demon- strated that the presence of a trapping layer does not alter the DC or RF behavior of SOI MOS transistors [28]. With second generation HR-SOI products, RF IC performance is further advanced meeting more stringent losses, coupling and non-linearity specifications (FIGURE 12) [25].
![FIGURE 10. Measured effective resistivity of Gen 1 HR- SOI and trap-rich Gen 2 HR-SOI (TRSOI). Both use 10 kOhm.cm nominal resistivity handle Si substrate [25].](https://electroiq.com/wp-content/uploads/2015/07/Substrate-Fig-10-1024x651.png)
FIGURE 10. Measured effective resistivity of Gen 1 HR- SOI and trap-rich Gen 2 HR-SOI (TRSOI). Both use 10 kOhm.cm nominal resistivity handle Si substrate [25].
![FIGURE 11. (a) Measured crosstalk comparing Gen 2 HR-SOI (TR SOI), Gen 1 HR-SOI and quartz [25] . (b) Measured harmonic distortion along a CPW line, on standard SOI (~ 10ohm.cm) and Gen 1 HR-SOI (~ 1 kOhm.cm) and Gen 2 HR-SOI (TR-SOI) (~ 10 kOhm.cm).](https://electroiq.com/wp-content/uploads/2015/07/Substrate-Fig-11-1024x430.png)
FIGURE 11. (a) Measured crosstalk comparing Gen
2 HR-SOI (TR SOI), Gen 1 HR-SOI and quartz [25] . (b) Measured harmonic distortion along a CPW line, on standard SOI (~ 10ohm.cm) and Gen 1 HR-SOI (~ 1 kOhm.cm) and Gen 2 HR-SOI (TR-SOI) (~ 10 kOhm.cm).
FIGURE 12. Harmonic two and three measured on CPW on commercially available versions of Gen 2 HR- SOI (eSi) substrates.
Because the trap-rich layer in Gen 2 HR-SOI substrates is integrated at the substrate level, additional process steps and consequently more conservative design rules are no longer needed, leading to a more cost effective process and a possible smaller die area per function. Gen 2 HR-SOI substrates now enable RF designers to add diverse on-chip functions such as switches, power amplifiers and antenna tuners with excellent RF isolation, good insertion loss and better signal integrity at lower cost than traditional technologies (FIGURE 13). It also brings clear benefits for the integration of passive elements, such as high quality factor spiral inductors [29], tunable MEMS capacitors [30], as well as reducing the substrate noise between devices integrated on the same chip. Beyond performance, RF-SOI offers a unique advantage to further reduce board area by integrating all FEM devices on the same die [3].
FIGURE 13. Gen 2 HR-SOI (eSi) substrates, advantages vs Gen 1 HR-SOI substrate.
In addition to innovation at the substrate level, Soitec developed the characterization needed to predict the RF Harmonic Quality Factor (HQF) at the substrate level and before device/circuit manufacturing. The characterization method is based on spreading resistance profiling (SRP), which can predict the 2nd harmonic distortion (HD2) performance of a coplanar waveguide (FIGURE 14). This essential metrology step is used today throughout the Soitec product line to ensure Gen 2 HR-SOI SOI substrates provide the expected RF performance at the device level.
FIGURE 14. Harmonic Quality Factor (HQF) methodology.
New substrates for new collaborations
As demonstrated, UTBB FDSOI and Gen 2 HR-SOI substrates are well positioned to address ULP IoT and mobile connectivity applications that will respectively require drastic power reduction and higher frequency bands at very low cost. Combining advanced CMOSprocess capabilities with the demonstrated benefit of engineered SOI substrates is paving the way for digital and RF integration for next generation cost sensitive integrated ULP mobile connected devices.
Furthermore, there are multiple examples where innovative substrate engineering can address roadmap challenges, enable further integration; provide differ- entiation in final product at a more efficient cost and footprint. Some examples of different application segments include: Photonics, Imaging sensors, advanced FinFET (TABLE 1).
Looking beyond a wafer and an application, entering the substrate era requires critical partnerships across the entire ecosystem. This includes having an augmented collaboration along the value and supply chain, covering collaborations with material, equipment and substrate suppliers as well as collaborations with foundries, IDMs and fabless companies. Soitec greatly supports this model and believes in establishing strong collaborations to seed future critical innovations.
Conclusion
Engineered SOI substrates are now a mainstream option for the semiconductor industry adopted by several foundries. UTBB FD-SOI substrates enable planar fully depleted devices with full back bias capability to extend Moore’s Law at 28nm and beyond providing excellent power/performance/cost benefits. Gen 2 HR-SOI substrates enable FEM integration and higher linearity and isolation meeting stringent performance requirements for advanced standards at an improved cost. Combining advanced CMOS process capabilities with the demonstrated benefit of engineered SOI substrates is paving the way for digital and RF integration for next generation cost sensitive integrated ULP mobile connected devices. As such, engineered SOI substrates are well positioned to serve future integrated IoT applications.
Acknowledgement
The authors would like to thank Bich-Yen Nguyen and Eric Desbonnets for their valuable contribution and constructive discussions.
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MARIAM SADAKA is a Soitec fellow based in Austin, TX and CHRISTOPHE MALEVILLE is Senior Vice President, Digital Electronics Business Unit for Soitec, Grenoble, France.
![FIGURE 1. Technology migration history [2].](http://electroiq.com/wp-content/uploads/2015/07/Substrate-Fig-1.png)
![FIGURE 4. (a) UTBB FD-SOI Device integration supporting three nodes (11) (b) SOI/BOX thickness scaling ensuring a DIBL of 100 mV/V or below down to 7 nm node [9].](http://electroiq.com/wp-content/uploads/2015/07/Substrate-Fig-4.png)
![FIGURE 8. Silicon uniformity requirements to meet ITRS variability roadmap [4].](http://electroiq.com/wp-content/uploads/2015/07/Substrate-Fig-8.png)
![FIGURE 10. Measured effective resistivity of Gen 1 HR- SOI and trap-rich Gen 2 HR-SOI (TRSOI). Both use 10 kOhm.cm nominal resistivity handle Si substrate [25].](http://electroiq.com/wp-content/uploads/2015/07/Substrate-Fig-10.png)
![FIGURE 11. (a) Measured crosstalk comparing Gen 2 HR-SOI (TR SOI), Gen 1 HR-SOI and quartz [25] . (b) Measured harmonic distortion along a CPW line, on standard SOI (~ 10ohm.cm) and Gen 1 HR-SOI (~ 1 kOhm.cm) and Gen 2 HR-SOI (TR-SOI) (~ 10 kOhm.cm).](http://electroiq.com/wp-content/uploads/2015/07/Substrate-Fig-11.png)
