Hybrid floating gate nonvolatile memory

imec will describe — for the first time — a demonstration of ultra-thin hybrid floating gate (HFG) planar NVM cell performance and reliability. Results not only confirm the high potential of the HFG thickness scaling down to 4nm with improved performance, but also show excellent post cycling data retention and P/E cycling endurance. The optimized ultra-thin HFG planar cells show potential for manufacture and scalability for high density memory application. The stack consists of an ISSG tunnel oxide, a dual layer FG (PVD polysilicon + PVD TiN), a high-k IPD (ALD Al₂O₃) and an n-type polysilicon CG. (#2.2: "Ultra Thin Hybrid Floating Gate and high-k Dielectric as IGD Enabler of Highly Scaled Planar NAND Flash Technology")

XTEM of a Ge-channel FET with SiGe source/drain.

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Flexible CMOS with SOI

Flexible circuitry promises a host of innovative biomedical, security, wearable, and other products. To date, flexible circuits have offered only limited performance because plastic substrates aren’t compatible with the high temperatures/harsh processes needed to make high-performance CMOS devices. Fabricating high-performance CMOS on silicon substrates, and then transferring the devices to plastic, has shown to be complex and expensive.

At IEDM, for the first time, a way around this will be unveiled: IBM researchers will demonstrate high-performance state-of-the-art CMOS circuits, including SRAM memory and ring oscillators, on a flexible plastic substrate. The extremely thin silicon on insulator (ETSOI) devices had a body thickness of just 60Å. IBM built them on silicon and then used a simple, low-cost room-temperature process called "controlled spalling," which essentially flakes off the Si substrate. Then they transferred them to flexible plastic tape. (#5.1: "Advanced Flexible CMOS Integrated Circuits on Plastic Enabled by Controlled Spalling Technology")

XTEM of a Ge-channel FET with SiGe source/drain.

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Stressed-out 14nm FinFETs with SiGe channels

In a jointly authored paper, researchers from imec, GlobalFoundries and Samsung provide calculations of stress enhanced mobilities for n- and p-FinFETs with both Si and Ge channels for the 14nm node and beyond. Results indicate that both for nFETs and pFETs, Ge is "very interesting," provided the correct stressors are used to boost mobility. They conclude that strained channels grown on a strain relaxed buffer is effective for 14nm nodes and scalable to future nodes. TCAD simulation trends are experimentally confirmed by nano-beam diffraction (NBD). (#6.5: "Stress Simulations for Optimal Mobility Group IV p- and nmOS FinFETs for the 14nm Node and Beyond")

XTEM of a Ge-channel FET with SiGe source/drain.

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Scaling for 2D, 3D NAND memory

In an invited paper, researchers from Micron and Intel will discuss scaling directions for 2D and 3D NAND cells. They note that many 2D NAND scaling challenges are addressed by a planar floating gate (FG) cell, which has a smaller aspect ratio and less cell-to-cell interference. This figure compares a wrap FG cell (left) and a planar FG cell (right); the wrap cell is limited by a required aspect ratio of >10 for both the wordline and the bitline direction in a sub-20nm cell. The planar cell eliminates this limitation. (#2.1: Scaling Directions for 2D and 3D NAND Cells" [Invited])

A wrap FG cell (left) and a planar FG cell (right).

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Intel’s 22nm trigates for SoCs

Multiple-gate transistors provide superior on/off control, enabling high drive currents to be achieved at a lower supply voltage than otherwise. At the International Electron Devices Meeting (IEDM), Intel will discuss its use of the multiple-gate approach to build a complete and versatile 22nm 3D tri-gate transistor technology platform for a range of system-on-chip (SoC) applications. The high-speed logic transistors have subthreshold leakages ranging from 100-nA/μm, while the low-power versions feature leakage of <50 pA/μm yet have drive currents 50% higher than 32nm planar devices. The process also yields high-voltage transistors (1.8V or 3.3V) with the highest reported I/O device drive currents for an SoC technology (NMOS/PMOS=0.92/0.8 mA/μm at 1.8V). The trigate technology platform features eight to 11 layers of low-k and ultralow-k carbon-doped oxide (CDO) interconnect at tight pitches for different applications. (#3.1, "A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and high-k/Metal Gate, Optimized for Ultra-Low-Power, High-Performance and High-Density SoC Applications")

MIMCAP developed for 22nm trigate process.

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Stacking NVM, CMOS

Researchers from the National Chiao Tung University’s National Nano Device Laboratories describe their work which looks toward future 3D layered CMOS for giant high-speed data-storage applications. They demonstrate for the first time a sequentially processed 3D hybrid chip by stacking low-temperature (LT) ferroelectric-like (FE-like) metal-oxide nonvolatile memory (NVM) and multilayered TFT inverters. The sequential layered integration achieved sharp transfer characteristics and stackable 3D FE-like NVMs with 100ns program speed thanks to low-thermal-budget (sub-400°C) plasma/laser processes and self-assembled FE-like metal-ion-mediated APS dielectrics, which resemble low-k dielectrics and metallization in multi-layered back-end interconnects, they explain. (#33.6: "3D Ferroelectric-Like NVM/CMOS Hybrid Chip by Sub-400oC Sequential Layered Integration")

TEM of sequentially processed 3D hybrid chip from gate and channel view.

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Vertical graphene contacts for thermal TSV

Researchers from AIST in Japan will discuss how thermal conductivity of dense vertical and horizontal graphene (DVHG) was improved by forming vertical graphene contacts for thermal TSV. Thermal and electrical conductivity were improved by a factor of 10 and 100, respectively. The pyrolytic graphite with vertical graphene contacts showed a thermal conductivity of 1426 W/mK. (#33.5: "Improved Thermal Conductivity by Vertical Graphene Contact Formation for Thermal TSV")

SEM image of a nanowire resonator (2.3&mu;m &times; 65nm &times; 45nm). Electromechanical coupling is achieved through ~60nm flexible airgap capacitors. The nanowire resonates in-plane.

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3D integration with TSVs, chip-on-wafer

In this paper, TSMC describe an advanced 3D integration process featuring through-silicon via (TSV) and chip-on-wafer (CoW) technologies, analyzing the impact of wafer thinning, stacking, and TSV proximity effects to poly and high-k/metal gate (HKMG) CMOS devices. Using this 3D process, poly and HKMG CMOS wafers have been successfully thinned and stacked, showing little to no degradation in the process. The effect of TSV-induced mechanical stress on ΔIdsat for HKMG was found to be smaller as normalized to poly gate devices for the same channel length (ΔIdsat ratio of HKMG to poly is ~0.3 and ~0.5 for PMOS and NMOS, respectively). They also will show that ΔIdsat for HKMG device is proportional to TSV surface area, independent of TSV orientation, device polarity, and distance of device from TSV. (#33.4: "Thinning, Stacking, and TSV Proximity Effects for Poly and high-k/Metal Gate CMOS Devices in an Advanced 3D Integration Process")

SEM image of a nanowire resonator (2.3&mu;m &times; 65nm &times; 45nm). Electromechanical coupling is achieved through ~60nm flexible airgap capacitors. The nanowire resonates in-plane.

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Silicon nanowire FETs on 200mm FDSOI CMOS

Researchers from EPFL, CEA-Leti, and Minatec demonstrate for the first time the implementation of a highly doped silicon nanowire electromechanical resonator that exploits the depletion charge modulation in a junctionless FET to transduce mechanical motion on-chip. A fundamental resonance frequency of 226 MHz is detected in the drain current. The device is fully integrated in an FD-SOI-CMOS platform using conventional 200mm wafer technology. (#15.2: "Resonant-Body Silicon Nanowire Field Effect Transistor without Junctions")

SEM image of a nanowire resonator (2.3&mu;m &times; 65nm &times; 45nm). Electromechanical coupling is achieved through ~60nm flexible airgap capacitors. The nanowire resonates in-plane.

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TSV-based 3D power distribution

Researchers from IBM and Rensselaer Polytechnic Institute will report on a partition and assembly approach that combines both the electromagnetic (EM) and analytical simulations to accurately model and analyze several TSV-based 3D power delivery networks, which are composed of stacked-chips, interposer, and package substrate. With this method, they for the first time consider RLC couplings between multiple voltage supply rails in 3D systems. The quantitatively examined power performances, they say, unveil 3D power delivery design implications to fulfill 3D integration benefits. (#30.6: "Hybrid Modeling and Analysis of Different Through-Silicon-Via (TSV)-Based 3D Power Distribution Networks")

Two of the 3D power network architectures (not in scale) used in this work.

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