Category Archives: 3D Integration

April 5, 2012 — MOSAID Technologies Inc. is sampling a 16-die stack NAND Flash device operating on a single high-performance channel, the 5126Gb HLNAND. It comes in an 18 x 14mm, 100-ball BGA package.

The 16 industry-standard 32Gb NAND Flash die are stacked with two HLNAND interface devices, outputting 333MB/s (DDR333) at 1.8V output over 1 byte-wide HLNAND interface channel.

HLNAND is fabricated with a ring architecture, which avoids performance degradation in large chip stacks, compared to parallel bus architectures, said Jin-Ki Kim, VP of R&D, MOSAID. The ring architecture allows virtually unlimited NAND die to be connected on a single channel. It does not require termination resistors, lowering the device

April 4, 2012 — The Georgia Institute of Technology (Georgia Tech) Packaging Research Center (PRC) and its industry partners are developing low-cost/high-I/O silicon and glass interposers. Current work covers ultra-thin interposers, via linings, roll-to-roll manufacturing, and more. More areas of focus will be added with a Thinfilm Passive Components (TPC) industry consortium.

GT PRC proposes to add four new focus areas that include:

  • Second-level reliability with low CTE interposers;
  • Ultra-fine-pitch interconnection, down to 15um pitch;
  • Thermal enhancement of glass and silicon interposers and packages; and
  • Thinfilm Passive planar or IPD integration enhanced by through vias in glass or silicon.

The primary objective of the passive consortium is to transform today’s thick and bulky discrete components into thin IPDs or thin planar films with 10X improvements in volumetric density and performance at the same cost as today’s components for power, digital, RF, and analog functions. The thin IPDs (see the figure) will be micro-assembled on, or deposited as planar thinfilms on silicon or glass interposers or packages.

Figure. High-performance thin-film passives on silicon and glass interposers.

The TPC on Silicon and Glass Interposers and Packages Research focuses on:
Novel nanoscale materials and processes for improved properties such as volumetric density, stability and Quality factor
High-yield manufacturing with self-healing and precision-processing
Process integration as planar thin films or micro assembly of IPDs to silicon or glass substrates.

The Georgia Tech PRC has been pioneering low-cost and high I/O silicon and glass interposers with groundbreaking accomplishments in ultra-thin glass and Si panel handling, high throughput vias at small pitch, via-lining for electrical and thermo-mechanical performance, low-cost RDL, small-pitch Cu-to-Cu Interconnections, roll-to-roll ultra-thin glass, via reliability, electrical superiority of glass over Si, and prototype interposer demonstration. Companies interested in more information about this industry consortium are encouraged to contact Dr. Raj Pulugurtha at [email protected], or Prof. Rao Tummala at [email protected]. Internet: http://www.prc.gatech.edu/partnership/TPC.

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March 30, 2012 – BUSINESS WIRE — Semiconductor packaging and test services (SATS) provider Amkor Technology Inc. (NASDAQ:AMKR) granted SHINKO ELECTRIC INDUSTRIES CO., LTD. (Tokyo:6967) a non-exclusive license to its proprietary Through Mold Via (TMV) semiconductor packaging technology.

Amkor will transfer its TMV process to SHINKO, which can manufacture packages based on the via technology under Amkor’s patents. SHINKO may also use the registered TMV trademark for sales and marketing activities. Amkor customers will have multiple sources for the TMV packaging service. Last year, Amkor surpassed 100 million units of its TMV products fabricated.

The technology provides SHINKO with a 3D package stacking process for package on package (PoP) components. With TMV, a blind via is created through the mold compound after package molding. This exposes PoP bond pads on the package substrate

March 26, 2012 – PRNewswire — Semiconductor design/manufacturing software supplier Synopsys Inc. (Nasdaq:SNPS) is combining several products into a 3D-IC initiative for semiconductor designers moving to stacked-die silicon systems in 3D packaging. The 3D-IC initiative will bring in leading IC design and manufacturing companies to work with Synopsys on a comprehensive EDA solution, including enhanced versions of its IC implementation and circuit simulation products.

The 3D-IC technology initiative will focus on design requirements of multiple die to be stacked vertically, or in a side-by-side "2.5D" configuration on a silicon interposer. Multi-die stacks incorporate different materials, often bonded together, with varying coefficients of thermal expansion (CTE). Thermal mismatch can lead to silicon deformation and hurt transistor performance. Through-silicon vias (TSV), microbumps and other solder bumps produce a permanent stress in their silicon zone. Synopsys’ Sentaurus Interconnect TCAD tool analyzes these effects and models the TSVs in the die stacks. Semiconductor companies, such as foundries, then use modeling results to create design rules specific to 3D-IC integration to ensure manufacturability and reliability.

Synopsys’ EDA offering in the 3D-IC initiative includes DFTMAX design-for-test test automation; DesignWare STAR Memory System IP for integrated memory test, diagnosis and repair; IC Compiler for place-and-route support; StarRC Ultra parasitic extraction support for TSV, microbump, interposer RDL and signal routing metal; HSPICE and CustomSim circuit simulation; PrimeRail IR-drop and EM analysis; IC Validator for DRC for microbumps and TSVs and LVS connectivity checking between stacked die; Galaxy Custom Designer for custom edits to silicon interposer RDL, signal routing and power mesh; and Sentaurus Interconnect thermo-mechanical stress analysis.

The Synopsys 3D-IC solution is available now in beta and is expected to be in production in calendar Q2 of 2012. Synopsys’ 3D-IC solution will be highlighted at the Synopsys User Group (SNUG) Silicon Valley event on March 26-28, 2012.

Synopsys, Inc. (Nasdaq: SNPS) provides electronic design automation (EDA) for semiconductor design, verification and manufacturing. For more information on Synopsys’ 3D-IC solution, please visit: http://www.synopsys.com/3D-IC.

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March 23, 2012 — SEMI is seeking papers for technical sessions and presentations at the upcoming SEMICON Europa 2012, October 9-11 in Dresden, Germany. Technical presentation abstracts are due April 30.

SEMICON Europa serves the global microelectronics industry in Europe, with new products and technologies from across the microelectronics supply chain: electronic design automation, device fabrication (wafer processing), and final manufacturing (assembly, packaging, and test). SEMICON Europa also features emerging markets and technologies, including micro electro mechanical systems (MEMS), flexible electronics and displays, nano-electronics, solid state lighting (LEDs), and related technologies.

SEMICON Europa 2012 plans to host more than 100 hours of technical sessions and presentations on the design and manufacturing of semiconductors, MEMS, printed and flexible electronics, and related technologies:

• International MEMS/MST Industry Forum, 8-9 October; theme: “New Dynamics in the MEMS Industry”

• Advanced Packaging Conference (APC), 9-10 October; theme “Packaging Solutions for the New Technologies”

• 14th  European Manufacturing Test Conference (EMTC), 10-11 October; theme: “Overcoming New Test Challenges through Cooperation and Innovation”
 
Submit a 200-400 word abstract of original, non-commercial and non-published material to [email protected], indicating in the subject line of the e-mail: “TEST Call for Papers,”  “MEMS Call for Papers” or “Advances Packaging Call for Papers.” The deadline for submitting abstracts is April 30, 2012. Abstracts must clearly detail the nature, scope, content, organization, key points and significance of the proposed presentation.  The abstract should also contain the main author contact details like job title, company, address, telephone and e-mail, with a short biography.

For more information about the conference or submitting abstracts, including guidelines and requirements, visit http://www.semiconeuropa.org/ProgramsandEvents/CallforPapers, or contact Carlos Lee, SEMI Europe, Tel. +32 2 6095334. SEMI is a global industry association serving the nano- and microelectronic manufacturing supply chains.

March 22, 2012 — Apple’s ARM-based processors have created a point of hardware differentiation in applications processors. With the A5X, Apple is going with a much larger die at the 45nm node (shared across the 2 prior generations), shares Chipworks. It’s also turned off the PoP track.

The Apple A4, still a commercially viable Apple processor, measures 53.3mm².  Only two (and a half?) generations later, the Apple A5X form factor is 165mm² — 3.1x larger. All three of the processors — A4, A5, and A5X — are 45nm chips. By way of further comparison, another flagship applications processor, the NVIDIA Tegra 3 is 82mm², and fabricated in a similar 40nm generation by TSMC, so it is (more or less) consistent with the A5.

Apple changed its chip packaging with the A5X, moving from a package-on-package (PoP) design with the DRAM to DRAM going on the other side of the substrate. This type of packaging theoretically has disadvantages in bill of materials (BOM) simplification and performance, due to the increased chip-to-memory routing. Chipworks considers potential heat issues might be to blame for decoupling the chip and DRAM in the new layout. At the 32nm node, Apple should see lower power consumption and return to the PoP packaging.

Die sizes:
Apple A4 Polysilicon Die = 7.3 x 7.3mm
Apple A5 Polysilicon Die = 10.09 x 12.15mm
Apple A5x Polysilicon Die = 12.90 x 12.79mm

Access the teardown report and download images of the Apple A5X and prior-generation die at http://www.chipworks.com/en/technical-competitive-analysis/resources/recent-teardowns/2012/03/the-apple-a5x-versus-the-a5-and-a4-%E2%80%93-big-is-beautiful/

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March 21, 2012 – Reuters — Taiwan raised investment ceilings for Chinese investors in liquid crystal displays (LCDs), semiconductors, IC assembly and test, microelectronics production equipment, and metal tool manufacturing.

Mainland China companies still cannot hold controlling stakes in these companies in Taiwan, or appointing managers, the government said. But they can hold more than 10% stakes in local companies. All investments must be approved by Taiwan regulators.

This revision also covers makers of light-emitting diodes (LEDs) and solar cells, opened to Chinese investment for the first time. Also read: 2011 results for Taiwan’s LED makers and packagers

Read the full report on Taiwan’s investment regulation changes from Argin Chang, Faith Hung, Chris Lewis at Reuters at http://www.reuters.com/article/2012/03/20/taiwan-china-investment-idUSL3E8EK0RM20120320

In 2011, Taiwan took over as the world leader for installed capacity of semiconductor manufacturing, with 21% of total capacity.

Taiwan also recently re-elected its leader Ma Ying-jeou of the Kuomintang (KMT) for a second term. Ma is not expected to make any major economic and regulatory reforms, according to the US-Taiwan Business Council.

Last month, Taiwan’s Ministry of the Interior (MOI) relaxed its conditions for granting multiple-entry visas to mainland Chinese, to make it more convenient for mainland Chinese business people to visit Taiwan and promote business opportunities. Once the new measures are implemented, the number of mainland Chinese business people obtaining multiple-entry visas is expected to double from the current 4,191 to more than 8,000 a year.

March 21, 2012 — Fraunhofer IZM and Fraunhofer CNT technology centers of Dresden, Germany, will use CMP supplier Axus Technology exclusively to provide advanced 300mm wafer process development and foundry services to North American customers.

Axus Technology is partnering with the Fraunhofer centers for process and metrology services for chemical mechanical polishing (CMP), wafer thinning, and related process technologies, increasing the breadth of offerings in the future. Axus Technology will support local North American customers, define the foundry or development work needed, and work with Fraunhofer engineering teams to complete it.

Fraunhofer’s European facilities focus on state-of-the-art wafer processing and deep engineering expertise. Process services range from small-batch 300mm wafer fab to production volumes, as well as design and development services.

Fraunhofer CNT develops advanced 300mm process flows for front- and back-end-of-line (FEOL/BEOL) applications. Fraunhofer’s IZM-ASSID (All Silicon System Integration Dresden) facility houses a 300mm process line that supports 3D wafer level package (WLP) integration and advanced packaging development. Both Fraunhofer facilities use Applied Materials Reflexion LK 300mm CMP tools and boast extensive metrology capabilities from defectivity analysis and film thickness measurements to microscopy, spectroscopy, X-ray analysis, and more.

Axus Technology’s US-based development and foundry facility handles 200mm wafers through die-sized samples. Partnering with 2 Fraunhofer institutions enables Axus Technology to expand to the larger wafer size without investing in additional manufacturing equipment. It also brings Fraunhofer’s expertise in chip scaling and 3D integration technologies to North America.

Axus Technology provides CMP and wafer thinning equipment and process services for semiconductor, micro electro mechanical system (MEMS), substrate, and related technologies. For more information, visit www.AxusTech.com.

The Fraunhofer-Gesellschaft is a leading applied research organization in Europe, with more than 20,000 staff performing contract research for industry, the service sector, and government.

Fraunhofer Institute for Reliability and Microintegration (IZM) concentrates on microelectronics and microsystem packaging development. Internet: www.izm.fraunhofer.de/assid.

Fraunhofer Center Nanoelectronic Technologies (CNT) focuses on 300mm production in front- and back-end-of-line (FEOL/BEOL) environments, innovative materials for SoCs/SiPs, and nanopatterning through electron-beam lithography. Internet: www.cnt.fraunhofer.de.

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March 15, 2012 — Semiconductor assembly and test services (SATS) provider Amkor Technology Inc. (Nasdaq:AMKR) added Mike Liang as president of Amkor Technology Taiwan. Liang’s background includes stints with Phoenix Semiconductor, Ti-Acer, UMC, and others.

Liang and his team will serve packaging and test customers and execute Amkor’s strategies in Taiwan. Taiwan recently took the global lead in wafer fabrication capacity, beating out its Asian neighbors and the Americas. Taiwan also leads in 300mm wafer capacity installed.

Liang brings "a proven track record in operations, sales and marketing for semiconductor packaging, wafer processing and testing services," said JooHo Kim, Amkor EVP, worldwide manufacturing operations. Liang was most recently president and CEO of King Yuan Electronics Corporation in Hsin-Chu, Taiwan, and has held executive and operational roles at Phoenix Semiconductor International, AbelLink Technology, Mosel-Vitelix, Ti-Acer, and United Microelectronics Corporation (UMC). Liang holds a Bachelor of Science in physics from National Cheng Kung University and an MBA from National Taiwan University.

Amkor provides semiconductor packaging and test services to semiconductor companies and electronics OEMs. More information on Amkor