Category Archives: 3D Integration

The 2012 Common Platform Technology Forum took place March 14 at the Santa Clara Convention Center, with registration topping 1200 attendees by noon. The Common Platform is a Samsung /IBM/GlobalFoundries foundry services entity created to provide a common design space with an assured production capability.

The meeting kicked off with Ana Hunter, Samsung’s foundry business VP. The Common Platform had its roots in 65nm, and is presently working with 20nm gate-last and 14nm FinFET. Pre-revenue investment in the 20nm to 14nm range approaches $10B, with $1-2B in process development, $250M in IP & design libraries, $100M in chip design and $7B in fab construction.

Gary Patton, VP of SRDC at IBM, gave the first keynote with prognostication on the kind of technology development that is in the pipeline beyond traditional CMOS scaling. We are presently in the 3D decade, both in terms of 3D transistor design and 3D packaging integration. Next will be the decade of nanotechnology materials, in which the critical device dimensions do not depend on photolithography. Long-term R&D for this coming decade is already underway, as an extremely long lead time is required for commercialization to manufacturing. In 2011 IBM broke its own US patent record with 6,000 filings, a position it has held for 19 straight years. He hopes EUV will be ready for 10nm, “but we have a dual path.” At 10nm, EUV will provide a bump in k1 factor from 0.15 to 0.55, better that we enjoyed at 90nm. The scanner still needs a 10x improvement in light power, but additional work is needed in photoresist materials and mask fabrication and inspection technology. A new EUV Center of Excellence at Albany CNSE is expected to be operational later this year. Below 80nm, resist development is focusing on directed self-assembly (DSA) of block copolymers. Presently, the 22/20nm work is being done in East Fishkill; 14/10nm at Albany; and 7nm & beyond at Yorktown Research. Fully depleted device structures are the recurring theme going forward. CNT devices provide advantages over FinFETs in terms an order of magnitude reduction in power consumption at the same operating frequency, or an order of magnitude increase in frequency at the same power. With these innovations in design constructs and materials, Gary noted that the transistors are still much more amenable to scaling than interconnects, in which RC performance and structural reliability in both the conductors and the insulators doth protest mightily with scaling. Photonic interconnects on chip continues to be an area of intense development, moving now from fundamental unit performance demonstrations to system integration. The packaging concepts that he reviewed, while challenging, we consistent with advanced packaging concepts that have been progressing over the past five years. TSV is currently in volume manufacturing for power system chips. For stacking large DRAM chips on top of high performance MPU, he expects TSV to be in production within 2 years.

Subi Kengeri, head of the advanced architecture development group, filled in for GlobalFoundries CTO Gregg Bartlett to discuss the convergence of consumer mobility applications enabled by semiconductor technology advances. Foundries are a 300mm leading edge business growing at 15% CAGR. Since 90nm, the time between design start and tape out has been extending as design complexity increases. Design cost has been increasing at a 25% CAGR, whereas fab cost has been increasing at 18%, albeit a much larger number. Smart mobile computing is starting to move into the design driver seat that has up to now been occupied by MPU and GPU functions. Gate last HkMG at 20nm has been selected to meet these needs for 3rd generation HkMG FinFET mobile devices. At 14nm FinFET, you need 100 WPH (wafers per hour) throughput with EUV to break even with 193i with multiple patterning; 180 WPH provides a compelling advantage for EUV.

Jong Shik Yoon, Senior VP Semiconductor R&D at Samsung, spoke on opportunities and challenges in 3D device integration. SOI FinFETs were pioneered by IBM, while Samsung & Intel led the development of bulk FinFETs; the Common Platform supports bulk FinFET. SOI FinFET is used by IBM for server and specialty mobile applications. CNT FET work has been going on at Samsung as well.

Simon Segars, EVP & GM of the ARM Physical IP Division, wrapped up the morning with the fabless design and manufacturing implementation perspective. Industry drivers today are mobile computing, servers and the “internet of things.” Lower cost entry level smart phones represent another billion unit market globally. Mobile networks require about 1 server for every 600 phones, which puts the server demand into perspective, particularly as servers alone become a more significant percentage of world power consumption (still single digits for now). Global internet mobile traffic for 2015 will be about 966 exabytes (that’s a whole lot of gigabytes…). Simon is confident that the collaboration infrastructure that has gotten them to 20nm is extendable to 14nm.

A panel discussion featuring R&D leaders from the 3 Common Platform partners, ARM and CNSE on the R&D pipeline for future semiconductor technology innovation followed lunch. Michael Liehr, VP Research at CNSE pointed out several ways in which the fab there operates like an industrial site, with professors leading engineering teams that function as much like an IDM process development group as a graduate student research group. GlobalFoundries in Malta, NY is currently running 32nm production and 20nm full flow qualification. Work on DSA for photolithography started at IBM in 2000 and is still not ready for prime time. Similarly, copper interconnect development work started at IBM in 1984 and didn’t go into production until 1997, and even then came as a surprise to many outsiders. This is indeed a very long development pipeline.

Rama Divakaruni, IBM Chief Technologist, and Lars Liebmann, IBM Distinguished Engineer, opened a technology session on 14nm technology development with a review of the grand challenges. EUV shows up as a fuzzy transition some time in 2H14 shortly before the 14nm production ramp begins. Development started about 30 years ago in the national labs, but they hope to be able to support integrated process flow development at Albany by YE13. This seems to add gravitas to Gary Patton’s expressed hope that it will actually be ready for 10nm. Triple patterning with 198i is proposed for M1 to maintain design protocols on a path that will provide for a relatively easy return to the EUV goal of single exposure for M1. When pressed for a volume production implementation of EUV, Lars admitted ‘not before 2015’ but could be no more specific.

Yongjoo Jeon, Samsung’s Director of Foundry Technical Marketing gave an overview of their technology offerings at 20nm. Samsung has two versions of the 20nm platform: 20LPE available June 2012 and 20LPM, scheduled for full production May 2013. The 20LPM will use double patterning for isolation, via 0 and minimum pitch M1; both are HkMG gate last. Their 20nm devices are currently 10% below target for DC performance and 20% below target for AC performance, but the root causes are known and the program is considered on schedule to meet its release dates.

Mukesh Khare, Director of Semiconductor Technology at IBM Research, described the innovation pipeline beyond 14nm. Technology elements will include strain, HkMG and FinFET variations to leverage recent innovations, but nanowires will lead the way to a brave new world. We’ve transitioned to a domain in which scaling leads to degradation rather than improvement; new materials and process innovation are required in its place. A silicon nanowire is thought to represent the ultimate extension of the fin structure. The game is already afoot for applying strain to an individual nanowire. Alternative channel material candidates include III-Vs for nFET and Ge and high % Si-Ge for pFET, though challenges remain for silicon integration and contact resistance. Carbon electronics will provide extraordinary carrier mobility and extremely long carrier mean free paths. IBM’s 40nm epitaxial graphene transistor on SiC still holds the RF performance record at 280GHz. Polymer DSA is IBM’s pipeline alternative to EUV. The technology has already been used in the dielectrics used in air gap interconnects. The photoresist analog holds the promise of providing ‘pitch in a bottle.’ The double entendre will be better appreciated on days when it does not work. In combination with 193i, DSA has been used to produce 25nm line/space pairs with excellent line edge roughness.

Michael A. Fury is a Director & Senior Technology Analyst at Techcet Group.

March 14, 2012 – PRNewswire — EV Group (EVG), semiconductor and MEMS fab equipment supplier, welcomed semiconductor materials supplier Shin-Etsu Chemical Co. Ltd. into its open platform for temporary bonding/debonding (TB/DB) materials supporting 3D semiconductor packaging. Shin-Etsu will work with customers to commercialize 3D IC packaging via wafer bond/debond in volume manufacturing environments.

Shin-Etsu’s advanced adhesives will be qualified with EVG’s EZR (Edge Zone Release) and EZD (Edge Zone Debond) process modules for ZoneBOND room-temperature debonding. Shin-Etsu MicroSi, a wholly owned subsidiary of Shin-Etsu Chemical, has worked closely with EVG’s process development teams to perform stringent test procedures for EVG ZoneBOND equipment.

A strong supply chain for temporary thin-wafer bonding is one step in "the advancement of 3D IC commercialization," noted Markus Wimplinger, EVG’s corporate technology development and IP director. Also read: EVG launches ZoneBond-capable modules and Brewer Science, EVG commercialize temporary wafer bonding with zoning laws

EVG offers ZoneBOND technology, EZR (Edge Zone Release), and EZD (Edge Zone Debond) modules for temporary wafer bonding, thin wafer processing, and debonding applications. The company touts its ability to use silicon, glass and other carriers; compatibility with existing, field-proven adhesive platforms; and the ability to debond at room temperature with virtually no vertical force applied to the device wafer. Strong adhesion occurs at the edge (perimeter) and minimal adhesion is applied to the wafer center, supporting grinding and backside processing at high temperatures and low-force carrier separation.

Shin-Etsu Chemical Co. Ltd. supplies semiconductor materials, semiconductor silicon, PVC resin, synthetic quartz glass and methylcellulose and materials including silicones and rare earth magnets. Shin-Etsu Chemical’s stock (TSE: 4063) is listed on three markets: The Tokyo, Osaka and Nagoya Exchanges in Japan. Internet: http://www.shinetsu.co.jp

Shin-Etsu MicroSi Inc. is a wholly owned subsidiary of Shin-Etsu Chemical Co. Ltd., providing materials and other products for photolithography, packaging, solar and flexible printed circuit applications. Internet: www.microsi.com.

EV Group (EVG) makes wafer-processing equipment for semiconductor, MEMS and nanotechnology applications.  Products include wafer bonding, lithography/nanoimprint lithography (NIL) and metrology equipment, as well as photoresist coaters, cleaners and inspection systems. More information is available at www.EVGroup.com.

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March 12, 2012 — At the recent IMAPS Device Packaging Conference in Ft McDowell, AZ, Solid State Technology’s Insights from the Leading Edge (IFTLE) brought together a panel of manufacturers, users and market specialists to discuss the Evolving 2.5D / 3D Infrastructure.

Panel host and Solid State Technology contributing editor Phil Garrou was joined by Douglas Yu, Sr Director of front end and back end technology development for TSMC; Jonathon Greenwood, Director of Packaging R&D at GlobalFoundries; Remi Yu, Deputy Division Director of UMC; Nick Kim, VP of electronic packaging technologies at Hynix; Rich Rice, Sr VP of sales for ASE ; Ron Huemoeller, VP of Advanced 3D interconnect at Amkor; Matt Nowak, Sr Director of Engineering at Qualcomm and Jan Vardaman, President of TechSearch Inc.

Photo [l to r]: Yu (TSMC), Garrou (IFTLE), Huemoeller (Amkor), Vardaman (TechSearch), Greenwood (GlobalFoundries), Yu (UMC), Kim (Hynix), Nowak (Qualcomm), Rice (ASE).

 

While TSV technology appears to be stabilizing…

Panelists were unanimous in their descriptions of mainstream 3D packaging being represented by 5-8

March 7, 2012 — Semiconductor fab equipment supplier Applied Materials Inc. (AMAT) opened the new Centre of Excellence in Advanced Packaging at Singapore’s Science Park II with its partner in the endeavor, the Institute of Microelectronics (IME), a research institute under Singapore’s Agency for Science, Technology and Research (A*STAR). Singapore’s Minister for Trade and Industry, Lim Hng Kiang, presided at the official opening ceremony.

Plans for the Centre were first announced in April 2011.

The Centre of Excellence in Advanced Packaging will focus on wafer-level and 3D packaging technologies, with a 14,000 square foot Class-10 cleanroom housing 300mm wafer processing equipment. It was created with combined investment of over USD100 million from Applied Materials and IME.

Applied Materials will provide the leading-edge equipment and process technology to be used by IME

March 6, 2012 — Semiconductor test and advanced packaging service provider STATS ChipPAC Ltd. (SGX-ST:STATSChP) uncrated its next-generation 3D embedded wafer-level ball grid array (eWLB) package-on-package (PoP) technology, with a package profile height below 1.0mm.

The PoP format aims for higher thermal and electrical performance, increased bandwidth and speed in an ultra thin package profile, with design flexibility in integrating memory and logic semiconductors. Industry standard is 1.4mm total stacked package height, 30% more than STATS ChipPAC’s new 3D eWLB. STATS uses fan-out wafer level packaging (FOWLP) to reduce the bottom PoP package height below 0.5mm. The technology also offers tighter substrate line/space capability. eWLB PoP is available in single or double-sided configurations.

STATS ChipPAC also offers a co-design process with packaging customers to optimize the functional performance of the ultra thin 3D package. The 3D PoP form factor targets advanced mobile applications: smartphones, media tablets, cloud computing, etc. Microprocessors are adopting the technology. Computing-sector customers are also using eWLB to reduce substrate complexity and cost.

Over 200 million eWLB units are in the market, with package architectures including small die, large die, multi-die and multi-layer designs.

STATS ChipPAC will present on innovative 3D packaging, covering eWLB, low-cost copper (Cu) column flip chip PoP technology, and stacked die integration of RF packages at the IMAPS International Conference and Exhibition on Device Packaging this week in Scottsdale, AZ.

STATS ChipPAC Ltd. provides semiconductor packaging design, assembly, test and distribution services. STATS ChipPAC is listed on the SGX-ST. Further information is available at www.statschippac.com.

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February 23, 2012 — SEMICON China takes place March 20-22 in Shanghai, with SOLARCON China and FPD China, together featuring 1,000+ exhibitors, 150+ government delegations, and 50,000+ attendees.

2011 saw 26% growth for semiconductor fab equipment spending in China, according to the most recent SEMI Consensus Forecast. China’s current Five-Year Plan (2011-2015) targets expansion for China’s microelectronics supply chain to meet the needs of the regional and global markets. US$40+ billion will be invested to fuel Chinese semiconductor industry growth during this period.

SEMICON China showcases the latest advanced manufacturing technologies and programs on the latest technology and business trends in the semiconductor industry and emerging markets. Keynote speakers include:

  • Tzu-Yin Chiu, CEO and executive director, SMIC
  • Tien Wu, director and COO, ASE Group
  • Yu Wang, director, president, Hua Hong Semiconductor; president, Grace Semiconductor Manufacturing
  • Charlene Barshefsky, former U.S. Trade representative, senior International partner, WilmerHale
  • Yoichi Yano, executive VP, Renesas Electronics
  • Walden C. Rhines, CEO, Mentor Graphics

This year’s event features four Theme Pavilions, each focused on a growing critical technology market:

  • The China Market IC Applications Pavilion spotlights companies and technologies focused on serving the fabless and IC design community. From IC design services to foundries to system assembly and test, the Pavilion showcases the best of China’s IC supply chain. Pavilion highlights include: Focus on 450mm wafer manufacturing; advanced automotive semiconductors; power ICs; assembly and test; and MEMS design and manufacturing.
  • The LED Manufacturing Pavilion features manufacturing technologies and information specifically focused on advanced LED and solid state lighting. China currently leads the world in terms of the number of active and under construction LED epi wafer and chip fabs. In 2011, over 400 new MOCVDs systems were installed in China, more than any other country in the world.
  • The TSV Pavilion showcases technologies and solutions for 3D IC and TSV systems. The growth of 3D IC and TSV has spawned a whole ecosystem for TSV technologies from industry, academia and research institutions, to equipment and material suppliers. 
  • The Secondary Equipment Applications, Service and Fab Productivity Solutions Pavilion  features exhibits and solutions for the growing secondary equipment market in China. Analysts project sales of used semiconductor equipment China to increase to between US$ 800 million and US$1 billion in 2012.

Prior to SEMICON China, March 18-19, the China Semiconductor Technology International Conference (CSTIC) will offer more than 300 high-level presentations, covering all aspects of semiconductor technology and manufacturing. Keynote speakers include representatives from IMEC, Samsung, and IBM.

SEMICON China also includes LED China Conference 2012 (March 21), addressing current government policies and support for LED manufacturing expansion; new developments in LED applications, LED fab equipment, and materials; and discussion on how the China LED fab industry can continue its growth.

March 20-22 will host a review of China’s High-Tech Parks, which help shape China’s semiconductor and emerging market (photovoltaic, HB-LED, etc.) industries. China’s regional governments overseeing these high-tech parks strongly support and are willing to provide additional resources to develop the semiconductor industry. Leaders from China’s major municipal governments and high-tech parks are invited to introduce their development plans and special policies. This High-Tech Park review area provides an excellent opportunity for companies which plan to expand China operations and market access.

Additional information regarding SEMICON China 2012 exhibition, programs, and registration is available at www.semiconchina.org.

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February 22, 2012 — International Solid-State Circuits Conference (ISSCC) is going on now, February 19-23, in San Francisco, CA. The conference gathers semiconductor design and device architecture presentations from research firms like imec to chip companies like IBM. Following are some highlighted presentations.

On-chip voltage regulator
University-research consortium Semiconductor Research Corporation (SRC) and Columbia University showcased integrated voltage regulators (IVR) that feature energy densities more than 10x that of present state-of-art inductors. By introducing an unprecedented combination of magnetic materials, chip-stacking design and a 2.5D chip packaging process, the team from Columbia University (funded in part by the SRC) demonstrated a new IVR solution developed with a research team from IBM (SRC member). The technology can reduce power consumption, by 10-20% in a typical US data center, for example. The power converters integrated onto the same chip, or into the same package, as microprocessors "significantly improves computational performance per watt of power consumed," said Professor Ken Shepard, lead researcher for the team at Columbia. The researchers provided all of the traditional advantages of a switched-inductor converter in a form factor that is small enough to integrate on-chip. Another SRC member, Intel Corporation, also has been engaged actively in research in this area. More information about the research is published in “A 2.5D Integrated Voltage Regulator Using Coupled Magnetic Core Inductors on Silicon Interposer Delivering 10.8A/mm2,” presented at ISSCC at the session on Advances in Heterogeneous Integration. The paper is co-authored by Noah Sturcken, Michele Petracca, Ryan Davies, Ioannis Kymissis, Luca P. Carloni and Kenneth L. Shepard from Columbia, Angel V. Peterchev from Duke and Eugene J. O’Sullivan, Naigang Wang, Philipp Herget, Bucknell Webb, Lubomyr T. Romankiw, Robert Fontana, Gary M. Decad and William J. Gallagher from IBM. Learn more at www.src.org.

THz circuits from CMOS silicon fab
SRC and UT Dallas showed that circuits operating at the terahertz (THz) range can be affordably manufactured (hundreds of dollars instead of hundreds of thousands of dollars) in complementary metal-oxide semiconductor (CMOS) silicon, potentially creating new application sectors, including defense, medical, industrial process control and public and industrial safety. In contrast with x-ray, THz is intrinsically safe, non-destructive and non-invasive. With the cost-effective manufacturing development, THz can become accessible for use in everyday products. UT Dallas showed that a THz receiver can be manufactured affordably, using standard Schottky diodes in 130nm CMOS with higher cut-off frequency than MOS transistors. More information about the research is published in “280GHz and 860GHz Image Sensors Using Schottky-Barrier Diodes in 0.13µm Digital CMOS,” presented at ISSCC. The research is funded through SRC and performed at the RF and THz laboratory of Texas Analog Center of Excellence at UT Dallas. The paper is co-authored by Ruonan Han, a former student of Professor O, and Yaming Zhang, Yongwan Kim, Dae-Yeon Kim and Sam Shichijo at UT Dallas. More information at www.src.org.

Smallest NAND Flash
Flash memory maker SanDisk Corporation (NASDAQ:SNDK) highlighted the smallest 128Gb NAND flash memory chip currently in production, on a 170mm2 silicon die, targeting smartphone and tablet integration. SanDisk built the 128Gb NAND flash memory chip on its 19nm process technology, using its three-bit per cell (X3) technology. At 19nm, SanDisk is deploying its 9th generation of multi-level cell (MLC) NAND products and fifth generation of X3 technology. The 128Gb semiconductor device has X3 write performance of 18MB/s using SanDisk’s advanced all bit line (ABL) architecture. The 128Gb NAND flash memory chip was developed jointly by teams from SanDisk and Toshiba at SanDisk’s Milpitas campus. The effort was led by Yan Li, director of Memory Design at SanDisk. More information at www.sandisk.com.

First use of resonant clock mesh technology in volume ICs
AMD implemented Cyclos Semiconductor’s low-power semiconductor intellectual property (IP) in the AMD x86 core for inclusion in Opteron server processors and client Accelerated Processing Units (APUs). The adoption of the Cyclos resonant clock mesh IP will reduce power consumption. AMD’s 4+ GHz x86-64 core code-named “Piledriver” employs resonant clocking to reduce clock distribution power up to 24% while maintaining the low clock-skew target required by high-performance processors. Piledriver is the first volume production-enabled implementation of resonant clock mesh technology, with no increase in silicon area or changes to the chip manufacturing process. Cyclos resonant clock mesh technology uses on-chip inductors to create an electric pendulum, or tank circuit, formed by the large capacitance of the clock mesh in parallel with the Cyclos inductors. The Cyclos inductors and clock control circuits recycle the clock power instead of dissipating it on every clock cycle. More information at http://www.cyclos-semi.com and http://www.amd.com.

Higher-power, more-efficient SAR ADC
imec and Renesas Electronics Corporation reported a successive-approximation register (SAR) analog to digital converter (ADC) with improved power efficiency and speed, targeting wireless receivers for next-generation high-bandwidth standards. The new SAR ADC architecture is much faster than traditional chips, with small form factor and low power usage (1.7mWatt), achieving high resolution (11b). The fully dynamic, two-step interleaved pipelined SAR ADC achieves 10fJoule per conversion step power efficiency at a sampling speed as high as 250MSamples/s. The ADC prototype has been manufactured in 40nm CMOS with a core chip area of 0.066mm2.

Also at ISSCC, imec and Renesas Electronics present a new way to connect the ADC architecture with the complete radio architecture. To improve the power efficiency of the total receiver system, and avoid issues related to large input capacitors in a voltage-domain ADC system, a 3.2-51.2m Siemens current domain variable-gain transconductor (VGA) was used to drive a charge-domain SAR ADC with no overhead. A 10b 10-80MSamples/s VGA-ADC prototype in 40nm CMOS achieves 70dB DR while consuming less than 5.45mA from a 1.1V supply.

Wireless sensor, organic electronics work
imec and Holst Centre are presenting 14 papers on low-power design for wireless communication and wireless sensor networks, and organic electronics. In one, Imec and Holst Centre, in collaboration with Panasonic, announced a 2.3/2.4GHz transmitter for wireless sensor applications compliant with 4 wireless standards (IEEE802.15.6/4/4g and Bluetooth Low Energy), fabricated in a 90nm CMOS process. The transistor consumes 5.4mW from a 1.2V supply (2.7nJ/bit) at 0dBm output, 3-5x times more power-efficient than today’s Bluetooth-LE solutions. Imec’s new transmitter saves at least 75% of power consumption by replacing several power-hungry analog blocks with digitally-assisted circuits. With the SD−DPA for the generation of the time-variant signal envelope, it is also the first published ultralow-power 2.4GHz-ISM band IEEE802.15.6-compliant transceiver. Check out the list and major highlights here.

Want to see your ISSCC presentation highlighted here?
Send an email to digital media editor Meredith Courtemanche at [email protected] with your presentation details.

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February 21, 2012 — Electronics System Integration Technology Conference (ESTC) 2012 seeks original papers describing research in all areas of electronic packaging, including LED packaging, flexible electronics, assembly and interconnect technologies, and more. ESTC takes place September 17-20 in Amsterdam, the Netherlands. Organized by IEEE-CPMT since 2006, in association with IMAPS-Europe, the ESTC conference series focuses on interconnect and packaging technologies for electronic system integration. Submit your abstract by April 1.
 
Paper abstracts may be submitted to the following tracks and application areas:

  • Assembly and Manufacturing Technology
  • Materials for Interconnect and Packaging
  • Reliability
  • Embedded Die and Wafer Level Packaging
  • 3D Integration Technology
  • Microsystem Packaging
  • Flexible and Stretchable electronics
  • Advanced and Emerging Technologies
  • Power Electronic Packaging
  • Optoelectronic Packaging
  • Thermal and Mechanical Modeling
  • Electrical Design & Modeling
  • Consumer Electronics
  • Automotive and Industrial Electronics
  • Avionics and Space Electronics
  • Medical Electronics
  • Solid State Lighting
  • Telecom System Electronics
  • Wireless Electronics
  • RF-ID and Smartcards
  • Display and Imager Electronics
  • Energy System Electronics

Submit a 300-500 word abstract that describes the scope, content and key points of your proposed paper. Abstracts must include results and graphics. Please visit www.estc2012.eu to upload your abstract. Submissions for poster presentations are also welcome. Submission deadline for abstracts is April 1, 2012.

ESTC will select the best paper and best poster presentations. For each, the author(s) will receive a personalized ESTC award and a monetary prize from the IEEE-CPMT Region 8 Director.

The official language of all presentations is English. All oral and poster presentation authors are invited to prepare a paper for the conference proceeding which will also be included in the IEEE XPLORE database after the conference.
 
Your submission must include the mailing address, business telephone number and email address of the presenting author and affiliations of all authors. All submitted abstracts will be reviewed by the committee to ensure a high-quality conference. At the discretion of the program committee, paper abstracts submitted may be considered for poster presentation. The work should be original and not previously published, and avoid inclusion of commercial content. Additional instructions about formatting the paper will be published on www.estc2012.eu.

Selected presenters will be notified on June 1, 2012. Final paper manuscript will then be due August 15, 2012.

Related story: Advanced packaging at the 2010 ESTC

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February 17, 2012 — Wright Williams & Kelly, Inc. (WWK), a cost & productivity management software and consulting services company, opened its 2012 semiconductor industry survey on equipment and process timing. Only participants will receive the full results, free of charge. Download the survey form at http://www.wwk.com/2012survey.pdf.  
 
The 2011 survey found double patterning lithography, through silicon vias (TSVs) and TSVs with copper fill, and high-k metal gate (HKMG) with HfO2 and ZrO2 likely technologies to be implemented on semiconductor fab lines in 2012.

Other expectations from the semiconductor industry included remote tool diagnostic capability from their equipment suppliers; manufacturing capacity, utilization and cycle time simulation; and implementation of 300mm prime advances.
 
Respondents did not expect to see 193 high-index immersion, direct-write, extreme ultra-violet (EUV), or imprint lithography in production until 2015 or later.

Take the 2012 survey: http://www.wwk.com/2012survey.pdf
 
Wright Williams & Kelly Inc. is an operational cost management software and consulting company serving technology-dependent and technology-driven organizations. WWK maintains long-term relationships with prominent industry resources including SEMATECH, SELETE, Semiconductor Equipment and Materials International (SEMI), and national labs and universities.  Its client base includes nearly all of the top 20 semiconductor manufacturers and equipment and materials suppliers as well as leaders in nanotechnology, micro-electro-mechanical systems (MEMS), thin film record heads, magnetic media, flat panel displays (FPD), solid state lighting/light emitting diodes (SSL/LED), and photovoltaics (PV).

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