Category Archives: 3D Integration

Will 22nm need a mid-node?


January 2, 2012

January 2, 2012 —  In 2011, the hot topic was whether semiconductor manufacturing would move to metal gate first or gate last. Today, this is still a hot topic, although I posit that everyone will use gate-last manufacturing at 20nm. Currently, 22nm is in production at Intel, the first company to implement gate last; others such as IBM and foundries like TSMC will also use it for 20nm manufacturing.

20nm manufacturing will be very difficult, which could extend the period for 28nm. A mid-node may be developed or a “loose 20nm structure,” because of the difficulty in obtaining acceptable yields. Essentially, we are at 28nm now and using gate first or gate last, but the industry will shift to a 20nm metal gate last approach, exclusively.

Gate first is similar to silicon gate technology because it is very extendable and very transferable from existing silicon gate technology. Gate last is very difficult because it is a completely new process structure using multiple film stacks. The focus for 20nm or a mid-node will be to drive improved device performance primarily for consumer products and that, in conjunction with technologies like laser spike annealing, will provide the optimum battery life.

For junction formation and leakage, there is a growing set of problems caused by using older technologies. As we progress to smaller features, laser annealing plays a much more important role in the structure’s performance by significantly lowering leakage. In addition, at these leading-edge device nodes, bump packaging, or flip chip, enables increased device performance while reducing the total package form factor by utilizing through silicon vias (TSV) for 3D stacking. At 20nm, over 90% of leading-edge logic chips will require bump packaging solutions. Memory companies are aggressively pursuing TSV technology to bring it to mainstream DRAM production for memory-on-memory technology in the next two years. In addition, silicon interposer solutions are gaining traction and I believe that at some version of the 28nm logic node, companies will use wafer foundries with silicon interposer technology to provide high-density wire interconnection. Packaging in general used to be driven by logic and the computing market segment. Moving forward, bump packaging will play an increasing role as we transition from laptops to tablets and from on-board disk drives to cloud networking. These devices will drive the change in technology.

With the many technology transitions that need to occur to move to the 22/20nm node, the transition to TSV 3D will ultimately decide the winner for the balance of this decade. Also, compounding the equipment manufacturers’ R&D investments will be the transition to 450mm diameter wafers, which will be driven by all the major semiconductor companies. By combining the technology challenges we face and the wafer diameter change, executives in the equipment industry will require a strong balance sheet to be successful.

Art Zafiropoulo is chairman and CEO of Ultratech Inc.

This article is part 7 of a series of 22nm forecasts from Solid State Technology contributors.

Part 1: Semiconductor process technology challenges at 22nm by Dean Freeman, Gartner

Part 2: At 22nm, leave chip layout to the experts by Gary Smith, Gary Smith EDA

Part 3: Focus on first order effects at 22nm by Howard Ko, Synopsys

Part 4: Mask-wafer double simulation: A new lithography requirement at 22nm by Aki Fujimura, D2S

Part 5: 22nm requires foundry-to-packaging-house cooperation by E. Jan Vardaman, TechSearch International

Part 6: Strained silicon and HKMG take the stage at 22nm by Mohith Verghese, ASM America

Part 8: Startups pave the way to CMP at 22nm by Michael A. Fury, Techcet Group

Part 9: 20nm mask technology relies on SMO and DPT by Franklin Kalk, Toppan Photomasks

Part 10: 3D integration key to 22nm semiconductor devices by Paul Lindner, EV Group

December 29, 2011 – At the recent 7th annual RTI 3-D Architectures for Semiconductor Integration and Packaging (3D ASIP) Conference in Burlingame CA, the "buzz" centered around the presentation by TSMC‘s Doug Yu, senior director of integrated interconnect, who repeated the case he had made at the November Georgia Tech Interposer Conference [see "2.5D announcements at the Global Interposer Tech conference"] for the pure foundry model for 2.5 and 3DIC — claiming that TSMC was readying to take on full beginning to end interposer manufacturing.

Yu told the audience of more than 200 that sharing the fabrication process with OSATs is not the preferred option for TSMC, because "the risk for the customer is too high […] therefore we [TSMC] will take full responsibility and accept full risk." TSMC is proposing that such one stop shopping will be simpler, cheaper and more reliable than using multiple sources (i.e. foundries, assembly houses and potentially other partners). Yu remained steadfast in his assessment that the required investments and the technology needed to handle thinned wafers would require that the foundries take control of such processing: "This is a new ballgame; the old ways of doing business are out of date for this new technology." On rumors that TSMC is currently working with only a handful of 2.5D/3D customers (including Xilinx); he indicated that "new customers will have only the integrated solution proposal […] some, but not all of them [customers] want us to work with other partners, but many like our new approach very much."

Certainly with customer Xilinx being first to enter the 2.5D market space, TSMC appears ahead of the rest of the foundries in this regard. Ivo Bolsens, VP and CTO of Xilinx detailed the company’s Virtex 2000T FPGA product which he claims delivers 4

December 27, 2011 — The Global Semiconductor Alliance (GSA) released "3D IC Architecture: A Natural Evolution," a report sponsored by Macronix International Co. Ltd. and Etron Technology Inc. GSA also published the second edition of the 3D IC Design Tools and Services Tour Guide.

3D IC Architecture covers 3D and 2.5D packaging technology: benefits, gaps in the current semiconductor ecosystem, barriers, applications, and ways to accelerate commercialization.

The Tour Guide compiles input from EDA, R&D, market research and services companies involved in the commercialization of 3D and 2.5D interconnect technology. The Tour Guide documents the 3D IC capabilities of these companies.

Also read: GSA awards semiconductor companies

"GSA provides a forum for key players in this complex semiconductor ecosystem and recognizes the need to support design and manufacturing standards as well as new business practices to accelerate 2.5D and 3D market adoption," said Jodi Shelton, president of GSA.

GSA also hosts forums on the packaging technologies, working group meetings, and other events. The Alliance also publishes articles on packaging trends. To participate in this important effort, please contact Wade Giles at http://www.gsaglobal.org/association/contact_form_wade.aspx.

The Report and Tour Guide are complimentary to GSA members and available for download at http://www.gsaglobal.org/publications/3dic/index.asp. Non-members may purchase the Report and Tour Guide through the GSA Store.

The Global Semiconductor Alliance mission is to accelerate the growth and increase the return on invested capital of the global semiconductor industry by fostering a more effective ecosystem through collaboration, integration and innovation. Internet: www.gsaglobal.org.

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December 27, 2011 — Small, mobile, Internet-connected devices are bucking the slow economy and use advanced packaging technologies to pack an enormous amount of functionality into a very small form factor, notes New Venture Research. The chip packaging method also determines the speed and performance of that chip, as well as its battery consumption.  

Advanced IC packaging technologies include system in package (SiP), stacked packages, fan-in quad flat pack no leads (QFN), fan-out wafer-level packages (WLP), and interconnection styles of 3D and 2.5D through-silicon vias (TSV) and flip chip. The use of these packaging technologies for mobile electronic devices is covered in New Venture Research’s Advanced IC Packaging Technologies, Materials, and Markets, 2011 Edition.

Stacked packages are essentially a vertical multichip package. They come in many forms, including die stacks, package on package (PoP), package in package (PiP), TSOP stacks, QFNs, MCMs, and WLPs. Now found in all cell phones, stacked packages are in a high-demand market. Stacked package revenue will experience a 10% compound annual growth rate (CAGR) through 2015.

TSVs/3D interconnect creates a die stack with short interconnection distance for high speed, low power consumption, reduced parasitics, and small form factor. Vias go through the silicon, electrically connecting the die vertically. It replaces wire bonds and other second-level interconnects. The identified potential markets for TSVs will grow from 35 billion units in 2010 to over 54 billion in 2015.

System in package (SiP) devices are a functional block, a system of electronics that combines functional units together onto a single substrate to enable the shortest electrical distance between parts for superior performance. This reduces the amount of traces going into and out of the package, enabling a more simplistic PCB for the final product and potentially reducing system costs.  Revenue for SiPs will expand at a 5.4% CAGR through 2015.

To increase the reach of the QFN package, fan-in QFN involves extending the number of rows of leads from the usual one to two or three rows. This allows hundreds of package leads, up from the 50 or fewer in a traditional package design. Although the number of fan-in QFNs assembled currently is quite small, the potential is huge, with a projected CAGR of 63.1% for revenue through 2015.

Reconfigured or fan-out wafer-level packages (FOWLP) were introduced in 2006. After devices are manufactured on a wafer, the devices are sawn and transferred on a carrier to another larger wafer that has gaps between die, which are filled with overmold material that also coats the back side of the devices for protection. This allows for a larger surface on which to extend a redistribution layer, thus allowing for far more I/Os than would be possible on the original smaller WLP surface. Solder balls or bumps can be added to this surface for interconnection to a printed circuit board (PCB). Fan-out WLPs are expected to have a CAGR of 15.9% for revenue through 2015.

Cellular handsets are the primary handheld electronic gadget globally, especially in areas too vast to support wired communication lines. Cellular handsets are growing at an 8.5% CAGR between 2011 and 2015, and smart phones, a subset of total cellular handsets, are growing at a 15.2% CAGR.

More information can be found on these topics and others in the new report, Advanced IC Packaging Technologies, Materials, and Markets, 2011 Edition, from New Venture Research at newventureresearch.com.

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December 19, 2011 — Powertech Technology Inc. (trading number:6239) has approved a tender offer of NT$25.28 per share for the common shares of Greatek Electronic Inc. (trading number:2441), with a minimum acquisition target of 166,061,377 shares, or 30% of the outstanding shares for Greatek. The maximum acquisition is set at 282,304,340 (51%).

Powertech can expect to spend up to NT$7.137 billion in the tender offer. The tender offer period runs through February 3, 2012 and must be approved by relevant competent authorities.

Greatek specializes in semiconductor packaging and test services, covering P-DIP, SOP, SOJ, SSOP, TSSOP, MSOP, QFP, LQFP, TQFP, PLCC, TO and QFN form factors. It boasts circuit probing and final test offerings, and owns 2 factories at Zhunan in Miaoli County, Taiwan (R.O.C.). Greatek employs 2500 people.

The deal would boost PTI’s logic-chip packaging portfolio. DRAM packaging is Powertech’s main business, Ken Liu of Taiwan-based China Economic News Service (CENS), notes, and the DRAM industry has suffered declines in recent quarters. Liu quotes PTI general manger Zhongji Liao as saying that the company will shift its logic packaging business to Greatek, which will operate as a independent manufacturer.

With the tender offer, Powertech plans to create a system of cross support of production between Powertech and Greatek, increasing market competitiveness and technological efficiency for various products and reducing costs for a total packaging process. The new alliance also is expected to increase consolidated revenue. Positive changes on enterprise value and return on equity of both companies is foreseeable, reports management.

Also read: Elpida, PTI, UMC finalize 3D IC partnership

Grand Cathay Securities is commissioned to serve as the financial adviser and PWC Legal is commissioned to serve as the legal consultant of offeror in the tender offer.

Powertech provides IC packaging, testing, and distribution. Powertech has more than 6,000 employees worldwide, with facilities at Hsinchu Industrial Park, Hsinchu Science-Based Park and Suzhou Industrial Park. Please refer to http://www.pti.com.tw for more information.

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December 15, 2011 — Licensing company Rambus Inc. (Nasdaq:RMBS) is engaging with the Industrial Technology Research Institute (ITRI) in Taiwan on the development of interconnect and 3D packaging technologies.

Initially, the companies will collaborate on the development of system integration using silicon interposer technology. Rambus joined the Advanced Stacked-System Technology and Application Consortium (Ad-STAC), a multinational research association led by ITRI. As Ad-STAC members, Rambus and ITRI will share ITRI

December 12, 2011 — SEMI is looking for presenters for technical sessions and other opportunities at SEMICON West 2012, July 10-12 in San Francisco, CA.

SEMICON West 2012 will feature more than 40 hours of technical sessions and presentations across three show floor technology stages — the TechXPOTs — focused on critical industry topics shaping design and manufacturing of semiconductors, high-brightness (HB) LEDs, MEMS, printed and flexible electronics, and other related technologies.

SEMI is soliciting technical presentations in topic areas including:

Wafer Processing:

  • Emerging Architectures for Logic and Memory
  • Advanced Materials and Productivity Solutions
  • Advanced Lithography

Test:

  • Probe Card/Handlers
  • Semiconductor Test Strategies
  • ATE
  • Adaptive Test

Packaging:

  • Contemporary Packaging Technology and Productivity Solutions
  • New Packaging Solutions
  • Packaging Materials
  • Trends and Opportunities in 3D-IC
  • Testability and Thermal Management of 3D-IC
  • Interposer Solutions for Packaging

"Extreme" Electronics:

  • Opportunities in MEMS
  • High-brightness LED Manufacturing
  • OLED Manufacturing
  • Printed and Flexible Electronics

Submit an abstract (maximum 500 words) focused on the latest developments and innovations in these technology areas, inclusive of supporting data. The deadline for abstract submission is March 15, 2012. Submissions may be made online from the SEMICON West 2012 website at:  www.semiconwest.org/Participate/SPCFP.

On-line submission for abstracts is now available at: www.semiconwest.org/node/8311. Contact Agnes Cobar at [email protected] with questions.

SEMICON West is an event for the display of new products and technologies for microelectronics design and manufacturing, featuring technologies from across the microelectronics supply chain, from electronic design automation, to device fabrication (wafer processing), to final manufacturing (assembly, packaging, and test), as well as emerging technologies. For more information on SEMICON West 2012, please visit: www.semiconwest.org  

SEMI is the global industry association serving the nano- and micro-electronics manufacturing supply chains. For more information, visit www.semi.org.

December 7, 2011 — Arteris Inc., network-on-chip (NoC) interconnect IP company, will incorporate its FlexNoC NoC interconnect IP into an SoC die on silicon interposer test chip with Taiwan Semiconductor Manufacturing Company (TSMC). TSMC recently approved additional spending on advanced packaging tech.

"TSMC chose to work with Arteris on the interposer based test chip program because its interconnect technology is ideally suited to addressing the SoC wire routing congestion and timing closure challenges," said Suk Lee, director of design infrastructure marketing at TSMC.

Arteris’s FlexNoC NOC interconnect IP is physically implemented as a distributed network of small design elements within a SoC floorplan. FlexNoC addresses bandwidth, latency, and quality of service (QoS) requirements introduced with wide data paths.

Arteris is a TSMC Open Innovation Platform Partner and a participant in TSMC’s Reference Flows 11.0 and 12.0.

Arteris Inc. provides Network-on-Chip interconnect IP and tools to accelerate System-on-Chip semiconductor (SoC) assembly for a wide range of applications. More information can be found at www.arteris.com.

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