September 7, 2011 – 3M and IBM say they are jointly developing a new class of material adhesives specifically for stacking and packaging semiconductors in layers of up to 100 separate chips. The resulting silicon "brick" could make chips 1000
Category Archives: 3D Integration
September 6, 2011 — Alchimer’s AquiVia film-deposition technology promises to cut fill deposition times and cost even with complex through-silicon via (TSV) 3D packaging structures. The product targets TSV ramp-up at production levels, according to the company.
The AquiVia TSV barrier-layer process provides uniform, 100% step coverage over complex silicon topography, including high-aspect-ratio vias with scalloped walls. Existing TSV etch technologies tend to create scalloping, steps, and other surface features that challenge subsequent film deposition coverage, said Claudio Truzzi, Alchimer chief technical officer (CTO), noting that vacuum-based deposition processes have failed to create high-quality barrier layers, "especially in deep, small-diameter vias with aspect ratios of 10:1 and beyond." The AquiVia barrier films demonstrate 100% coverage on sides and bottom of vias, even with stair-step patterns and scalloping.
The improved barrier layer, one of the bottom-most elements in the TSV film stack, enables subsequent depositions to be completed in less time and at lower cost, according to Alchimer. The coverage also eliminates certain performance and reliability problems that can occur during subsequent seed-layer and fill deposition, such as "electromigration, poor fill results, and high-resistance pathways in interconnect circuits," said Truzzi.
AquiVia Barrier and Alchimer wet deposition products offer conformality, step coverage and purity that reduce costs and improve performance over PVD, CVD, or other dry processes, according to the company.
Alchimer will be exhibiting with their Taiwanese partner, Kromax, at SEMICON Taiwan Booth 672, Sept. 7-9, 2011. Alchimer will present at a DigiTimes workshop on optimum 3D TSV structures and processes, on the afternoon of Sept. 7th at the Grand Hyatt, Taipei.
Alchimer makes chemical formulations, processes and IP for the deposition of nanometric films used in a variety of microelectronic and MEMS applications, including wafer-level interconnects and TSVs for 3D packaging. Visit alchimer.com.
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August 30, 2011 – SEMICON Taiwan (Sept. 7-9) approaches, the island’s most celebrated event for microelectronics manufacturing, coorganized by SEMI and the Taiwan External Trade Development Council (TAITRA), offers more than 60 programs and sessions and 550 exhibitors spanning the entire semiconductor value chain and related high-growth industries.
A "Market Trend Forum" will host five industry analysts with their takes on future trends in semiconductor markets from up and down the value chain: foundries, DRAM, packaging, and equipment/materials.
The SiP Global Summit presents the latest 3D IC developments from TSMC and ASE, and offers talks on test challenges, 2.5D-3D ICs, and device-embedded substrates, dubbed "the last mile" in heterogeneous integration in SiP packaging.
A gathering for celebration, to see and be seen: The 2011 Leadership Gala Dinner will honor TSMC’s Morris Chang, recipient of the 2011 Akira Inoue award, and we’re told that President Ma Ying-jeou will talk as well. Other invited guests listed are Vincent Siew, VP representing the ROC; Wu Den-Yih, Premier of the Executive Yuan; Yen-Shiang Shih from the Ministry of Economic Affairs (MOEA); and Taipei Mayor Hau Lung-Bin.
For networking, the CEO Forum presents a range of talks from top industry execs (Mentor Graphics, IMEC, Applied Materials, TSMC), addressing market differentiation, future "hyper-intelligent systems," equipment technology inflection points, and other silicon IC technology challenges and opportunities. And there’s the annual SEMICON Taiwan golf tournament and luncheon.
Other forums cover a range of hot industry topics:
– MEMS: Litho for 3D TSV MEMS, etching, simulation, test
– LEDs Cost and technology trends, manufacturing efficiencies, packaging
– Green Manufacturing: Reducing and efficiently managing consumption of energy, water, hazardous substances, waste, etc. Talks include ISO and SEMI standards, TSMC’s "total chemical management," pump/abatement, automation, etc.
– More: Manufacturing/design collaboration, CMP, secondary equipment, and a number of themed pavilions including a Cross-Strait and several national ones.
To learn more about the show and register, go to www.semicontaiwan.org.
August 29, 2011 — Foundry GLOBALFOUNDRIES entered into a strategic partnership with packaging house Amkor Technology Inc. (NASDAQ:AMKR) to develop integrated semiconductor assembly and test processes for advanced silicon nodes. The aim is integrated fab–bump–probe–assembly–test steps that can be commercialized across multiple customers and end-market applications.
Amkor is becoming a founding member of GLOBALFOUNDRIES’ Global Alliance for Advanced Assembly Solutions, formed to foster semiconductor interconnect, assembly and packaging technology innovation.
The integration of interconnect, assembly and packaging at advanced semiconductor nodes makes supply chain management more critical, as chip designers can exploit packaging technologies as part of the silicon development. 3D IC stacking is also an alternative to traditional technology node scaling at the transistor level. Chip-package interaction is becoming more complex. This was the topic of "Collaboration to Strengthen the IC Supply Chain," held at The ConFab 2011, in which Amkor and GlobalFoundries gave presentations. Read summaries from the talk in More Moore & More than Moore require fabless, foundry, and packaging houses on board.
The companies also recently expanded their lead-free wafer bump licensing relationship by amending their existing lead-free bumping technology license agreement.
The joint development effort on advanced packaging will target lower costs, faster time-to-volume, and reduced technical risks, said Gregg Bartlett, senior vice president of technology and research and development at GLOBALFOUNDRIES. Dr. Robert Darveaux, Amkor’s corporate vice president, technology and platform development, noted the value of major packaging and foundry companies working together, serving "our common customers."
GLOBALFOUNDRIES is a full-service semiconductor foundry with a global manufacturing and technology footprint. For more information, visit http://www.globalfoundries.com.
Amkor is a leading provider of semiconductor assembly and test services to semiconductor companies and electronics OEMs. More information at www.amkor.com.
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August 24, 2011 — The SMTA will host sessions and courses with Amkor, Research in Motion, and TechLead Corporation on package-on-package (PoP) 3D stacking at SMTA International (SMTAI), October 16-20 in Fort Worth, TX.
Lee Smith, Amkor Technology, will present "Package on Package (PoP): Past, Present and Future" during the opening session on October 18. Assemblers have integrated PoP surface mount stacking increasingly over the last 5 years, notes Smith. Smartphones and tablet computers rely on PoP for signal processing and memory architectures. Over 11 million packages are surface-mount-stacked each week, he adds. The session is open to all attendees.
Also plan to attend "Assembly Solutions for Next-generation Package on Package (PoP) Requirements and Process" and "Reliability Characterization of PoP Materials and SMT Processes," chaired by Lee Smith of Amkor Technology and "Process and Reliability Characterization of PoP Materials and SMT Processes," chaired by Sheldon Schwandt of Research In Motion.
"Assembly Solutions for Next Generation Package on Package (PoP) Requirements and Process" and "Reliability Characterization of PoP Materials and SMT Processes" will feature Intel Corporation, Qualcomm, and Rambus Inc. speakers.
"Process and Reliability Characterization of PoP Materials and SMT Processes" speakeres include Amkor Technology, Flextronics, and Universal Instruments Corporation.
Charles Bauer, Ph.D., TechLead Corporation, will instruct a half-day tutorial, "3D Assembly…CSP to PoP to Board," covering fundamental to advanced technologies for stacked chip packaging and assembly, as well as stackable packages. Topics include the challenges of die thinning and thin die attach, mixed technology die attachment and bonding, flip chip, multi-level wire bonding, TAB and TSV technologies.
Details about SMTA International can be found online at http://smta.org/smtai.
The SMTA membership is an international network of professionals in microsystems, emerging technologies, and related electronic assembly business operations.
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August 17, 2011 — The annual Known Good Die (KGD) conference will address semiconductor die testing, assembly, manufacturing, and business challenges, with the tagline "KGD in an Era of Multi-Die Packaging and 3D Integration." The KGD Conference takes place November 10 in Santa Clara, CA.
The event is co-located with another MEPTEC event, "2.5D, 3D and Beyond: Bringing 3D Integration to the Packaging Mainstream," set for November 9.
"Multi-function 3D, vertically stacked or multichip packages" are increasingly incorporated into mobile consumer products, such as tablets and smartphones, notes Jonathan Davis, president of the Semiconductor Business Unit at SEMI, which co-presents KGD with MEPTEC. Complex package configurations rely heavily on KGD to meet functionality, time-to-market, and cost goals.
For 18 years, the KGD conference has marshaled technical experts, managers and business development professionals from around the world for an interactive exchange on the latest developments in the die product industry.
The KGD conference sessions will cover such topics as KGD test, handling, delivery, standards, current methods, options and infrastructure.
For more information on the Known Good Die conference, visit: http://meptec.org/meptecknowngoodd.html.
SEMI is a global industry association serving the manufacturing supply chains for the microelectronic, display and photovoltaic industries. For more information, visit http://www.semi.org.
MEPTEC provides a forum for semiconductor packaging and test professionals to learn and exchange ideas that relate to assembly, test and handling. For more information, visit http://meptec.org/.
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August 16, 2011 — The 2011 iNEMI Roadmap, published by the International Electronics Manufacturing Initiative (iNEMI), includes a new chapter on micro electro mechanical systems (MEMS) and sensors, and an expanded chapter on packaging to include substrates discussions.
This issue also includes more input from international (outside of North America) participants than in prior years.
MEMS devices are expected to see exponential growth, expanding into sensors, fluidics, RF components, expanded gyroscope capabilities for motion-gesture sensors, and more applications. This variety is impeding standardization in the MEMS sector. Different functionality needs push MEMS devices into customization more than standardization. Scalable manufacturing processes, packaging technologies, cost-effective and non-destructive test technologies are needed, as well as a better basic understanding of MEMS failure mechanisms. Resonator performance must also be improved.
3D packaging affects a broad range of electronics manufacturing operations, and is discussed in many areas of the Roadmap. Increased momentum in the move toward 3D packaging — through-silicon vias (TSV), thinner die, high-density interconnect (HDI), die shrinkage, embedded actives and passives — creates issues up and down the supply chain, affecting assembly processes and equipment, design and simulation tools, reliability methodologies, thermal management strategies and cooling technologies, and test and inspection strategies.
The Roadmap also acknowledges ongoing challenges for R&D funding, resulting partially from an electronics industry move from vertically integrated OEMs to a multi-firm, globally distributed supply chain. IC assembly, passive components, and electronics manufacturing services have "critical need" for research and development. Industry collaboration is gaining traction in university R&D centers, industry consortia, ad-hoc cross-company development teams, and other areas. Government, academia and industry consortia will need to formulate ways to adopt and develop emerging technologies within the global outsourcing environment.
The more than 575 individuals who contributed to the 2011 Roadmap represent over 310 corporations, consortia/associations, government agencies and universities, located in 18 countries. The 2011 Roadmap is free for iNEMI members and is for sale to non-members, with special discounted pricing available for universities, research institutions, government agencies and non-profit organizations. For the first time, individual chapters are available for sale and can be purchased on, and downloaded from, the iNEMI website. The 1800-page document features 27 chapters that provide in-depth discussion of six product sectors and 21 different manufacturing, component/subsystem, business process and design technologies. For information about purchasing options and pricing, go to http://www.inemi.org/node/1863/buy
The International Electronics Manufacturing Initiative
August 12, 2011 — SEMI will hold the first-ever SiP Global Summit, September 7-9, co-located with SEMICON Taiwan. Three forums cover system in package (SiP) test, the "3D IC era," and the requirements of mobile electronics.
Participants will include ASE, Qualcomm, Sony, TSMC, Verigy; and R&D and market research organizations including Gartner, Fraunhofer IZM, IMEC, Yole Development and ITRI.
SEMI cites mobile electronics — smartphones, e-book readers, etc. — as a major driver for SiP heterogeneous architectures. An ITRI recent forecast indicates that production value of 3D-ICs for mobile phone applications will hit $3.65 billion by 2015.
Three major forums comprise the first SiP Global Summit: 3D-IC Test Forum, 3D-IC Technology Forum and Embedded Substrate Forum. Representatives from 25 firms will speak on 3D-IC, TSV, silicon interposer and embedded substrate technologies.
The test section — 3D-IC Test Forum: Finding Heterogeneous Integration Solutions — will outline package test challenges that inhibit yields. Executives from ASE, KYEC, and Qualcomm will discuss 3D TSV challenges and cost strategy from the operators’ perspective. FormFactor and Teradyne executives will discuss how equipment makers attack the challenges facing test operators.
3D-IC Technology Forum: Ringing in the 2.5D- and 3D-IC Era will cover the transition from 2D form factors into the Z space. How will packaging houses balance performance optimization, time-to-market expedition and cost reduction? Speakers will discuss different materials, equipment, process nodes, and product standardization and commercialization methods. Organized by IMEC and SEMI, this forum gathers presentations by ASE, IEEE-CPMT, IMEC and Xilinx.
The Embedded Substrate Forum: Last Mile to a Heterogeneous Integration forum will feature R&D staffers from Nokia, who will discuss the differences between packaging substrates, module substrates and motherboards with an eye on mobile technologies. TechSearch International will also share information on the embedded substrate developmental trend.
Free registration for the event is available at www.sipglobalsummit.org
"Cost control, design, mass production, and testing" need improvements as commercialization ramps up, noted Dr. Ho-Ming Tong, general manager and chief R&D officer of ASE. Deployment of silicon interposer, or 2.5D IC, technology is expediting migration from the 40 to 28nm node. "Commercialization of 2.5D- and 3D-ICs may take place in 2013," says Tong.
SEMICON Taiwan, held simultaneously with the SiP Global Summit, will feature the Advanced Packaging/Testing Gallery sponsored by ASE and KYEC, showcasing cutting-edge testing/packaging technologies and applications. Learn more at http://www.semicontaiwan.org/en/
SEMI is a global industry association serving the manufacturing supply chains for the microelectronic, display and photovoltaic industries. For more information, visit www.semi.org.
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August 12, 2011 — Laurent Malier, CEO of Leti, described the research group’s work and the outlook on fully depleted silicon on insulator (FDSOI), 3D packaging technologies, and integrated photonics on silicon (Si photonics), in a video interview at SEMICON West 2011.
Malier says performance data at 22nm shows FDSOI is comparable to FinFET with respect to the speed gain and low power performance. FDSOI technology is also easily manufactured and it’s ready for scale down to 11nm, Malier notes.
Leti also recently demonstrated 3
August 10, 2011 – Ron Huemoeller, SVP of advanced 3D interconnects at Amkor, participated in two panels at SEMICON West 2011: 2.5D silicon interposer packaging technologies and supply chain, and 3D packaging technology and the ecosystem. He shared his thoughts on the panel topics during a video interview at the show.
Among the issues Huemoeller sought to emphasize via the 2.5D panel is the importance of silicon interposers, the timeline with respect to their integration, and the assembly and supply constraint challenges. With respect to the latter, he said the industry is suffering from a lack of supply on the part of interposers, which could negatively impact the industry with respect to product timing and the release of products. Furthermore, there are hand-off issues that take place from the interposer side to assemblers (e.g., chip/package interactions).
In going from 2.5D to 3D packaging technology, Huemoeller explained that the industry needs to have the right design tools in place, i.e., EDA tool sets and the software. Still another challenge is the thermal issues that emerge when stacking die. "The 3D sector has not addressed these thermal issues," he said, whereas, "the 2.5D sector has addressed these nicely." A second problem is how cost will affect the dovetailing of products into one to meet customer timing requirements. He anticipates that 2.5D technology will remain in play for a long period of time. 3D technology should start to come into play with the smart phone sector, followed by larger die sector/higher power applications in the latter part of this decade. "[3D] probably won’t be fully adopted until 2019/2010, primarily because of the software issues," he said.