Category Archives: 3D Integration

August 4, 2011 — Ludo Deferm, IMEC, came to SEMICON West with several major announcements, from the system level to the layers of semiconductors. IMEC’s major interests include scaling with 3D technologies, selective epitaxy, RRAM, lithography, and more.

 

Hot spots create charge losses in stacked chips. Stacking is nice, but if it creates memory losses, it cannot serve the industry, Deferm points out. Heat-spreading through silicon vias may be the answer to this problem. SEMICON West allows imec to bring problem resolutions like this to the design community.

For semiconductor device structures, scaling always has its limits. To get around that, imec developed an implant-free silicon germanium (SiGe) quantum well device. Selective epitaxial growth allows reduced lateral resistance. The channel control is much better, and the structure is scalable, but developments are still ongoing, especially on the PMOS/NMOS interaction.

In memory activities, imec is working on resistive RAM (RRAM) endurance (number of cycles) and materials, and new materials for the metal insulator/metal capacitor for DRAM to reduce leakage. The goal is smaller, denser memory with the same kind of capacity as larger generations.

Deferm also speaks about the lithography tool ASML delivered to imec in Marchl. They are using it for EUV litho exposures and a laser-assisted discharge plasma (LDP) source. These trials are headed for 60 WPH on the tool by 2012. Imec also is working on mask cleaning for EUV.

Wrapping up his talk, Deferm covers industry collaborations in 450mm production tool development, 3D integration, and new devices. Big equipment suppliers having to "do it all" in areas of new technologies, such as EUV and 450mm, want help from IDMs sharing the burden. Collaborations in 3D packaging is more related to applications than economics, and therefore collaborations are different. FinFETs and other new device architectures are only going to be used if neccessary, Deferm predicts, so it will come later than expected.

July 28, 2011 — Texas Instruments Incorporated (TI, NYSE:TXN) has shipped more than 30 million units of its PowerStack packaging technology, a combination of chip stacking and clip bonding that is designed to improve performance and chip densities in power management devices.

In PowerStack, TI’s NexFET power MOSFETs are stacked on a grounded leadframe. Copper clip bonds connect the I/O voltage pins. The packaging technology enables heightened integration in a quad flat-pack no-lead (QFN) form factor. This 3D packaging cuts down on package area by as much as 50% (compared to side-by-side MOSFETs). The package’s thermal performance, current carrying capability, and effeciency are supported by this design.

PowerStack is in volume production at TI’s Clark facility, which is the company’s newest semiconductor assembly and test facility (Philippines). TI will expand capacity for advanced packaging at Clark in 2011, "nearly doubling initial capacity," added Bing Viera, managing director of TI Philippines.

The company is targeting PowerStack for computing and telecommunications applications that must handle higher loads, from "broadband mobile video and 4G communications…and take up less space," said Matt Romig, analog packaging at TI.

Texas Instruments makes semiconductors. Learn more at www.ti.com.

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July 26, 2011 — 3D semiconductor packaging processes involve various groups, and standards are important in the hand-offs between them, explains Mark Berry, sales director at Metryx. He covers how to use metrology to protect wafer yields in 3D packaging.



Berry spoke to ElectroIQ in a podcast interview at SEMICON West 2011 this month in San Francisco, CA.

"People who are receiving wafers need something they can benchmark," said Berry. Towards the end of the through silicon via (TSV) process, "if you take too much silicon off the wafer, you going to take the dies with it…and if you take too much silicon off the wafer, you’ll expose the circuitry." Metrology has to play a role in controlling wafer processing to achieve yields that make 3D ICs cost-competitive, he said.  

Another concern with 3D semiconductors is that the end user already has placed a lot of value in the wafers by the time TSVs are formed, noted Berry. Because the transistors have already been made, if the relatively simple and inexpensive 3D packaging process fails, then end users are writing off a lot of product. "But you don’t want to spend a lot of money in putting the metrology into place to get it right," so the key thing is "a balance between managing the process, understanding how the process flows, measuring at the right points so you know where the failure events will be so you can select them and control them, but not overdoing the metrology," Berry concludes.

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July 26, 2011 – Despite the evolving confusion with other "3D" technologies, 3D IC integration has been making significant commercial strides in the last 12 months because many think it will ultimately be the low-cost, high-performance solution.

Care should be taken when searching the 3D literature these days because confusion has arisen in the news media when discussing 3D integration (with through-silicon vias), 3D packaging (i.e. package-on-package), 3D for TV (stereoscopic 3D) and "3D IC" (the latest name for Intel’s finFET transistor structure).

When examining the commercial introduction of 3D integration (with TSV) one must remember that ultimately the acceptance of new technology introductions always come down to economics and ROI. When determining the valuse of 3D integration one must compare it to the costs of the manufacturing facilities for the "next node" . Fab costs for the 22nm node are expected to approach $6B, leaving few logic or memory IDMs or foundries who can afford such costs.


Fab start-up cost comparison in US $M. (Source: GlobalFoundries)

For example, one can see that the number of players in each succeeding generation of logic node has been diminishing rapidly.


(Source: IBS, at SEMI Industry Strategy Symposium [ISS], Jan. 2010)

In addition, with design costs approaching $100 MM at the 22 node, the production volume needed to absorb design NRE keeps increasing, making use of that node limited to high volume products that can absorb such costs.


(Source: Gartner)

Thus, it is the conclusion of many practitioners that next generaton designs will move to 3D IC with TSV because they will be the low cost, increased performance solution.

Certainly, a look at the headlines since last June generated by some of the major players led by Xilinx, TSMC, Elpida and Samsung, clearly show 3D integration is entering the commercialization stage. How far it will go towards becoming a commodity technology will depend on the accuracy of the aforementioned economic considerations.

July 25, 2011 – At this year’s SEMICON West, 100+ attendees gathered at the Suss MicroTec workshop "3D Integration: Are we there yet?" to hear technical experts from around the globe to present updates on the status of 3D technology.

Eric Beyne of IMEC addressed the technical issues of carrier systems for 3D through-silicon via (TSV) thinning and backside processing, pointing out that right now silicon carriers are favored over glass because: (1) the glass must be CTE matched to silicon over a large temperature range, (2) the high cost of ground to tight TTV specification, and (3) a negative effect on plasma-based post-grinding backside processes due to its low thermal conductivity. After alignment and temporary bonding, Beyne recommends the use of use of in-line metrology to insure bonding integrity before grinding occurs.

Rama Puligadda, division manager for advanced materials R&D for Brewer Science, indicated that their Zonebond room-temperature debonding process is meeting all customer requirements and is moving towards full commercial introduction. The Zonebond process basically uses a 2.5mm ring of adhesive to hold the wafer in place for grinding and backside processing. This allows for easier subsequent debonding. The thin wafers are released from the carrier at room temperature after mounting on a film frame.

Stephen Pateras, product marketing director at Mentor Graphics, pointed out that TSVs can be used to create test access paths so that all BIST resources can be accessed on any device. Pateras also concludes that all EDA players need to support common test access infrastructures since this will be required to stack die from difference sources.

Eric Strid of Cascade Microtech revealed that the company is producing lithographically printed probe cards by MEMS techniques capable of 6

July 21, 2011 — Steve Lerner, CEO of Alchimer, discusses the company’s latest suite of through silicon via (TSV) technologies in a podcast interview at SEMICON West 2011.

Earlier this year, Alchimer announced a new wet-deposition process, AquiVantage (see figure), that grows interconnect layers for interposer redistribution layers (RDLs) and enhances via-last backside wafer interconnects. The new process provides concurrent wet deposition of TSV and front-side isolation, barrier, and copper fill/RDL, while eliminating chemical mechanical polishing (CMP) and dry deposition steps. It also supports smaller vias with higher aspect ratios. On the backside, the process allows selective maskless growth of the on-silicon isolation layer, completely eliminating an entire expose/develop/etch/clean lithography-process cycle. Lerner discusses how the new technology reduces costs. "It’s an agnostic platform that can be transferred to existing assets rather than constructing new equipment," said Lerner.

Figure. Top part of a SEM cross-section highlighting the concurrent growth of TSV and RDL isolation and barrier, as well as the concurrent TSV Cu fill and RDL Cu seed deposition. The SEM inlens method used for this photo shows a high contrast between the polymer isolation and the metallic materials.

According to company, overall, interposer cost savings of more than 50% are achievable with the new process. The technology also accommodates thicker wafers, eliminating the need for wafer carriers and allows for highly scalloped via structures and faster etching times.

July 19, 2011 – Management of mechanical stresses is one of the key enablers for the successful implementation of 3D integrated circuits using through-silicon vias (TSVs). The stress-related impact of the processing done at the various companies in the manufacturing supply chain needs to be characterized and shared, and designers need a DFM-like solution for managing stress.

In conjunction with SEMICON West, SEMATECH and Fraunhofer IZFP hosted "Stress management for 3D ICs using through silicon vias: Product-level reliability workshop" to address product level considerations for dealing with stress-driven reliability mechanisms of the via-middle through-silicon-via (TSV) 3D stacking technologies. On Thursday, July 14, technologists and technology managers from various companies and institutions in the US, Asia, and Europe gathered to examine what is required at the product level to managing stress in 3D interconnects, and to drive consensus and support for these techniques across the industry.

In a series of invited talks, speakers discussed the following:

  • Keynote presenter Mark Nakamoto of Qualcomm shared a high-level perspective of product reliability and new risks associated with the use of new features: TSVs and microbumps, new materials and processes, and new chip package interactions using thinned die and hard microbumps.

  • Eric Beyne of IMEC presented on failure analysis challenges and techniques including X-ray tomography, magnetic current imaging, time domain reflectometry, photon emission microscopy, SAM, lock-in thermography, IR, and SAW based techniques.

  • Ron Huemoeller of Amkor discussed some of the new failure mechanisms that might not be addressed by traditional package qualification tests, and concluded that a paradigm shift in engineering for reliability is needed.

  • TSV intrinsic reliability and reliability qualification challenges was presented by You-Wen Yau of Qualcomm CDMA Technologies.

  • Suresh Ramalingam of Xilinx discussed the current status of reliability testing, stress simulations, and failure mode analysis for his company’s Stacked Silicon Interconnect Technology.

In the afternoon, a working session focused on discussing failure mechanisms, test structures, material characteristics, measurement techniques, and modeling techniques.

On Wednesday, October 12, in conjunction with SEMICON Europa, a sixth workshop, hosted by Fraunhofer IZFP in collaboration with SEMATECH, will focus on reliability-limiting degradation kinetics.

SEMATECH is hosting a 3D Interconnect wiki site to provide a forum to the community to discuss the issues raised in these workshops.

July 14, 2011 — Jonathan Davis, SEMI, chats about standards development in 450mm and 3D IC, as well as the importance of collaboration, and how it is happening at SEMICON West.

There are a lot of options to continue semiconductor advancement, but they all require collaboration. Complexity is the word, Davis says. SEMICON West is a key event to bring parts of the industry together, in everything from SEMI standards meetings to exhibit hall meetings.

SEMI recently started a task force for 3D IC. In 450mm standards dev: 5 standards are available, 11 are in the pipeline, and more were discussed at SEMICON West. There is "substantial movement" in 450mm exploration, Davis notes. More specific declarations are coming out now, compared to a year ago, from the suppliers and chipmakers with 450mm on their company roadmaps.

Davis also discusses the semiconductor industry investment forecast, which his colleague Dan Tracy addresses here.

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July 14, 2011 — Sitaram Arkalgud, director of interconnect at SEMATECH, co-moderated a session on 3D perspectives and development of the infrastructure during the 3D TechXPOT session at SEMICON West ("3D in the Deep Submicron Era," July 13 at 1:50PM]).

Arkalgud discusses the high-volume manufacturability issues and gaps in both 2.5D and 3D semiconductor technologies with respect to backside processing and wafer bonding, thinning, and handling. The figure is a summary of SEMATECH’s results from its survey on gaps in the via-mid ecosystem.



In the podcast, Arkalgud reports on the efforts that have gone into developing a kind of "dashboard" for standardization efforts being undertaken by SEMATECH’s 3D Enablement Center, SEMI, and other standards bodies/organizations such as IEEE, JEDEC, and Si2. He also discussed the anticipated timeline for 3D TSV applications and volume manufacturing (see the chart).

Chart. 3D TSV outlook. SOURCE: SEMATECH
– 12 companies surveyed Aug-Sep 2010: IDMs, foundries, fabless, OSATs
– High density via-mid applications including interposers, heterogeneous stacking, logic on logic, memory on memory; 2011-2014 timeframe
– Addresses all aspects of via-mid: wafer processing, assembly, reliability, inspection/metrology, design, test
– Highest priorities for heterogeneous stacking (e.g., wide IO DRAM) shown below

Gaps in Standards and Specifications
EDA Exchange Formats: Partitioning and floorplanning; Logic verification; Power/Signal integrity analysis; Thermal analysis flow; Stress analysis flow; Physical verification; Timing analysis

Reliability: Reliability test methods

Test: DFT test access architecture

Inspection/metrology: TSV voids, defect mapping, microbump inspection and coplanarity

Chip Interface: Stackable memory pin assignment; Stackable memory physical pinout

TSV: Keep out area, fill materials, dimensions

Thin wafer handling: Universal thin wafer carrier

Technology Development and Cost Reduction
Reliability: Criteria; Test methods; ESD

Temporary bond/debond cost reduction: Materials and release mechanisms cost reduction; Equipment cost reduction

TSV: Keep out distance/area

 Microbumping and bonding: Pad metallurgy and layer thickness; Bump metallurgy

Inspection/metrology: Microbump inspection and coplanarity; TSV voids; BWP voids

Test: Probing microbumps cost reduction

SEMATECH has been busy at SEMICON West 2011:

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July 13, 2011 – JCN Newswire — Mitsubishi Heavy Industries Ltd. (MHI) developed a fully automated 8" wafer bonding machine that bonds large-scale integration (LSI) circuits at room temperature, creating 3D ICs. Its fast atom beam (FAB) gun irradiates atoms to activate material surface bonding.

Previous room-temperature wafer bonding systems used ion guns, which could not acheive 8" wafer bonding. Whereas an ion gun radiates an argon ion beam, a FAB gun radiates a neutral atom beam of argon, which acheives about 20x greater energy per particle. The FAB gun removes oxide films on the bonding metal material’s surface. MHI’s supporting beam radiation technology also helps evenly activate the entire 8" wafer. Results show robust metallic electrode bonding for 3D integrated LSI circuits.

The process works with silicon and various metals. By eliminating heat stresses, the machine makes a wider range of materials available for 3D packaging. The room temperature process leads to a rigid, reliable bond in less time than a heat/cool process.

The system’s cassette holds 20 8" wafers and can perform wafer conveying and alignment for bonding automatically. The machine set preliminary bonding conditions for each wafer individually in high mix environments.

MHI is now looking to develop this technology for 12" wafers.

Mitsubishi Heavy Industries, Ltd. (TSE: 7011, ‘MHI’) makes heavy machinery. For more information, please visit the MHI website at www.mhi.co.jp.

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