Category Archives: 3D Integration

May 19, 2011 – Package-on-package (PoP) provides a cost/performance solution that solves business and logistics issues associated with stacking devices directly. 3D through silicon vias (TSV), with its associated manufacturing and test uncertainties, and questions about who handles what in the supply chain, cannot yet meet PoP’s benefits, says TechSearch International (TSI).

Memory and logic packages can be tested separately before assembly with PoP. Standardization of the top memory package footprint allows memory packages from various suppliers to be interchanged. Memory devices are wire bonded in the top package, but the logic device in the bottom package is migrating to flip chip, including copper pillar.

Package-on-package (PoP) volumes continue to grow with a CAGR of 31% from 2009 to 2015. Applications driving this double-digit growth include mobile phones (especially smartphones), tablets, games, iPods, and digital cameras. "This high growth and broad adoption has been driven by the continuous advancements that PoP has delivered. When Amkor ramped PoP in 2005, the mobile processor clock was 330MHz with a 0.65mm pitch interface to the top SDRAM/NOR combo memory. Now, processor speeds exceed 1 GHz with a 0.4mm pitch interface to the top low power DDR, with near term roadmaps exceeding 2.5 GHz and high-density PoP interfaces supporting two channel LP DDR2. With more than four billion mobile processors forecasted for smart device applications in the next four years, PoP growth and advancements will continue at a high rate," stated Lee Smith, VP of marketing and business development at Amkor Technology.

The latest issue of TechSearch International’s Advanced Packaging Update contains a unit forecast for PBGAs, TBGAs, and CBGAs. Forecasts for FBGAs, QFNs, flex-substrate CSPs, and stacked die CSPs are also provided. Market estimates for each package type are based on input from both captive and merchant assembly operations. Key applications and drivers for unit volume growth are highlighted. The report also includes an analysis of the impact of the tragic events in Japan on the electronics industry infrastructure. A special section provides insights into packages for automotive electronics. Included in the Update Service is a complimentary set of PowerPoint slides.

TechSearch International, Inc., founded in 1987, is a market research firm specializing in technology trends in microelectronics packaging and assembly. For more information, visit http://www.techsearchinc.com

Subscribe to Solid State Technology/Advanced Packaging.

Follow Advanced Packaging on Twitter.com by clicking www.twitter.com/advpackaging. Or join our Facebook group

by Pete Singer, editor-in-chief

May 19, 2011 – At this year’s The ConFab, held May 15-18, in Las Vegas Nevada, a recurring theme was that 3D integration shows tremendous promise, particularly with many fabless companies, yet many barriers remain. "We firmly believe 3D will provide a better form factor and better system level performance," said Nick Yu, VP of technology development at Qualcomm. He believes that smart phones and the demand they create for wide I/O memory stacked on logic could be the key enabler for through-silicon via (TSV) technology. "We really think it can bring the best of all worlds into your mobile handset," he said. "We think the smart phone space is really the right application for 3D TSV stacking." Growth in this market drives a lot of volume, which will drive down the cost and drive adoption, thus justifying the industry’s investment.

How soon does all this happen? Yu said Qualcomm is pushing for implementation by 2013, and that over the last four years they have already completed a lot of engineering work with the supply chain and demonstrated the concept. It’s a little bit of a "chicken-and-egg" situation, he noted, because a driver product is needed to acquire process learning and drive the product ramp, but there are "no real show-stopper or intrinsic technical issues," he said.

Wide I/O memory on logic provides significantly more bandwidth. The memory industry’s view is that as smart phones blur the lines between tablets and hand laptops, demand for memory bandwidth will be nearly insatiable. To enable that, standards are needed and JEDEC is going to finish the wide memory standardization by the end of this year. Memory vendors will have parts sampling in 2012, all targeting end-product going to market by 2013, according to Yu.

What’s not quite there yet, though, according to Yu and other presenters at The ConFab, is the 3D supply chain. "3D really ties a lot of other players together and it has this really complicated cobweb type of relationship," he said. "It is, in a sense, quite disruptive to the supply chain. That’s certainly one of the major challenges for a fabless company like Qualcomm. We’ve been spending a lot of time and resources to work with the supply chain for the last four years on this."

Qualcomm has a clear vision of what the product looks like, and that the architecture has already been optimized, Yu explained. The next step is to implement that in the manufacturing process — and therein lies the rub. "I think there are some integration challenges out there that we haven’t quite fully resolved," he said. "We need some sort of standards and conventions between the supply chain hand-offs." One example is the quality of a stack of known good die (KGD). "If we have a stack of memory, what is meant by a known good stack of memory? Who’s going to be responsible for the test, and what’s the quality of it?" All these discussions need to happen between the supply chain partners, with "huge implications" for their balance sheets, he noted.

Other business model questions: Who ultimately owns the dies? Who owns the inventory? And does the "pass-through" business model work? How is it going to be funded? Who owns the integration process in the end, and who owns yield? There are no easy answers.

The good news is that companies such as Qualcomm appear to be committed to making it work. "We really thought about all those challenges and we’ve set out to work with the industry, leveraging some of the standards bodies and really pulling together different players in the supply chain to work through that," Yu said. "There’s a lot of good will and intent in the industry, but I don’t think there’s enough leadership." Certainly SEMATECH has a strong program underway, but like everything else, it takes people like YOU to get involved.

May 18, 2011 — For the first time, the semiconductor industry is moving to 3D device structures, such as through silicon vias. This is significantly different than moving to thinner devices, says Raj Jammy, SEMATECH, at The ConFab 2011. He speaks with senior technical editor Debra Vogler.

Conformality of the gate dielectric, conformality of the contacts, and design all come into play. Semiconductor makers must still create robust and high-yield devices to be sucessful.

The biggest challenges for high-volume manufacturing of through silicon vias (TSV), Jammy says, are all through the process flow. Bonding and de-bonding is one major example, with poor throughput. Materials stresses, especially on thinned dies, are another.

SoC technologies are on the verge of some significant changes, Jammy predicts. For example, an entire smartphone could be fit onto one SoC. With system in package (SiP), additional functionality will be integrated, even MEMS devices.

Jammy also reviews SEMATECH’s roadmaps for logic and memory.

Read a summary of Jammy’s ConFab 2011 presentation on new device architectures.

by John Behnke, VP of worldwide sales and marketing, Intermolecular Inc.

May 18, 2011 – Another eventful (but still rainy) day at the SEMI/IEEE Advanced Semiconductor Manufacturing Conference (May 16-18), bookended by the two highlights: an information-rich and wide-ranging keynote talk by Gary Patton, VP of the semiconductor R&D center in IBM’s systems and technology group, and a panel discussion on "Models for successful partnerships in semiconductor manufacturing." (Before getting into those, Monday evening’s poster session was quite good, with lots of productive interaction; it brought out the international composition of the attendees, with Europe and Asia well-represented. Plenty of good posters were on display; it was difficult to pick the best one, and there will likely be several in close competition for the award.)

Patton’s keynote was remarkable for both scope and depth: he incorporated an unbelievable amount of high-level industry perspective and technical depth into less than an hour. He noted that there are now something like a trillion devices connected to the Internet, with 2 billion people online and some 4 billion using mobile devices generating 225,000 terabytes of data a month. Teenagers send an average of 100 text messages per day, he added — this actually seems low, based on what I see my daughters doing.

On the technology side, Patton noted that device scaling, which had traditionally provided intrinsic improved performance, now requires significant device engineering to overcome the "pitch hole" that degrades performance with scaling. This is forcing new material use and is one of the many things driving R&D costs up.

Another challenge is 3D packaging, where trends at the wafer level and package level are challenging reliability. On the one hand, ultralow-k porous films being used in wafer-level interconnects make it more difficult to maintain a rigid substrate; on the other hand, new lead-free solder bumping requirements are more rigid and less deformable than their predecessors. The upshot is that 3D packaging schemes must deal with internal stresses that can cause interconnect failures.

ASMC 2011
Day 1: Rain doesn’t damper the spirit
Day 2: Approaching device scaling, manufacturing challenges with partnerships
Day 3: EUV, image sensors, and a capital perspective

Picking up a theme from Norm Armour’s first-day keynote, Patton cited a number of successful collaborations that IBM has managed, in part because of a 4× increase in R&D costs over the last decade. Referring to technology development as an "ecosystem," he cited successes working with ASML, Toppan Photomasks, Zeiss, and Mentor Graphics on the critical source-mask optimization (SMO) technology that is allowing optical lithography to extend to 20nm-14nm, and with ATMI on high-dose implant strip.

Like Armour, Patton was optimistic about EUV litho technology, predicting it would come into early use at the 14nm node, and then more extensively at 11nm.

The panel discussion, ably moderated by veteran journalist Dave Lammers, featured four perspectives on how partnerships can be applied to chipmaking challenges.

Walid Ali, senior manager for R&D at the Abu Dhabi-based Advanced Technology Investment Company (ATIC), gave a global perspective on the human capital needed for development of new chipmaking centers, noting that there are some areas of concentrated activity but others (like Brazil) where there are many engineers but little silicon presence. Abu Dhabi is drawing on its large expat community, including many engineers from the Indian subcontinent, to fill out its expanding tech sector; he called out academic institutions and other educational efforts in their plan to help build the ranks of engineers. In response to a question from Lammers, Ali also hinted that the ATIC-funded fab in Abu Dhabi will be watching some disruptive technology introductions, but wouldn’t divulge details.

The panel’s academic representative, Mike Fancher of the New York State Center for Advanced Technology in Nanoelectronics, and associate professor of Nanoeconomics, at the SUNY College of Nanoscale Science and Engineering (CNSE), noted that the Albany-based effort has been working in that area in its 800,000-square-foot facility. He noted that some 12,000 jobs have been created or retained in the region by the program since 2001, with over 250 participating industry partners.

Another hub of industry-academic collaboration is CEA-Leti, the French research center, where over 4000 people work side-by-side, including ~1500 students, ~1600 researchers, and ~900 industry assignees. The presentation by equipment asset manager Olivier Demolliens made me want to visit, and not just because of the skiing opportunities in the Grenoble area — successful joint-development programs have included double-patterning work with Nikon, multibeam lithography development with Mapper, and an interesting effort in directed self-assembly with an unnamed partner.

Also on the panel was Ari Komeran, Intel industry development manager/director of Europe, the Middle East, and Africa. While Intel has something of a reputation for being self-reliant, it also has a tremendous number of partnerships and collaborations with universities, startups, and suppliers. He highlighted the Israeli model of providing government and academic support for startups as a good alternative to the venture capital model, providing good financial leverage.

An audience question touched on the problem of financing education. Fancher noted that students at the College of Nanoscale Science and Engineering are all on fellowships and get graduate student wages. Demolliens added that in France, students don’t have to pay, but that it’s challenging to attract them to tech careers. "We have to get people to dream," he said.

Next report will include a tour of the Luther Forest Technology Campus, where GlobalFoundries’ Fab 8 is located, and final ASMC 2011 wrap-up.

May 18, 2011 — Alchimer, nanometric film deposition provider for advanced 3D packaging applications, launched a new wet-deposition process, AquiVantage, that grows interconnect layers for interposer redistribution layers (RDLs) and significantly enhances via-last backside wafer interconnects. The process eliminates 2 costly photolithography steps.

Interposers incorporate a through-silicon vias (TSV) structure, as well as front-side redistribution circuitry (for attachment to the chip stack) and back-side redistribution and bumping (for attachment to the circuit board).

The AquiVantage process provides concurrent wet deposition of TSV and front-side isolation, barrier, and copper fill/RDL, while eliminating CMP and dry deposition steps. It also supports smaller vias with higher aspect ratios.

On the backside, the AquiVantage process allows selective maskless growth of the on-silicon isolation layer, completely eliminating an entire expose/develop/etch/clean lithography-process cycle.

AquiVantage uses the same cost-saving technology as Alchimer’s wet processes for TSVs.  It eliminates several process steps, including two costly photolithography steps, in producing high-quality films. By eliminating steps, 3D package interposer costs can be reduced 50%.

AquiVantage technology accommodates thicker wafers, eliminating the need for wafer carriers and allows for highly scalloped via structures and faster etching times.

Alchimer CEO Steve Lerner sees AquiVantage changing business models and fab methods of manufacturing enterprises all along the electronics value chain, including IDMs, OSATs, and foundries.

Alchimer develops and markets innovative chemical formulations, processes and IP for the deposition of nanometric films used in a variety of microelectronic and MEMS applications, including wafer-level interconnects and TSVs for 3D packaging. Visit www.alchimer.com.

by Debra Vogler, senior technical editor

May 18, 2011 – Raj Jammy, VP of materials and emerging technologies at SEMATECH, covered a broad swath of CMOS scaling drivers, system and device trends, and infrastructure requirements during session #3 at the ConFab (May 15-18 in Las Vegas). System-level trends, such as smart phones, mobile computing (e.g., iPads), and cloud computing are driving requirements for low- and ultralow-power logic with multi-core/multi-modules, dense 3D nonvolatile memory RAM for SSDs, and dense DRAMs. There is also a move to SoCs, along with high levels of functional integration and faster data transfer between modules and chips.

At the system level, the implications for devices include an even greater need for leakage reduction, and wide-band intra-chip and inter-chip interconnects. At the device level, architectural transitions to 3D FinFETs, III-V FETs, 3D flash memories, RRAM, STTRAM, SoCs, and 3D TSVs, and even photonic interconnects are being evaluated. Each of these alternatives poses specific challenges — but common to all are strong infrastructural needs to be successful. Among the transitions’ challenges will be new materials and/or using non-silicon materials, new models/test methods/designs, integration challenges, as well as processes, materials, tools, and packaging.

Jammy sees CMOS transitions unfolding between 2012 and 2017 (Figure 1) — starting with planar Si, SiGe (2010), moving to non-planar Si, SiGe in 2013, and on to III-V non-planar in 2016 and Vdd-0.3V III-V TFETs by 2019. Robust process technologies and tools such as selective ALD that are low damage will play a major role in making the transitions happen. Materials interactions and devising suitable test structures, methods and reliability will also be needed.

Click to Enlarge
Figure 1: Roadmap CMOS transitions, 2012-2017.

With respect to non-planar device scaling, the pros and cons among the key technologies (i.e., wafer, FinFETs, and nanowires) will have to be weighed. For example, the starting cost for bulk wafers are lower than for SOI wafers, but they require more process steps to produce isolated devices. And the use of FinFETs poses many possibilities: two or three gates, tall fins, a high-mobility channel, or a heterogeneous fin channel. Even nanowires have many pathways from which to choose: single wire, stacked wires, high-mobility channel, or a heterogeneous wire channel — with progressively more difficult integration going from one to the other (Figure 2).

Click to Enlarge
Figure 2: Non-planar device scaling: trade-offs are key.

 

 

At The ConFab 2011, Jammy spoke with senior technical editor Debra Vogler about TSVs, SoCs, SiPs, logic, and memory:

 

by John Behnke, VP of worldwide sales and marketing, Intermolecular Inc.

Click to EnlargeMay 17, 2011 – The first day of the SEMI/IEEE Advanced Semiconductor Manufacturing Conference (May 16-18) offered productive and informative sessions on keeping chipmaking profitable in coming generations. Even the weather was pro-business; drenching rainstorms ensured that no one was tempted to wander out into the beautiful Saratoga Springs, NY, countryside.

Keynote speaker Norm Armour, VP and GM of GlobalFoundries’ Fab 8 in New York State, was well-received as "the most popular person within 1000 miles" — not just because he’s one of the industry’s truly nice guys, but because so many conference attendees were eager for jobs or a part of Fab 8’s $7.2 billion purchasing budget. Armour noted that his first fab project in Austin had a budget of about $100 million, which I thought was interesting as that is what a single EUV tool will cost.

Those levels of expenditures for Fab 8, said Armour, explain why new collaboration models are needed to address broad challenges in areas like EUV, 3D packaging, automated process control, and R&D in general. Likewise, the development of 450mm wafers, which he predicted would be the state-of the art technology platform for chipmakers by 2017, with fabs running in the $10 billion range.

Armour indicated that Fab 8 expects to receive its first EUV litho tool in the second half of next year, and to begin using EUV at the 14nm node. Asked whether EUV would be ready, he replied, in essence, that the alternatives (double, triple or even quadruple patterning) are so unappealing that it must be ready.

ASMC 2011
Day 1: Rain doesn’t damper the spirit
Day 2: Approaching device scaling, manufacturing challenges with partnerships
Day 3: EUV, image sensors, and a capital perspective

Other noteworthy talks to open this year’s ASMC:

— Heiko Fröhlich of Infineon discussed a very impressive fully automated on-the-fly edge inspection initiative at a 200mm fab. By inspecting every wafer’s edge for cracks, residue, incomplete copper edge bead removal, and litho wafer-edge exclusion (WEE), the program has been able to identify 5-10 problem wafers each month. The use of analytics to assign a value to WEE was very innovative; the achievement is especially noteworthy because of the fab’s wide range of products, and the fact that it runs geometries from 250nm down to 90nm.

— David Stark, manufacturing capabilities project manager at the International Semiconductor Manufacturing Initiative (ISMI), spoke on equipment health monitoring. The concept is an evolution of data mining, creating a metric of the "health" of process tools, and even particular chambers. In trials with Lam etchers, the system has been able to predict chuck life to within ~100 hours. More broadly, Stark posited that it could be advantageous for a fab management system to route particular wafers to a healthier tool rather than the first-available, as is typically done now.

— A very good overview of through-silicon vias (TSVs) from Klaus Hummler of SEMATECH, whose 3D Interconnect Program (with a long list of blue-chip members) seems to really be stepping up to the task of developing some standardization in the still-fragmented TSV space. This is a perfect example of the type of collaboration that Armour was calling for in his keynote, and it’s good to see it being put into practice.

An added bonus to a very interesting and productive first day of the conference: the night before the hotel bar and grill stayed open late enough for us to catch the San Jose Sharks playoff hockey game. (Unfortunately, they lost!)

by James Montgomery, news editor

May 17, 2011 – Harvey Frye, vice-chairman of TEL America, summarized the new supplier landscape, showing the evolution of equipment stretching 50 years, with interdependent trends for both equipment developers and customers. Tools in the 1960s were mostly proprietary and manual with basic functionality; by the ’70s tools came in a wider variety, with some auto-handling and basic process controls. OEMs asserted dominance in the 1980s, emphasizing higher reliability and a unit process focus to a more global customer base. The 1990s saw "explosive tool diversification" with diverse materials, integrated processing and controls, and overall equipment effectiveness to improve efficiency. That diversity expanded to the "extreme" entering the 21st century as the industry crossed into the nano-process horizon and into diverse market applications, and began to explore and embrace consortia efforts to meet cost/complexity needs.

From a macro point of view, Frye categorized a list of decreasing trends (feature size, # of customers, device lifetimes, shorter time-to-ramp and time-to-market, and margin pressures) in contrast to those trends on the rise: device complexity, diversity of materials, IDMs/OEMs moving up the value chain, costs for leading-edge development and per-gate, and diversity of IC choices.

Since the ’80s and into today and the future, supplier collaboration has become increasingly complex — a denser mix of factory management & process control, process integration & unit process engineering, factory automation, contamination control, and product engineering. Chipmakers and tool suppliers concurrently have to navigate the integration of device designs and processes, production process, and chamber/platform designs.

For TEL, a collaborative approach means convergent business needs/strategies, with each partner contributing unique technology, know-how, and experience, Frye explained. He emphasized complete and constant communications of needs and expectations as the project evolves — and the need to develop a "trust relationship" within which ideas can be freely exchanged, to allow for a "one-team" environment.

There are three pathways within an equipment supplier’s universe, Frye showed: primary ownership, involvement/connection, and awareness/influence. Primary owners are deeply involved in future tool development (concept and alpha), through development of prototype pilot tools, beta qualification, and unit processes, and ramping with production tools, tool quality, productivity, and COO. Being involved means participation as a consortia partner, stepping back for a slightly broader view of functionality (DFM, materials, processes, tool linkage), integrating processes and process control modeling, and system extendibility. Above that level are those focused on end-market needs, IC design/simulations/modeling, test methodologies, time-to-market, and ultimately fanning out with copy-exact (or copy-close) practices. For "second-life" equipment there’s a strata too: primary owners focus on refurbishment and upgrades, those involved/connected look to optimize the supply chain, relocation/resale, and new processes, and those stepped back to an "influence" position emphasize new applications and third-party support options.

Many of these factors are logic-centric, Frye noted, from higher mask sets to stringent standards to test strategies, 3D packaging, and demanding customization.

The future landscape for suppliers will be very much a customer-process-centered world, Frye advised. That means adapting to a faster cadence for consumer markets, expanding synchronized complexity with partners through lifecycles, and measuring success by avoiding harm to customer objectives, all under an increasing influence of the logic sector. Some things will never change, though, he said — well-developed relationships are fundamental, and smart innovation "can always lead or save the day."

Meredith Courtemanche, digital media editor

May 16, 2011 — Today at The ConFab, John Chen (Nvidia), Jeong-ki Min (Samsung Electronics), and Abraham Yee (Nvidia) gathered foundry, OSAT, and chip maker leaders to discuss what happens beyond Moore’s Law. The following are key points from "Collaboration to Strengthen the IC Supply Chain."

John Waite, VP, packaging development and central engineering at GLOBALFOUNDRIES, presented "Supply Chain Reaction: A Collaborative Approach to Packaging Innovation." Since packaging costs are the dominant contributor to the value chain, designers need to select the right combination of silicon and packaging technologies to achieve performance and cost goals.

What enables success in the More Moore realm? Waite lists diverse options for wafer bumping (lead-free, copper pillar, lead and high-lead solders used in bond on pad, repassivation or redistribution [RDL] designs) and package form factor (QFP/QFN, BGA and flip chip, wafer-level chipscale packages [WLCSP]), as well as vertical options that take advantage of Z space (stacked chips, system in package [SiP]). These each have tradeoffs of cost, time, and density/performance, and customers must make packaging choices with these goals in mind.

Click to Enlarge
Packaging influences the front end. SOURCE: John Waite, GLOBALFOUNDRIES.

Packaging increasingly requires attention on the frontend because of the packaging demand on the wafer. The frontend, backend, and system suppliers must collaborate in chip development. Early engagement, EDA tool flow optimization, turnkey wafer-to-package assembly, and other risk reduction strategies take a design from R&D into high-volume manufacturing.

Nick Yu, VP of technology development, Qualcomm, brought a fabless perspective to the session. In "3D Through Si Stacking Technology — a Qualcomm Perspective," Yu reminds us that 3D packaging creates thin, small, exciting products with long battery life. All 3D packages create better form factors on the board, increased performance for the device, and higher modularity in the design. The options to create a 3D package, however, as Waite also noted, are myriad: wire bonded chip stacks, flipped stacked chips, bumped/bonded chip stacks, through silicon vias (TSV) implemented as interposers, via first, or mid-process. Yu assesses these 3D technologies on the commercialization roadmap. Leading-edge technologies, like wide I/O memory on logic, are moving from lab to fab for the best of all worlds.

Click to Enlarge
Supply chain needs a 3D ecosystem, as 3D is disruptive to how we do things today. SOURCE: Nick Yu, Qualcomm.

While integrated fabless companies are ramping up leading-edge 3D IC designs, the lack of standards is holding back the 3D ecosystem. Traditional business models also don’t support the boundary-breaking 3D design and process steps. Yu supports integration via standards bodies and research consortia to bring design and manufacturing standards to the 3D arena. Consider Yu’s questions: Who owns the die? Who holds the inventory? How are pass-through costs funded? Who owns the integration process? Who owns the yield? Is the additional risk of TSV worth the benefits over wire-bonded stacks? Is a fabless design company or an IDM the way to go? The key question here is who acts as the "3D aggregator"? Foundry, memory company, OEM, fabless, OSAT?

Raj Pendse, VP of product and technology marketing at STATS ChipPAC and Robert Darveaux, CTO of Amkor, covered this supply chain integration from the dedicated packaging house perspective. Pendse presented "3D Packaging Evolution from an OSAT Perspective." Darveaux spoke on "Supply Chain Challenges for 3D Integration of Memory and Logic Devices using TSVs."

Click to Enlarge
Material flow and infrastructure evolution. SOURCE: Dr. Raj Pendse, STATSChipPAC Inc.

Pendse sees synergies and intersections among parallel developments in the three areas of packaging technology (i.e. traditional die and package stacking on substrates, fan-in and fan-out wafer level packaging and 3D Si integration). With these new process technologies, the OSAT industry’s role is transformed. Pendse channels wafer bumping, thinning, and other tasks into an in-between space for the Si foundry and OSAT to determine logical hand off points. Many of these processes can be done in both — the question to ask is who can do it better in each scenario? Is TSV fabrication best handled in the fab, with the OSAT taking over via fill and silicon interconnect? Pendse also spoke on "bridge" technologies — interposers, super-thin package-on-package, TSV hybridized with fan-out wafer-level packages (FOWLP) — that play an interim role in the commercialization of 3D. Pendse shared a typical OSAT TSV roadmap through 2013 with the attendees.

Darveaux compared the relative ease of sourcing, assembly, and test of package-on-package (POP) with the challenges of TSV: difficult to test high-density area array contact pads or bumps; bare or partially assembled memory and logic die that are difficult to burn in adequately; a newer joining technology not widely available to OEMs and contract assemblers; a poorly characterized joining process yield; and, due to the immaturity of the test, burn-in, and assembly; unclear ownership of defect liability. This applies to the "2.5D" interposer strategy as well as pure 3D TSV stacks. Interconnect processes are too new and done in too small sample sizes to lead to industry agreement on the right method: die-to-die first or die-to-laminate first? Interposer in singulated format or wafer format?

Click to Enlarge Click to Enlarge
Consortium collaboration model. Supply chain collaboration model. SOURCE: Robert Darveaux, Amkor Technology.

These problems can not be resolved by technologies or business models alone. TSV processes can be standardized and characterized, with the resource-sharing model of consortia or the faster but potentially messy supply chain collaboration on specific projects. Both offer pros and cons, and fit different needs of the industry.

More from The ConFab:

May 13, 2011 — The ConFab gathers semiconductor industry leaders to discuss the biggest trends in the chip manufacturing sector. One of these major trends is 3D packaging. In Session 2 on Monday (May 16), John Waite (GLOBALFOUNDRIES), Raj Pendse (STATS ChipPAC), Robert Darveaux (Amkor), and Nick Yu (Qualcomm) will combine fabless, foundry, and packaging house perspectives on the disruptive design and process changes that 3D creates for the semiconductor and packaging industries.

John Chen (Nvidia), Jeong-ki Min (Samsung Electronics), and Abraham Yee (Nvidia) will lead "Collaboration to Strengthen the IC Supply Chain."

Smaller dimensions and higher complexity chips are driving "More Moore," while "More than Moore" is pushing vertical integration, such as 3D TSV. Both require changes to the traditional frontend and backend of semiconductor manufacturing.

3D packaging, whether bonded wafers with through silicon vias (TSV) or wire bonded chip stacks, push packaging processes into the fab, and make wafer-level processes the outsourced semiconductor assembly and test (OSAT) provider’s responsibility. In this new supply chain, many questions are raised about ownership and responsibility in the implementation of a new chip design. Since our IC industry has long been divided into EDA or fab tool supplier, fabless, foundry and assembly/test companies, getting everyone to work together and make profits for each party can be extremely challenging. This session is intended to explore various options.

Session 2, "Collaboration to Strengthen the IC Supply Chain" presentations:

John Waite, VP, packaging development & central engineering, GLOBALFOUNDRIES: Waite will present "Supply Chain Reaction: A Collaborative Approach to Packaging Innovation." As the industry moves aggressively to more advanced technology nodes, the once "bland" interconnect, assembly and packaging processes can now improve performance and power efficiency as well as reduce costs for chip designers. Chip-package interaction (CPI) is significantly more complex today, requiring coordination between design and manufacturing. It is increasingly difficult for foundries and OSATs to be able to deliver end-to-end solutions that meet the requirements of leading-edge designs. A new approach is needed — one that leverages the success of a "shared investment, shared return" model.

Raj Pendse, VP product & technology marketing, STATS ChipPAC: Pendse will present "3D Packaging Evolution from an OSAT Perspective," illustrating the synergies and intersections among packaging technologies (i.e. traditional die and package stacking on substrates, fan-in and fan-out wafer level packaging and 3D Si integration) and the resulting future path for packaging technology. Pendse will discuss the transformed role of the OSAT industry in supporting this evolution. Latest developments in wafer thinning, micro bumping, micro bonding and logical hand off points among Si and package foundries will be presented, and Pendse will look at "bridge" technologies — interposers, TSV substrates — that play an interim role in the commercialization of 3D.

Robert Darveaux, CTO, Amkor: Darveaux will present "Supply Chain Challenges for 3D Integration of Memory and Logic Devices using TSVs." While package-on-package (POP) technology allows ease of test, flexible sourcing, and mature interconnect technology, TSV technology suffers from difficult-to-test high-density area array contact pads or bumps; bare or partially assembled memory and logic die that are difficult to burn in adequately; a newer joining technology not widely available to OEMs and contract assemblers; a poorly characterized joining process yield; and ultimately unclear ownership of defect liability. These problems can not be resolved by technologies or business models alone.

Nick Yu, VP of technology development, Qualcomm: Yu is presenting "3D Through Si Stacking Technology – a Qualcomm Perspective." Qualcomm, as an integrated fabless company, has several primary motivations for following 3D TSV-based stacking technologies. Yu will propose a roadmap for the evolution of the 3D technology, and detail the integration challenges for an integrated fabless manufacturer using a distributed supply chain. Yu shares Qualcomm’s implementation strategy, and points to some of the gaps in the business model associated with 3D products.

See The ConFab’s conference program here.

Bios:

Session Leaders:
John Chen, Ph.D., VP of technology and foundry operations, Nvidia: Dr. Chen has 30 years of experience in IC industry ranging from IDM to Foundry to Fabless companies. Dr. Chen was a Howard Hughes Doctor Fellow and received a Ph.D. in EE and an Executive Management degree, both from UCLA. He also holds a M.S. from University of Maine and a B.S. from National Taiwan University, both in E.E. He started his career as a researcher in Hughes Research Laboratories, subsequently at Xerox Palo Alto Research Center (PARC). Most of his work involves CMOS devices and process technologies. Later, he has had various technical and managerial positions in technology development and IC manufacturing. He has held positions at Cypress Semiconductor, TSMC, WaferTech (a JV then led by TSMC), and Nvidia. Dr. Chen has published 100 papers, mostly by IEEE and a book, "CMOS Devices and Technology for VLSI." Accolades and industry service include IEEE Fellow, Technical Advisory Committee for ITRI, Taiwan, and committee member of SIA and GSA.

Jeong-ki Min, VP of foundry marketing, Samsung Electronics Co., Ltd. LSI Division: Jeong-ki Min joined Samsung in 1984 and has served in marketing, technology planning, and capital investment to M&A and other strategic alliances. He also worked for Samsung’s US operations (San Jose, CA), as a planning officer. Min leads foundry and ASIC marketing teams and his current responsibility at System LSI Division includes business development and market research and customer engineering supports.

Abraham Yee, director of advanced technology & package development, Nvidia Corporation: Yee is responsible for readying next generation technologies for production, benchmarking technologies, investigating new technologies and setting NVIDIA’s process roadmap. Prior to NVIDIA, he has worked with SUN Microsystems, Equator Technologies, and LSI Logic Corp. Dr. Yee received his BA in Mathematics and Physics and his PhD in Physics from UC Berkeley.

Speakers:
Waite is responsible for global packaging development and collaborative R&D activities, as well as central engineering. Waite joined GLOBALFOUNDRIES in 2009 after a 25-year career in technical and management positions at AMD and IBM.

Pendse completed his BS in Materials Science from IIT Bombay with Top in Class honors and his Doctorate in Materials Science from UC Berkeley. Prior to joining STATS ChipPAC, Raj held various positions in package engineering and R&D at National Semiconductor Corp and Hewlett-Packard Labs. His work has spanned the gamut from packaging of high-end microprocessors, ASIC and graphics products to low-cost packaging solutions for logic and analog devices used in mobile phones and consumer products. His most recent focus has been on flip chip and 3D wafer level packaging.

Darveaux has 24 years experience in the IC packaging field at the Microelectronics Center of North Carolina, Motorola, and Amkor. Robert has a B.S. in Nuclear Engineering from Iowa State University and a Ph.D. in Materials Science and Engineering from North Carolina State University. His expertise covers thermal and mechanical simulation, materials characterization, failure analysis, and fatigue life prediction for solder joints. Robert has published over 75 technical papers and has 22 patents.

Yu is a Vice President of Engineering at Qualcomm’s CDMA Technologies Division. He sets Qualcomm’s semiconductor technology roadmaps including wafer fab process node, backend interconnect and packaging technologies. Yu has 18 years of experience with Qualcomm on low power wireless chipset and SoC development. He is one of the architects of, and has participated in the definition and development of, many Qualcomm chipset products. Nick has an MSEE degree from Georgia Institute of Technology.