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When you’re designing a geometrically complex structure like a high-k metal gate, FinFET, or vertical DRAM, you will probably use SEM/TEM cross-sectional imaging to work out the bugs. Maybe even a touch of AFM. However, in production, optical scatterometry-based technology is used, chosen for its speed, non-destructive nature and ability to monitor the 3D shape of a feature. This group of metrology techniques is commonly called OCD (Optical Critical Dimension) or SCD (Scatterometry Critical Dimension).

SCD tools commonly employ either reflectometry, ellipsometry, or a combination of the two methods.  In both approaches, the tool focuses a beam of light onto the structure and collects the light that bounces back. By varying the wavelength, a spectrum is constructed that can be sensitive to the shape of the structure, to the optical properties of the materials that comprise the structure, and to previous-layer features buried within materials transparent at the measurement wavelength.

For a given structure and SCD measurement setup, a set of modeled spectra are generated (either on the fly, or offline and stored as a library of curves) that characterize how the spectrum would change if a parameter of interest were varied—for example, the depth of a trench in a vertical DRAM. The measured spectrum is then compared to the modeled spectra to determine which of the models fits best. The result should correspond to a precise, repeatable value for the parameter of interest.

Of course, seldom is anything that simple in real life. Sometimes more than one parametric change (e.g. trench depth and top CD) results in about the same change in the spectrum. The SCD community calls this phenomenon “parametric correlation.”

Let’s say SCD is being used to monitor the shape of a high-k metal gate structure in production

(Figure 1). Suppose the metal undercut, metal and silicon layer bottom CDs and the silicon sidewall angle are the parameters of interest; various failure analysis techniques have shown that small variations in these parameters can correspond to significant degradation in device performance or yield. Let’s also say that small variations in the undercut length are evident in the SCD spectrum—but in a way that’s indistinguishable from what happens when the metal bottom CD changes. A similar issue was reported by GLOBALFOUNDRIES and IBM, in a paper published in a recent SPIE Proceedings on Advanced Lithography.1 

 

How can you unravel which structural or material variation is causing the change in the spectrum in the presence of parametric correlation? It’s easy if you are certain that one of the two correlated parameters is well controlled—and therefore you can assume that the other parameter is changing. Unfortunately, this is not always the case.

A related way to reduce the variables in the problem is by carrying data forward from previous layers.  If the results for a given layer on a given wafer have already been determined, that information can be used to “fix” the values of some parameters in new layers.  This capability is available today if the wafer has been consistently measured on the same SCD tool. In the future it will be possible to extend this capability to wafers measured on different SCD tools within a fab—as long as those tools are well matched.

When it’s not possible to remove variables by fixing their values, parametric correlation can often be broken by changing the type of SCD measurement: using a different wavelength range; sending the light in at a different azimuth or altitude angle; changing the polarization; or using ellipsometry instead of reflectometry or vice versa. If you have enough different technologies to throw at the problem, you may find one setup that allows the SCD tool to respond sensitively to one of the correlated parameters and not the other.  Sometimes it’s necessary to combine spectra from multiple technologies (angles, polarizations, etc.) or from measuring multiple structures (vertical and horizontal lines, or isolated and dense lines) to come up with a unique solution.

In the example cited earlier, GLOBALFOUNDRIES and IBM found that the use of multiple azimuth angles (parallel and perpendicular to the direction of the dominant lines and spaces) allowed SCD to monitor variations in the metal undercut with high precision and repeatability—and low parametric correlation.

Rebecca Howland, Ph.D., is a senior director in the corporate group and Lanny Mihardja is a product marketing manager in the Films and Scattering Technology (FaST) Division at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

References

1.       Matthew Sendelbach, Alok Vaid, Pedro Herrera, Ted Dziura, Michelle Zhang and Arun Srivatsa, “Use of multiple azimuthal angles to enable advanced scatterometry applications,“ Metrology, Inspection, and Process Control for Microlithography XXIV, ed. Christopher J. Raymond, Proc. of SPIE Vol. 7638, 76381G, 2010.

by Paula Doe, SEMI Emerging Markets

Materials experts from across the supply chain who gathered at the Strategic Materials Conference 2012 in San Jose in October discussed key materials needs for micromanufacturing outside the CMOS mainstream, as OLEDs and GaN-on-silicon power semiconductors come to market, and alternatives like graphene, CNTs, and self-assembling polymers get closer to commercial application.

Large OLED displays are coming, and counting on materials breakthroughs

OLED adoption in larger displays is surely coming, driven by business necessity, argued James Dietz of Plextronics. Most of the major display makers are seeing operating losses from their LCD business, and OLEDs look like the best option for higher-value, differentiated products to improve margins. The OLED displays look significantly better, and they may potentially open new markets for lighter or flexible or more rugged displays, or for dual-view products. OLEDs’ ultra-fast switching speeds could allow different viewers with different glasses to watch different programs at the same time on the same screen. Moreover, though OLEDs are more expensive now, the variable costs for a 55-in. OLED TV made on an 8G line will be quite comparable to those for a similar LCD. And the OLED costs have far more potential to come down further, by developments like simplifying the layer stack and introducing wet processes that use lower cost equipment with higher utilization of the expensive materials.

But the nature of the market also means new challenges for suppliers. Anxious to avoid another experience like the commoditization of the LCD sector, display makers intend to keep their processes and complex OLEDs materials stacks to themselves this time, which makes process integration of different materials and equipment difficult. The device makers are investing in developing their own materials, making exclusive contracts with equipment and materials suppliers, and doing their own process integration. Integration is also being driven by some materials suppliers like DuPont Displays. But the familiar semiconductor model of the material and tool supplier working together to deliver a process to the customer is not the rule. "We see a gradual transition from all vapor to more solution layers," says Dietz. "OLEDs will enter the TV market in the next three years, and will have solution process steps by 2015."

The 55-in. OLED TVs announced for 2012 now look more likely to come out in only very small volume — a few thousand units in 2012 — and initial prices of ~$9000 will limit sales. But OLED TVs will start to see real growth by 2014-2015, helping to push OLED displays to a $25 billion market by 2017, reports Jennifer Colegrove, VP of emerging display technology at NPD DisplaySearch. She says ten new AMOLED fabs are planned to be built or updated in the next three years. OLED materials, now about a ~$350 million market (include the OLED organic materials but not substrates), should grow at close to the same 40% CAGR of the overall market, to reach $1-2 billion in 2014. But breakthroughs are still needed in oxide and amorphous silicon backplanes, color patterning technology, lifetime of blue materials, encapsulation materials, reduction of materials usage, and of course integration, uniformity and yields of all these things.

OLED display revenues will grow to about $35B in 2019, up from $4B in 2011, with CAGR ~40%. (Source: NPD DisplaySearch, Q3’12 Quarterly OLED Shipment and Forecast Report)

Solution processing is critically important to bringing down the cost of large screen OLEDs, argued John Richard, president, DuPont Displays, as the current production methods which rely on thermal evaporation with fine metal masks are proving costly to scale to 8G substrates. "We developed an alternative process using soluable materials to bring down cost," he notes. Wet processes reduce capital needs and cut material waste to reduce costs significantly, but still need ever better lifetimes and efficiencies of the OLED materials, particularly for blue. A major Asian display maker has licensed the DuPont technology, and plans to scale it up to 8G. The process uses largely pre-existing tools to slot coat the hole injection and transport layers, and pattern the surface with wetting and non-wetting lanes, before nozzle printing stripes of red, green and blue emitters using custom tool developed with Dai Nippon Screen.

The rest of the stack — the electron transfer layer, the electron injection layer, and the metal cathode — is then deposited by thermal evaporation. Richard says coating and printing processes can use significantly less material than vapor deposition, as it avoids losses in the chamber, on the mask, and during alignment and idling. DuPont reports printed blue emitter lifetime is up to 30,000 hours — or 8 hours a day of video for 15 years — before degrading to half brightness. Next issues include optimizing the cost of synthesis and starting materials, and reducing operating voltage for better device efficiency.

Graphene and carbon nanotubes get closer to commercial applications

Next-generation energy storage presents materials opportunities as well. One key enabler for improving both supercapacitors and batteries could be graphene, especially with better sources for consistent quality material at reasonable cost. Bor Jang, CEO of Angstron Materials, reported that his company has engaged a contract manufacturer in Asia to start volume production of as much as 30 tons of graphene next year, using Angstron’s technology that claims good control of structure and properties. "That will bring down costs by an order of magnitude," says Jang. First application will likely be performance enhancers for lithium-ion battery electrode materials, and then for improved electrodes for supercapacitors. Angstron has announced demonstration of a graphene-based supercapacitor with energy density comparable to a nickel hydride battery.

"We think supercapacitors is a market to invest in," said Chris Erickson, general partner at Pangaea Ventures, a somewhat unusual venture fund that invests particularly in materials and green technologies. "We think it will reach $1 billion in the near future." Erickson is also enthusiastic about the potential for dynamic window glazing using vapor-deposited coatings and ITO to adjust to control the shading on windows, for dramatic energy savings of up to 30% in energy consumption in a building, according to NREL — and buildings reportedly use 49% of total energy in the US.

Nantero reported major progress from its long effort in controlled processing and performance for its carbon nanotube thin film, targeting low-cost, low-power non-volatile memory. CTO and co-founder Thomas Reuckes said the company is now lithographically patterning films of its spin-coated aqueous solution of carbon nanotubes, as roughness, adhesion and defectivity are now suitable for semiconductor processing. Metal impurities are down to <1ppb in liquid form, wafer-level trace metals to <1E11 atoms/cm2 . Reuckes reported production of working and yielding 4Mbit CNT memory arrays, and showed results of reliability data. The company just announced a joint development program with imec to manufacture, test, and characterize the CNT memory arrays in imec’s facilities for applications in next generation <20nm memories.

GaN for power semiconductors needs higher purities than LED market

Power semiconductors made on GaN on silicon are being released to the market now, and, given time, could potentially address some 90% of the what IMS Research projects will be a $25 billion (silicon-based) power semiconductor market for MOSFET and IBGTs by 2016, suggested Tim McDonald, VP for emerging technologies at International Rectifier Corp. GaN theoretically offers much better specific on-resistance to breakdown voltage tradeoff than Si or SiC. The key to wide adoption is for GaN on Si based solutions to achieve 2-4× performance/cost compared to silicon.

To achieve the necessary low costs, IR uses compositionally graded layers of AlyGaxN grown on the silicon to ease the thermal and lattice mismatch of the GaN film to the silicon wafer. IR claims 80% yields, with warp and bow controlled enough to run on a standard 150mm CMOS line. GaN on silicon is moving more quickly to market for power semiconductors than for LEDs, as it brings better performance, not just potentially lower prices. It also helps that threading defects do not have the same impact on performance–plus IR has been developing the technology for six or seven years already.

The power market needs higher purity materials and cleaner tools for better yields on its larger die, compared to the LED market. It also prefers larger diameter wafers for lower costs. Demand for gas sources and MOCVD tools should scale with volume, and the tools need to be optimized for larger wafers and become more automated, with perhaps some 2,000-3,000 tools needed for the whole market over the next two decades. Packaging may move from wire bonding to soldered or sintered contacts, and will adopt other means of reducing stray packaging-related inductance and resistance.

The LED market will see only a few more years of significant growth, argued Jamie Fox, lighting and LEDs manager for IMS Research-IHS. Revenues from displays including TVs are leveling off from their fast ramp, as the markets mature, and as LEDs get both brighter and cheaper, driving down both units needed and cost per unit. The LED lighting market will continue its fast climb to near ~$6 billion over the next several years, but then as more lamp sockets are replaced by the longer lasting LEDs (and CFLs), there will be less need for replacements, and the market will slow. Slower adoption near term, however, would mean less saturation later.

Cree’s Mike Watson, senior director of marketing and product applications, countered by pointing out the potential for innovation that solid state technology brings to lighting, noting how digital technology has transformed markets like telephones and cameras into new industries for digital communications and digital imaging. "Semiconductor technology keeps changing industries by innovation," he noted. "Why do we keep thinking of it as just replacement?

Directed self-assembly for higher resolution lines and holes

Another of the more innovative materials alternatives on the CMOS side is directed self-assembly for next-generation patterning, which seems to be making rapid progress. AZ Electronic Materials CTO Ralph Dammel reported that block copolymers, with similar molecules together in blocks instead of randomly dispersed, tended to arrange themselves with the similar chain sections together, conveniently lining up into cylinders that look similar to lithographic contact holes, or into lines similar to lithographic lines and spaces. Wafer surface patterning with topography or chemicals can control the placement of these self-assembled patterns, on top of standard 193nm immersion lithography. Work with IBM Almaden suggests the process can provide better CD uniformity for quadruple patterning at lower cost than the spacer pitch division process. Other work shrinks contact holes, while improving the CD variation compared to the resist prepatterns. The company is now providing large-scale samples for in-fab process learning, with implementation perhaps as early as 2014, though design for self-assembly needs further development work.

When something happens to a reticle, the consequences can be dire. Contamination in the wrong place on a reticle can result in a defect in every die of every wafer. Fabs have to keep their reticles clean.

On the other hand, if the reticle is cleaned too many times, the pattern can start to erode. Reticle pattern degradation eventually causes critical dimension uniformity (CDU) changes on the wafer, which can translate into issues of device performance or yield. Plus, while the reticle is going through the cleaning process, it’s not available to do its work in the scanner.  Unless reticle cleaning is carefully planned, production of that particular product may screech to a halt. Fabs need to check their reticles for contamination and pattern degradation—at a frequency that balances the cost of taking the reticle offline to inspect it and the cost of the inspection itself against the risk of printing reticle defects or CDU errors on the wafer.

Some fabs have moved their reticle cleaning facilities on site, greatly accelerating the turnaround time to get the reticle cleaned, re-inspected, and back online. New cleaning technologies have also come into favor, including wet processes like UV-ozonated water with hydrogen peroxide, and dry processes including plasma and laser shot cleaning. In general the new processes have resulted in reduced overall defectivity post-clean; however, the problem of pattern erosion remains, and the remaining defects can be more difficult to detect.

Recent studies1 have shown that contamination is more likely to occur at the edges of mask pattern features than in open areas between features. That’s bad news for the wafers, because a variation on the edge of the mask pattern will immediately affect the carefully engineered wavefronts of the light that transfers the mask pattern to the photoresist on the wafer. It’s also bad news for the reticle defect inspectors, because it’s much more difficult to detect a defect in an area of dense pattern than a defect the same size, sitting in the middle of an unused space. Also, the mask error enhancement factor (MEEF) of a defect within dense pattern is higher than that of a defect in open space—which means that the defect within the pattern is more likely to print on the wafer and more likely to affect die yield. It may be difficult to find defects on the edge of pattern, but these defects have the potential to be the most damaging. They must be found.

In the mask shop, reticle inspection is accomplished by comparing the pattern on the mask to the design information—a “die-to-database” inspection. In the IC fab, the mask database is often not available. For that reason, KLA-Tencor invented a database-free method for detecting contamination on a mask, a method called STARlightTM, named for its use of Simultaneous Transmitted And Reflected light. First introduced in 1995, the STARlight methodology2 compares the transmitted-light and reflected-light images of a reticle to determine whether or not a defect is present. Since then, STARlight has undergone many improvements, and today’s fifth-generation STARlight is optimized for detecting defects on edges of pattern features.

1. STARlight operated on the simultaneous transmitted (left) and reflected (middle) image to identify the defect (right).

STARlight addresses the issue of finding localized contaminants, even on pattern edges. It works for single-die, multi-die or shuttle masks (multi-die masks comprised of different die), inspecting any kind of random or repeating pattern—including the scribe line. Once these defects are found, the reticle can be cleaned and re-used.  But what happens when the cleaning process is modifying or removing pattern—material that’s supposed to be there—instead of contaminants?  Or what if the problem is not localized contamination, but a contaminating film that affects the reticle’s transmissivity? These issues may not create defects on the wafer, but they may affect the wafer’s CDU.

Some inspection systems now offer a mode that maps the reflectivity or transmissivity across the entire reticle. In some cases, these data are collected simultaneously with localized defect data. The reticle maps can then be processed and calibrated against a reference to extract CDU information.

2. Examples of intensity-based CDU maps from the reticle inspection system.

3. Degradation of a sub-resolution assist feature (SRAF), imaged by the reticle inspection system.

With the introduction of new cleaning processes and smaller pattern features, reticle management in the IC fab has extended beyond detection of localized defects to include detection of contaminating films and CDU changes. With thoughtful sampling strategies, regularly inspected reticles can live long, productive lives.

Rebecca Howland, Ph.D., is a senior director in the corporate group and Mark Wylie is a product marketing manager in the Reticle Products Division at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

References

1. E. Foca, A. Tchikoulaeva, B. Sass, C. West, P. Nesladek, R. Horn, “New type of haze formation on masks fabricated with Mo-Si blanks,” Photomask Japan 2010.

2. F. Kalk, D. Mentzer, A. Vacca, “Photomask production integration of KLA STARlight 300 system,” Proc. SPIE 2621, 15th Annual BACUS Symposium on Photomask Technology and Management 112 (1995).

 

 

 

 

by Tom Morrow, executive vice president, Emerging Markets Group, SEMI

European government representatives, consortia and suppliers discussed programs to support and participate in the anticipated conversion of leading-edge wafer manufacturing to 450mm wafers at SEMICON Europa in Dresden. Possibly signaling a major change in the 450mm planning framework, representatives from G450C, imec, Fraunhofer IISB, and others discussed mechanisms for greater European participation, and emerging research initiatives, related to 450mm development. In addition, in probably the first major public discussion of the 450mm lithography system schedules following investments from TCMC, Intel and Samsung last summer, ASML provided a comprehensive presentation on their roadmap for 450mm EUV platforms.

Michael Liehr, newly promoted to executive Vice President of Innovation and Technology at the College of Nanoscale Science and Engineering (former IBM veteran, Paul Ferrar has been appointed General Manager, Vice President and coordinator of G450C project), provided an update on the consortium’s pilot fab, tool roadmap, wafer development, and wafer availability plans. Newly announced at Europa was G450C’s welcome of global collaboration efforts with regional consortia and government agencies. As a new consortium on the crowded stage of collaborative research development, G450C’s working relationship with other consortia in the industry has been an ongoing question for manufacturers, suppliers, and key stakeholders. G450C’s role in prequalifying tools for 450 wafer manufacturing places them in a powerful, central role in the future of the industry. With the industry consolidating and global R&D dollars needing increasing focus and efficiency, the roles, core competencies, and optimal distribution of research initiatives across the world is undergoing significant transformation.

"We’re looking forward to working with any regional organizations including wafer pool and adjunct tool demos," said Liehr during the session. While G450C priority remains on the specific program deliverables, Liehr spoke to the need to recognize and value the contributions of other players in global industry. He said that G450C selection, validation, evaluation of projects would proceed with criteria emphasizing technical and commercial transition value and that "G450C understands that public funding must be applied within the taxpayer region."

Liehr’s comments were welcome news to European consortia with a high stake in the semiconductor industry. The Fraunhofer-Gesellschaft network in Germany, for example, has 60 institutes, more than 1800 employees and an annual research volume of 1.65 billion euros (2010), of which 1.4 billion euros is generated through contract research. Lothan Pfitzner, head of department at Fraunhofer IISB provided an overview of his organization’s existing and planned activities in 450mm manufacturing process development. Pfitzner said Fraunhofer Group will support 450mm R&D&I activities based upon their strong expertise and experience in equipment assessment, manufacturing science (e. g. process control, automation, wafer handling, etc.), flying wafer concepts, green aspects, modeling and testing.

For reasons of cost optimization, Fraunhofer is also willing to reclaim 450mm wafers. In addition, Fraunhofer hopes to contribute in the area BEOL and of TSV in optimization of processes as well as in the area of metrology and defect detection and characterization. Part of these activities will take place at the Fraunhofer IISB Erlangen facilities.

Fraunhofer plays a key role in many current and planned public-funded research efforts related to 450mm manufacturing. The ENIAC EEMI450 is currently developing and evaluating wafer material, metrology tools, process equipment, and handling systems. The CATRENE NGC450 program is providing analysis and optimization of cluster platform performance. Planned programs under Framework 7 include SEA450 involving equipment assessment of cleaning and hot processing equipment and corresponding metrology tools. Another planned program is ENIAC 450EDL project involving virtual metrology and predictive maintenance models for 450mm metrology tools.

Imec, headquartered in Leuven, Belgium, has nearly 2000 researchers including more than 600 industry residents and guests, is also planning a 450mm pilot line to begin construction in 2013 and scheduled for completion in 2015. Phase one of the program is anticipating funding from the Flemish government, EU ENIAC FP7, and industry sources. Imec expects to play a key role in the acceleration of 450mm equipment development through installation of alpha and beta tools for early learning in an "industry-relevant technology flow." The organization’s track record of support for advanced process and lithography development is expected to be a key factor in securing a strong role in 450mm manufacturing programs.

Other European initiatives include those by Israeli "Metro450" Consortium comprised of five key companies: AMIL (metrology division of Applied Materials), Nova, Jordan Valley, Nanomotion, and Intel. University support comes from four institutions and public funding comes from the Israeli Chief Scientist budget. The regional interest in 450mm manufacturing stems from Israel’s strong success in wafer fab metrology, now accounting for over 30% of world’s share and approximately $1.3 billion in sales. Menachim Shoval, Metro450 Board Chair, said the transition of current 300 mm metrology solutions to 450mm manufacturing is not trivial and threatens their current world position.

Other regional interests expressed during the forum include those from the state of Saxony in Germany. Silicon Saxony, the organization representing the interests of the substantial semiconductor cluster, has a vision that by 2018 it "will be seen as a trendsetter for innovative semiconductor manufacturing technologies for 450mm and may plan to install its 1st 450mm manufacturing site in the Dresden region."

The scale and diversity of interests in 450mm is impressive, but a realistic forecast for European pilot lines and public funding is hard to gauge. Currently G450C plans to qualify "one or two…maybe three" tools per process, limiting broad supplier participation in future 450mm manufacturing. European efforts to supplement the G450C qualifying process may help open the participation opportunities for other companies in 450mm manufacturing, especially for European companies hoping to benefit from public funding. But significant EU and country funding of 450mm R&D is not yet assured. With the current European debt crisis and emphasis on austerity, significant funding for semiconductor R&D may be limited. Furthermore, there remains significant debate over research priorities with many in the European semiconductor community, including leading European device makers, favoring R&D emphasis on "More than Moore" programs.

Opening up the qualifying process for 450mm high volume production tools to European consortia would seem to benefit 450mm device makers, tool makers and the overall industry move towards 450mm wafers. In addition to expanding the number of qualifying tools and public R&D funding sources, European consortia can be expected to link important process development efforts in 3D transistors, 3DIC, and other areas with 450mm production requirements. Many of the current EEMI450 programs also feature unique approaches to metrology and material handling, adding an important "innovation" element to 450mm development efforts. At this stage of the 450mm transition, however, it is uncertain how likely G450C will move to open up their primary tool qualification role to organizations they may perceive as competitors. According to Liehr, "The same consolidation forces affecting device makers and suppliers are affecting R&D facilities. Specialization will need to be furthered so there is minimal overlap."

ASML begins 450mm development

Another noteworthy discussion in the European 450mm session was ASML’s plans for large wafer lithography systems to support high volume 450mm production. ASML successfully negotiated billions of dollars in capital investment by Intel, TSMC and Samsung this summer to support accelerated development of extreme ultraviolet (EUV) systems for 450mm manufacturing. Until a 450mm EUV lithography system is developed, 450mm pilot line development will utilize nano imprint technology, a significant R&D limitation according to many observers.

In perhaps the first public discussion of the company’s 450mm plans, ASML’s Frank Bornebroek discussed the product strategy and technology challenges for 450mm EUV systems. He described how ASML will now simultaneously develop four tools on two platforms to accommodate 450mm production. He said the initial versions will provide 30 wafers per hour in 2016-2017, extended to 60 WPH for EUV in 2018-2019. For immersion systems, ASML is targeting 50 WPH in 2016 and high volume systems in 2018.

While the company is committed to the G450C schedule for high volume production, significant technical barriers will need to be overcome. "It’s not just a scale up, but significant overlay improvements will be required…overlay drives patterning" said Bornebroek. "The larger the wafer, the more difficult it will be to improve productivity. We will need to accelerate 3-times more mass at 2-times more accuracy."

ASML is in process of hiring an additional 200 employees to meet the aggressive delivery goals. 450mm systems will require a "full base frame redesign" with major changes to chucks, mirror blocks, stages, tables and handlers, with adaptations to sensor and metrology systems. Bornebroek indicated that "450mm wafers will provide limited cost benefit for scanning systems."

by Dan Tracy, senior director, SEMI Industry Research and Statistics

October 3, 2012 – Semiconductor manufacturers in Japan are either consolidating or closing fabs, and, in several cases, transitioning to a "fab-lite" strategy, all in a restructuring effort to meet the market challenges ahead. While device manufacturers are consolidating manufacturing operations and plan to outsource more wafer fabrication and package assembly to foundries and packaging subcontractors, a large installed fab capacity remains in Japan. Recent data for the year shows overall wafer area shipments into Japan’s fabs being the same as shipments into Taiwan.

By 2014, the total installed fab capacity Japan should increase slightly from about 4.5 million to 4.6 million 200mm equivalent wafers per month. Installed 300mm fab capacity is expected to increase from about 760,000 to 840,000 300mm wafers per month — representing, by region, the third largest 300mm fab manufacturing capacity base globally. Over the next several years, fab spending in the Japan market will be directed towards the production of NAND flash memory, power semiconductors, high-brightness LEDs, and CMOS image sensors.


Regional share forecasted for 2013 fab materials market. Total market size: $25.7 billion.

Overall equipment spending in Japan will likely range on the order of $4 billion per year. Expected NAND flash investments in 2013 could approach up to $2.5 billion. LED fab equipment spending is estimated to be $340 million next year. Finally, Sony is expected to invest about US$ 1 billion or more in its CMOS image sensor production.

Japanese equipment and material suppliers are leading players on the global semiconductor industry stage. It is estimated that Japan-headquartered equipment companies collectively capture about 35% share of the global semiconductor industry spending per annum. Like their North American and European counterparts, customers in the rest of the Asia Pacific region are the largest base for new equipment sales.

Chemical and other material suppliers in Japan are market leaders in the manufacturing of silicon wafers, III-V wafers, advanced chemicals, packaging resins, and packaging substrates. It is estimated that the Japanese material suppliers sales represent about 70% of the global semiconductor materials market, both fab and packaging.

Japanese suppliers showcase the latest products at SEMICON Japan 2012

Leading Japanese equipment and materials suppliers will exhibit at SEMICON Japan 2012 on December 5- 7, along with global key players, at the Makuhari Messe, Japan. Find the latest products and innovations this companies offer to customers globally that enable key technologies for the future including 450mm, EUV, TSV, power devices, and HB-LEDs to name a few. Also, the show will co-locate with a major photovoltaic show, PVJapan 2012 so you can connect to two major microelectronics industries in a single visit.

For more information, including registration and exhibition, visit www.semiconjapan.org/en.

by Karen Lo, director, SEMI Taiwan

September 26, 2012 – At the SEMICON Taiwan 2012 450mm Supply Chain Forum on September 7, leading foundries and equipment manufacturers such as TSMC, TEL, Lam Research, Applied Materials, and KLA-Tencor convened to discuss the latest trends in 450nm technology as well as the opportunities and challenges involved. The experts at the forum agreed that many technical obstacles remain on the path to achieve mass production for 450mm wafers by 2018. The industry supply chain must collaborate on innovation to make this vision a reality.

In a presentation entitled "450mm challenges and opportunities," Dr. C.S. Yoo, senior director of the 450mm program at TSMC, said that increasing node complexity means diminishing returns from process miniaturization. For this reason, the industry began studying 450mm wafers with the goal of improving production efficiency, accelerating technology ramp-up, and shortening production cycles. Yoo stated that these advantages, together with higher land and personnel utilization rates, hopefully will offer the semiconductor industry more opportunities for long-term development.

Dr. C.S. Yoo, sr. director of 450mm program, TSMC

According to Yoo, the biggest question in the bid to realize mass production by 2018 is whether the industry can successfully develop the lithography required for 10nm node processes by 2015. At the same time, the industry must solve problems such as rationalizing equipment costs to make return on investments predictable, realizing significant improvements in productivity, and development of automated unmanned foundry operations, smart equipment, and green foundries.

The industry made many technological breakthroughs during the conversion over to 300mm wafers — and Yoo expects that the transition to 450 will produce even more innovative technologies in the future. TSMC will leverage its partnership with the Global 450 Consortium (G450C) as well as work with IC and equipment manufacturers to support the successful transition of the industry to 450mm.

Dr. John Lin, general manager of G450C, introduced the latest developments at G450C, noting that significant advances in 450mm technology have occurred in the past year and industry interest is continuing to build. He stated that the goal of G450C is to begin demonstrating 14nm technology this year and put 10nm into pilot production between 2015 and 2016. Major improvements in the quality of supply for 450mm wafers have been made, and most of the production machinery should complete the prototype phase by 2014. As for lithography — the most crucial part of the project — the preliminary prototype will probably be completed in 2016 and be ready for mass production by 2018.

The CNSE cleanroom is expected to be ready by December 2012; it will be the first 450mm foundry in the world. Lin said that G450C will continue to collaborate with suppliers and SEMI to promote the standardization of 450mm hardware infrastructure components as well as back-end processing and packaging and testing operations. By sharing in the costs of development, the industry will enjoy the benefits offered by 450mm.

Among equipment manufacturers, Dr. Akihisa Sekiguchi (VP and GM of corporate marketing, TEL), Mark Fissel (VP of 450mm program, Lam Research), Kirk Hasserjian (corporate VP of silicon systems group, Applied Materials) and Hubert Altendorfer (senior director of 450mm program, KLA-Tencor) all talked about the challenges involved with developing 450mm equipment.

Seikiguchi believes that 450mm will revolutionize the semiconductor industry and that only companies with strong financial fundamentals will survive due to the high cost of investment. With several years to go until the target of achieving mass production by 2018, Seikiguchi believes that the risks and uncertainty during this period makes proper communication and collaboration between customers, equipment suppliers, foundries and industry associations all the more important. The semiconductor industry should learn from past experience with 300mm transition to avoid making the same mistakes.

Mark Fissel of Lam Research also invoked the transition to 300mm as an example. The first prototype was completed in 1995 but the "dot-com" bubble and other economic factors slowed progress, so it took nine years for 300mm wafer shipments to finally exceed 200mm wafers in 2004. The development of 450mm equipment must also contend with design issues and challenges in terms of technology, capacity, cost and size. Fissel believed that the industry must balance the risk for 450mm development with its long-term ROI.

Kirk Hasserjian of Applied Materials proposed six important factors for a smooth transition to 450mm: Synchronization of the industry’s transition timetable, maturity of lithography, cost sharing, collaboration, innovation, and supply chain readiness.

The eventual wafer size transition will have widespread implications, both for those who make the transition as well as for those that wait. Much of the semiconductor ecosystem is now paying attention to — and planning for — the transition. SEMI is facilitating the development of industry standards and the flow of information throughout the supply chain. SEMI recently launched 450 Central, a web-based information service to help the industry efficiently transition to 450mm-ready solutions and keep the industry informed of important news and perspectives on 450mm wafer processing.

The most knowledgeable and authoritative voices in the industry discuss these tough issues at SEMI events around the world. Our objective is advance the dialog — to convey useful information to our attendees — and to serve as a platform for productive collaboration on these and other industry issues. The upcoming SEMICON Europa (October 9-11) features a 1.5 day session on "Progress in 450mm." For more information on SEMI, visit www.semi.org.

Overlay error is the offset in alignment between pattern at one step of a semiconductor process and pattern at the next step. Traditionally overlay error has referred to successive device layers, but in the case of double-patterning lithography, overlay error may stem from interwoven patterns at the same layer. Regardless, controlling overlay error is one of the most difficult issues that lithography engineers face in this era of shrinking design rules and complex, advanced lithography techniques. Because overlay error can affect yield, device performance and reliability, it must be measured precisely, and all sources of systematic overlay error must be discovered and addressed. These may include mask pattern placement error, deviations from wafer planarity, scanner nonlinearities and process variation.

In most cases, overlay error is measured optically by capturing an image of a specially designed alignment mark called an overlay target. Half of the overlay target is printed during the first process step, and the other half of it is printed during the second process step.

 

A standard overlay target is printed in two steps,  indicated in red and blue, and structured to measure the errors in x and y.

An overlay metrology tool captures the image and quantifies the alignment between the first and second parts of the target. The result is reported as a vector quantity, having a magnitude and direction corresponding to the x and y offsets. The procedure is repeated for each of the overlay targets on the wafer. Overlay error maps are comprised of a circular field of tiny vectors, representing the overlay error across the wafer. These maps are used to adjust the scanner or to uncover issues with the mask pattern, the wafer shape or the process. Overlay error maps are also used to disposition wafers.

Flexible, robust multi-layer target allows simultaneous measurement of overlay error within the same layer and between layers.

A recent development in the area of overlay measurement is extension of measurement capability to new layers and new materials (see above). When overlay error between layers is measured, the optical properties of the top layer are critical to the quality of the data. The metrology tool needs to be able to send photons through the top layer to detect the pattern underneath, and the quality of the image of the buried pattern is critical to the quality of the overall measurement. Because semiconductor processes use a variety of materials, and the optical absorption of a given material generally varies with wavelength, the well-equipped metrology system can select from a variety of wavelengths to achieve sufficient image quality for the buried pattern to enable an accurate, repeatable measurement. The alternative—introducing an extra process step to etch a “window” in the top layer before patterning it—adds significant cycle time and may degrade the underlying pattern. Cycle time pressures are ever-present and well known. Furthermore, when the entire overlay error budget is limited to a small number of nanometers, lithographers cannot afford to allot a large portion of the budget to uncertainty in the output of the overlay metrology tool.

Examples of particularly challenging classes of materials are those used to build 3D transistors, and hard mask materials used during litho-etch-litho-etch lithography. Hard mask materials are opaque to visible light, and their optical properties may fluctuate with composition and even with annealing temperature.  The latest overlay metrology systems can provide an appropriate wavelength that penetrates the top layer, making overlay metrology feasible without additional process steps.

Another new development in the field of overlay metrology is the use of multi-layer overlay targets. New target designs now allow a lithography engineer to measure within-layer overlay and between-layer overlay using one target. These innovative targets are small enough to be inserted into the die without consuming an unfeasible amount of valuable real estate. Their designs are flexible and robust, allowing adjustments for specific process and layer requirements. They are compatible with various pitch-splitting and double-patterning schemes. Most importantly, the new multi-layer targets allow lithographers to measure within- and between-layer overlay error with one image and, at the same time, reduce systematic errors that could degrade the measurement if separate targets had been used.

Overlay metrology remains one of the most challenging issues that lithographers currently face. Innovations in overlay metrology tool and target design must continue, to enable our industry to make smaller, faster, lower power, more affordable chips.

Rebecca Howland, Ph.D., is a senior director in the corporate group and Amir Widmann is a senior director in the Optical Metrology division at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

2012 stall could pave the way for a record-breaking 2013

by Christian Gregor Dieseldorff, SEMI Industry Research & Statistics

September 7, 2012 — Consumer and business sentiment has become more important than ever before in the semiconductor industry. As we near the end of the third quarter in 2012, pessimism about the economy prevails given the challenging financial situation in the US, a slowing Chinese economy, and the on-going European debt crisis.

At the beginning of 2012, the outlook for semiconductor revenue was more optimistic, with predicted average growth of about 4 to 6 percent. The macroeconomic situation inspired caution and semiconductor revenue outlook changed to an outlook of flat to 2 percent for this year, with various key companies announcing changes in their revenue outlook. For example, in July, Intel cut its 2012 sales growth target to US$ 55.6-58.7 billion, up 3 to 5 percent from 2011, though Intel expects a stronger second half of 2012. TSMC cut its revenue growth rate by about 1 to 2 percent, expecting a slowdown in 4Q12 and into 1Q13. In July, STMicroelectronics announced it will cut capex for 2012 by 25 percent because of a lower outlook.

Meanwhile, struggling Japanese MCU and Analog/Power-maker Renesas considers options to stay in business, such as consolidating business units or pursuing a fab-lite strategy. Fujitsu announced it will pursue a fab-lite strategy, and recently announced the closure of one assembly and test facility and the transfer of ownership of two other facilities to J-Devices Corp. Also since mid-2012, a number of companies have announced more layoffs — including Siltronic AG, Nokia, Cisco, ON Semi, Google’s Motorola Mobility and Rambus.

2013: Another golden year?

While various industry segments appear to be tapping the brakes, others are revving their engines, hoping for an improved 2013. Increased demand for mobile devices, such as new smartphones, ultraportable PCs, and tablets may push semiconductor revenue higher by 10 percent, making 2013 another golden year.

Semiconductor revenue and capex rise and fall together, such that fab equipment spending generally trends along a similar path.

Frontend fab equipment spending, by product types.
(Source: SEMI World Fab Forecast Reports, August 2012)

In terms of fab equipment spending, 2007 and 2011 were golden years. Although spending in 2012 will decline, it may still turn out to be the third largest spending year on record for overall fab equipment spending.

SEMI’s fab database shows about 200 facilities equipping (including Discrete and LED fabs), suggesting that 2013 has the potential to be another golden year — perhaps an all-time record — with 17 percent growth, almost $43 billion.

Frontend fab equipment spending. (Source: SEMI World Fab Forecast Reports, August 2012)

Key drivers for fab equipment spending in 2012 are the foundries, led by TSMC, Globalfoundries, and UMC with over $10 billion combined spending. Their dominance continues in 2013 with about another $10 billion in spending.

Frontend fab equipment spending by product types, showing largest spending types.
(Source: SEMI World Fab Forecast Reports, August 2012)

Examining fab equipment spending by product type, the DRAM sector is still struggling with declining average selling prices. The industry lost German maker Qimonda in 2009, Powerchip exited DRAM in 2011, and ProMOS is struggling. In order to avoid further ASP declines, DRAM makers ceased investments in new capacity and those who could afford it focused investment in new technologies and upgrading existing fabs. After the bankruptcy of Elpida, at the beginning of 2012, global capital expenditure for DRAM declined to very low levels. This is not expected to change in 2013.

Flash investments also slowed in 2012. For example, at the beginning of 2012, Sandisk announced a pause in Fab 5 capacity expansion. At the end of July, Toshiba announced it will cut its NAND production by 30 percent. However, SEMI data indicates that Flash investments will pick up again in 2013, with big spenders Samsung (mainly Line 16), SK Hynix, Flash Alliance, and Micron.

Samsung turns attention towards System LSI by converting existing Memory fabs into System LSI and building new ones. Spending on a grand scale, Samsung is predicted to pour over $5 billion in 2012 and over $6 billion in 2013, all into this product type.

Although more fab projects have begun than estimated last year, the overall number of fab construction projects has declined year-over-year. Looking at how this affects investments, in 2012 investments for construction projects are expected to decline by 4.4 percent (from about $6.4 billion to $6.1 billion). In 2013, another 10 percent drop will bring fab construction spending to about $5.5 billion.

Foundries perform much better than other industry segments in terms of installed capacity growth. Foundries are even more necessary given industry consolidation and as more IDMs change to a fab-lite or fabless business model. Examining installed capacity by product type, Flash will overtake DRAM in 2012.

Cutbacks in Flash production in 2012 have improved average selling prices so companies will likely increase Flash capacity in 2013 to meet anticipated demand growth. DRAM capacity investments are at "maintenance level," so no increase of installed capacity is expected in 2013. Samsung’s heavy investments in System LSI will singlehandedly grow SLSI capacity (its $4 billion conversion of Austin, TX fab from Flash to 28nm SoC logic devices).

Promising future

While 2012 may not bring positive growth, it may still end up reigning among the top performing years. As the industry continues to consolidate, with more companies moving towards a fab-lite or fab-less model, traditional foundries continue to expand and some big IDMs ramp their foundry services. Investment "engines" may be idling in the near-term, and those investments could gear up for a smooth acceleration into 2013, driven by high demand for mobile devices.

SEMI Industry Research and Statistics Group: A worldwide dedicated team

Since the last fab database publication at the end of May 2012 SEMI’s worldwide dedicated analysis team has made 296 updates to more than 230 facilities (including 52 Opto/LED fabs) in the database. The August edition of the World Fab Forecast, lists over 1,150 facilities (including 300 Opto/LED facilities), with 76 facilities starting production this year and in the near future.

The SEMI World Fab Forecast uses a bottom-up approach methodology, providing high-level summaries and graphs; and in-depth analyses of capital expenditures, capacities, technology and products by fab. Additionally, the database provides forecasts for the next 18 months by quarter. These tools are invaluable for understanding how the semiconductor manufacturing will look in 2012 and 2013, and learning more about capex for construction projects, fab equipping, technology levels, and products.

SEMI’s Worldwide Semiconductor Equipment Market Subscription (WWSEMS) data tracks only new equipment for fabs and test and assembly and packaging houses. The SEMI World Fab Forecast and its related Fab Database reports track any equipment needed to ramp fabs, upgrade technology nodes, and expand or change wafer size, including new equipment, used equipment, or in-house equipment.

Also check out the Opto/LED Fab Forecast.

Learn more about the SEMI fab databases at: www.semi.org/MarketInfo/FabDatabase and
www.youtube.com/user/SEMImktstats

SEMI
www.semi.org
San Jose, California
September 4, 2012

Technologies, Business Models, Applications and Materials Management Strategies in Transition — SEMI reports.

August 22, 2012 — The $100B+ electronics materials industry is undergoing rapid metamorphosis as technologies, markets, business models, and materials management practices are all being restructured to meet the needs of a profit-hungry, environmentally-conscious and innovation-dependent world. The $50 billion semiconductor materials industry alone, for example, needs investment in new lithography resists, novel device architectures, and advanced interconnect and packaging while trying to maintain margins in a consolidating industry where manufacturers know how to leverage buying power. At the same time, advanced electronics materials markets in displays, LED, PV and power semiconductors — collectively larger than traditional semiconductors — are providing new, potentially higher-profit opportunities for suppliers. Both manufacturers and suppliers are responding to these dynamics through joint development agreements and other collaboration models, increasingly important resource recovery strategies, and capitalizing on the synergies between advanced materials requirements among different industries.

These and other issues will be the focus of 2012 Strategic Materials Conference (SMC) to be held on October 23-24 at SEMI headquarters in San Jose, CA. For more information on the conference, visit www.semi.org/en/node/41386. SMC is the only conference dedicated to exploring the synergies, trends and business opportunities in advanced electronic materials. Many of the developments, trends and collaboration in one industry are applicable to other industries, creating potential valuable synergies across the materials spectrum. With presentations by leading market analysts, academic researchers, industry consortiums, leading manufacturers, and top suppliers, SMC will serve as a valuable forecasting tool and accelerator for advanced materials usage in the electronics industry.

To provide a broad reach, the 2-day SMC will feature four 2-hour tracks in semiconductors, carbon-based materials for energy storage and ICs, LED/Power devices, and OLED/printed electronics. Each of these areas are characterized by significant opportunities and challenges. In LEDs and power semiconductors, for example, dramatic increases in solid state lighting and emerging markets for electric vehicles, Smart Grid, solar inverters and other areas have a driven a race in Si, GaN on Si, GaN on GaN, SiC, and sapphire-based technologies. In organic and printed electronics, OLED displays are quickly emerging as a replacement for LCDs even in large format displays, potentially creating opportunities for leveraged technologies in OLED lighting, thin film batteries, printed logic and memory.

Other portions of the conference will be devoted to critical trends and issues in materials usage and materials development, including rare earth supply dynamics, materials recovery, collaboration models and joint development strategies, investment opportunities, and more. Leading industry analysts will also provide market forecast and insights into application trends. Significant networking opportunities including a dinner reception will be included in the conference.

Figure source: SEMI Materials Market Data Subscription May 2012

One of the collaboration strategies explored in the conference will discuss how equipment OEMs, materials suppliers and major manufacturers can work more effectively together. Today, frequent R&D efforts can be distributed at research consortia, manufacturer process development labs, and at materials suppliers, each in conjunction with key equipment suppliers who have their own development programs. Speakers from Intel, Micron, Air Liquid and Applied Materials will discuss common development strategies and ways they can be improved.

Materials refining, recycling and recovery is also becoming a critical issue for many industries due to regulatory compliance and as a cost reduction imperative, with implications for fab design, intellectual property protection, onsite materials infrastructure and other areas. Experts from Envirodigm, Sachem, Intel and Air Products and Chemicals will discuss this “paradigm shift” in manufacturing and how it provides both opportunities and challenges.

SMC has provided valuable information and networking opportunities to materials and electronics industry professionals since 1995. SMC 2012 builds on that legacy, expanding the reach and focus of the conference to examine advanced electronics materials for the semiconductor and adjacent industries. SMC is organized by the Chemical and Gas Manufacturers Group (CGMG) is a SEMI Special Interest Group comprised of leading manufacturers, producers, packagers and distributors of chemicals and gases used in the microelectronics industry. For more information on the conference, visit www.semi.org/en/node/41386.

Karen Savala, president, SEMI Americas

August 10, 2012 — This year at the SEMICON West press conference, I presented on “Supply Chain Readiness in an Era of Accelerated Change” and I’d like to summarize that presentation for you.  The talk centered on the increasing capital and technology requirements of advanced semiconductor production and the pressures this creates on the supply chain. The structure of the industry is rapidly changing — and how it will respond to the simultaneous challenges of Moore’s Law scaling, 450mm wafer production, 3D-ICs, and industry consolidation is very much unknown.   Much of this uncertainty is reflected in what we call “supply chain readiness.”

Never before has the industry faced greater economic and technological uncertainty. The industry is consolidating, with fewer leading edge chip makers and fewer leading edge suppliers.  The technical challenges are increasing as geometric scaling and Moore’s Law now must be accomplished with rising process engineering complexity — particularly in the areas of EUV lithography, 3D-IC chip packages and 450mm wafers.

The economic and technical challenges of today’s environment will have an impact on supply chain readiness.  In the past, the size and scope of the industry supported a vibrant supply chain of start-ups, innovators at the leading edge, brilliant fast-followers, and a variety of technology and process specialists. 

Today, the supply chain is dominated by several large OEM companies who rely upon a global ecosystem of technology subsystem and component firms.  As process engineering becomes more complex at leading-edge nodes, the readiness of the supply chain to deliver advanced, integrated solutions becomes less certain.

 

EUV Lithography

Photolithography systems are among the most complex and expensive machines on the planet.  They are also the most important tool to maintain the pace of Moore’s Law.  From advanced light sources from Cymer to highly engineered optics and lenses from Carl Zeiss, approximately 90% of an ASML lithography system comes from external suppliers. EUV systems are currently shipping, but as you know, they do not meet the required wafers-per-hour throughout for high-volume production.  Consequently, EUV is being deployed in conjunction with immersion lithography, directed assembly and other options. The node at which EUV fully enters mass production is still uncertain — certainly below 20nm, perhaps at the 16 nm node, possibly at 8nm.

To alleviate some of this uncertainty, both Intel and TSMC have made significant investments in ASML to support EUV development and help accelerate the introduction of 450mm systems.  While this massive infusion of cash will assure a common mission between these key industry players, how it will impact next generation mask infrastructure has yet to be seen.

In mask readiness, EUV mask blanks are an order of magnitude more complex than today’s conventional mask blanks.  Spectacular work has been accomplished to improve yield and reduce defects on these new systems.

Today, according to SEMATECH, mask performance is sufficient to meet the needs of memory, but still short on meeting the requirements for logic.  More importantly, as this chart shows, you’ll see that a significant gap between EUV mask blank demand and supply capacity currently exists.  Uncertain EUV insertion will make investment difficult for suppliers to address this capacity shortfall before full production is assured.  This uncertainty may also threaten production volume availability for EUV resists.

 

 

3D-IC

3D-IC is another area of dramatic and uncertain change lies in the area of 3D-IC stacked chips.  Given their potential for smaller form factors, increased performance, and reduced cost and power consumption, 3D-IC technologies are now enabling the next generation of advanced semiconductor packaging.  Already, 2.5D approaches using silicon interposers to provide wide IO bandwidth and denser packaging have been introduced, but many manufacturing and collaboration barriers remain before widespread commercialization. 

3D integration using through-silicon vias promise a fundamental shift for current multi-chip integration and packaging approaches.  But cost-effective, high-volume manufacturing will be difficult to achieve without standardized equipment, mat䁥rials, and processes.

With many advanced packaging processes taking place on the semiconductor wafer, the traditional supply chain of “front-end fab at the foundry” and “back-end fab at the packaging and test house” is at risk of falling apart. TSMC has been clear about their vision. They want an   expanded role in the industry to implement — not just wafer foundry services — but 3D integration as well, including thinning, bumping and assembly.

While the business models sort themselves out, there remain technology challenges and process flow uncertainty.  Chips-on-substrate, chips-on-wafer and chip-on-chip all remain viable options. 

Currently, there are no collaboration models to solve this foundry-OSAT-IDM and fabless chip matrix for complex, multi-chip packages.  SEMI standards are addressing many supply chain, equipment and materials issues. However, market demand and business models must continue to sort themselves out before 3D chip stacking can widely penetrate the industry.

 

450mm Wafer Transition

The most expensive semiconductor industry technology transition in history will occur with the transition to 450mm wafers.  R&D costs alone are estimated to rise between $8 and $40 billion, depending on the efficiency with which the transition is coordinated.  The high end of this estimate represents a level of investment that is equivalent to what the entire industry spent on advanced process development over the past five years.  These costs will be incurred concurrently with other major technical challenges in the industry, including the move to 3D transistor structures, and EUV and 3D stacked chips already mentioned. The recent investments in ASML by Intel and TSMC reflect just how much the industry will be changed by 450mm development requirements. 

Currently, the Global 450 Consortium, or G450C, with members from Intel, IBM, Global Foundries, TSMC, and Samsung, is in the process of constructing and equipping a 450 pilot line in New York.  G450C has said that it expects the line to complete by mid- 2013 to early 2014. The business model to equip this pilot line is unlike anything we’ve seen before — in this industry or elsewhere!  The pilot line will feature approximately 50 tool types, most if not all, from no more than two vendors.  Performance data from this pilot line will be used to qualify equipment purchases for high-volume production equipment.  To many, it is clear that to participate in future 450mm production, equipment suppliers must participate in the pilot line.

However, not all vendors are being asked to participate, and for those that do, the terms for participation in the pilot line are daunting.  How the industry will pay for and recover the massive R&D cost has not been resolved.  Suppliers must weigh a decision to participate in pilot line development in conjunction with the possibility of not being qualified for production equipment orders from the world’s top chip manufacturers.  The timing and quantity of these of these potential future orders are also not known. 

These are difficult and complicated negotiations and decisions for the industry’s leading OEMs.  They are even more complicated and difficult for the remainder of the supply chain. 

While our leading equipment suppliers must sell products and services to chip manufacturers, many of the component and subsystem suppliers do not; they often serve multiple industries. 

As the current collaboration model unfolds for 450mm development, its impact on a variety of technology suppliers — many of them exhibitors at SEMICON West — is uncertain. Approximately 90% of ASML’s components and subsystems are provided by outside suppliers.  Another example, Applied Materials is dependent on 800 suppliers worldwide, with 75 prime strategic suppliers representing 80 percent of their annual procurement allocation. 

On the transition of the industry to 450mm wafers — it is certain that the impact on the supply chain will be disruptive and significant. While it appears that G450C may be the primary path of coordination for the scale-up of wafer process tools, it is the OEMs that will be coordinating a complex multi-layered supply chain of component and sub-assembly providers.  At SEMICON West for the first time, the major process tool makers communicated requirements and expectations to the larger group of supply chain participants that may not have direct access to the consortia pilot line.

 

SEMICON West 2012

At SEMICON West, the most knowledgeable and authoritative voices in the industry discussed these tough issues.  Our objective is advance the dialog — to convey useful information to our attendees — and to serve as a platform for productive collaboration on these and other industry issues.  All of the events at SEMICON West (keynotes, partner events, TechXPOTs, and technical presentations) allow key industry stakeholders to discuss where it makes sense to collaborate — and where it’s best to compete.

 

Please let me know if you have comments or questions at [email protected].

 

Karen Savala

SEMI

www.semi.org