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In the third installment in a series called Process Watch, the authors discuss some of the challenges of 450mm wafers. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.

August 2, 2012 — Chip manufacturers need wafers that are both bigger and better: bigger to help achieve cost targets through gains in manufacturing efficiency, and better to help reach device performance targets through the time-honored path of the pattern shrink. Our industry leaders have announced plans for pilot lines producing devices with sub-20nm linewidths on 450mm wafers, beginning in 2014 or 2015.

In the meantime, wafer manufacturers need to figure out how to make these giant wafers. The increased time required to grow the huge silicon ingot and then to cool it down under conditions optimized for crystal quality raises the risk of defects in the silicon crystal significantly.1 Polishing the surface uniformly and without microscratches requires new equipment and consumables. New cleaning equipment and processes must be developed. Also, 450mm wafers are proportionally thinner than 300mm wafers — which means they are more likely to deform during processing or handling. Such deformation can induce slip lines — crystal lattice defects similar to geological slip lines after an earthquake — around the edge of the large wafer. Crystal-originated pits (COPs), particles, slip lines, microscratches and cleaning residues all can interfere with one or more of the tightly-controlled processes that comprise the early steps of building a semiconductor device.

Printing smaller patterns necessitates tighter specs on many aspects of the wafer — regardless of wafer size. Because 450mm wafers will be used for sub-20nm lithography, their flatness and surface roughness must be very well controlled. Gradual changes in the shape of the wafer surface can be corrected by the scanner during patterning, but the wafer must be reasonably planar across the reticle field. More abrupt changes in the shape of the wafer surface may not be correctable; this is termed higher-order shape. Uncorrectable higher-order shape can displace the pattern, resulting in misalignment (overlay error) between layers — or it can cause defocus errors that affect the critical dimension (CD) of the printed structures. Higher-order shape can also interfere with film uniformity during chemical-mechanical polish (CMP) processes. Any of these errors can result in electrical problems affecting the device’s reliability, performance or yield.

450mm wafers have a higher number of edge die — notoriously the lowest yielding die on the wafer. The shape of the edge (“Edge Roll-Off” or ERO) can affect CD during patterning of edge die. Defectivity at and near the edge of 450mm wafers is typically higher, and will need to be very carefully monitored.

In essence, substrate manufacturers need to make much larger wafers with surfaces even more perfect than they are now: truly bigger and better wafers.  The impact of the surface quality, defectivity, flatness and ERO of 450mm wafers is considerable: With more than twice the number of die as a 300mm wafer, every 450mm wafer is extremely valuable. And just to add an extra challenge, some industry pioneers have announced that they will manufacture devices on 450mm epi wafers — adding the complexity of an epitaxial silicon layer, with its slightly increased surface roughness, stress-induced warp and unique epi defects. There is also interest in validation of 450mm silicon-on-insulator (SOI) technology.

Bare-wafer metrology and defect inspection play key and early parts in enabling wafer, equipment and chip manufacturers to develop and control their sub-20nm processes on 450mm wafers. These tools need the sensitivity to meet sub-20nm node requirements, and the ability to handle 450mm wafers with reliability and speed. Sub-20nm inspection sensitivity is enabled by deep-ultraviolet (DUV) technology and high-resolution haze mapping, technology that was pioneered recently on 300mm wafers by the latest-generation surface inspection systems. The images below show examples of surface defects, polishing marks and cleaning residues revealed on 450mm wafers by the latest inspection technology. These images are visually interesting, but indicative of the early stages of the manufacturing process; images of wafers meeting chip manufacturing specs would look nearly uniform. High resolution surfaces images such as these are a quick and intuitive tool for identifying the source of the defect, so that the issue can be remedied immediately, before additional time and materials are consumed.

 

Rebecca Howland, Ph.D., is a senior director in the corporate group and Amir Azordegan, Ph.D., is a senior director in the Surfscan/ADE division at KLA-Tencor.

1. See for example, “Technical challenges in the development of next generation wafers.”.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions for chip manufacturing at the leading edge.

If you want to quickly find and fix the source of a process excursion, you have to be able to capture the right defects, and review and classify them efficiently. Electron-beam review is always the rate-limiting step in this process; thus it’s worth investing effort in improving the odds of identifying defects that are going to lead to discovery of the source of the excursion. Even at the blinding speed of up to12,000 defects per hour (the state of the art for an e-beam review tool), most fabs can’t justify the time to review every defect on every wafer. How do you make sure you’re reviewing the yield killing defects and not wasting time reviewing nuisance events?

On critical layers, optical wafer inspection has to be run very “hot,” that is, with very high sensitivity settings, in order to capture the smallest, lowest-contrast defects that may affect yield. The problem is that hot inspections frequently capture not only defects of interest (DOI), but also nuisance events, such as line-edge roughness or defects on dummy pattern.  Unfortunately, nuisance events tend to strongly dominate the defect count in a hot inspection. When it comes time to review the defects to determine their source, choosing a random, unbiased sample may lead to reviewing a very small number of DOI—perhaps too small to represent the DOI population accurately.  You might not even be lucky enough to sample all DOI defect types, if nuisance defects represent a large fraction of the defects captured. The result is a misleading defect pareto—which can result in a delay in getting a new process to yield, or even a delay in getting a new chip to market.

There are two main approaches to skew the defect pareto away from nuisance events and toward DOI: (1) reduce the percent nuisance capture on the inspection system and (2) identify nuisance events after inspection and remove them from the review sample. A third approach would be to identify nuisance defects during e-beam review, but that strategy would be the least efficient. Nuisance capture on the inspection system can be reduced by selecting an appropriate combination of inspection wavelengths, apertures and polarizations that preferentially captures DOI over nuisance. Having an inspection system that offers the flexibility to manipulate defect type capture can be very effective at reducing nuisance capture during inspection. This sort of approach has been used for many device generations and over many generations of inspection systems for nuisance reduction.

What’s new is the ability to use design information to either skip “nuisance areas” of the die during inspection—or, after inspection, to remove defects residing in nuisance areas from the review sample. The former strategy is called micro-care area inspection; the latter is called design-aware nuisance filtering.

One of our technology-leading customers recently used micro-care area inspection to focus a high sensitivity inspection on patterns comprised of dense, thin lines. An automatic “care area” generator was used to search through the design file of the die, to draw hundreds of thousands of small care areas wherever dense, thin lines occurred (Figure 1). Only these care areas would be inspected. Together the care areas represented less than 5% of the die area normally inspected—but defects occurring in these areas had a high probability of being yield killers. Severely restricting the inspected areas dramatically increased capture of the yield-killing bridge defects and reduced the nuisance defect population to nominal levels.

 

Design-aware nuisance filtering was used to help two prominent foundries reduce nuisance defects on a silicon-germanium (SiGe) layer. SiGe is used in some high K metal gate processes to improve device performance. The problematic nuisance defect on the SiGe layer represented a small change in shape to the edge of the polygon—a variation that had no apparent effect on the device. After the defect team optimized the wavelength/aperture/polarization combination for best capture of DOI, traditional nuisance filtering, based on the attributes of the defect signal during inspection, was able to reduce the nuisance defect count by an order of magnitude. However, nuisance events still dominated the captured defect population, at a rate of 90%. At this point, design-aware nuisance filtering was used to associate the locations of the nuisance defects to a small number of pattern types. When all inspection events associated with these pattern types were eliminated, the DOI contribution to the defect pareto advanced from 10% to 85%.  Two SiGe nuisance areas are indicated in Figure 2 with solid yellow lines.

 

Strategically manipulating the defect sample reviewed by the e-beam review system so that it contains a high percentage of DOI has become necessary to creating a defect pareto that quickly and clearly directs defect engineers to the source of the excursion. Techniques like micro-care area inspection and design-aware nuisance filtering can be valuable tools for skewing the defect pareto toward yield-killing defects. For further information about creating an actionable defect pareto, please see last month’s Process Watch article, “The Dangerous Disappearing Defect.”

Rebecca Howland, Ph.D., is a senior director in the corporate group and Ellis Chang, Ph.D., is Nuisance Czar in the wafer inspection division at KLA-Tencor.

Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions for chip manufacturing at the leading edge.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

 

“The Dangerous Disappearing Defect” is the first article in a new series called Process Watch. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions for chip manufacturing at the leading edge.

Finding and classifying defects on a wafer is a statistics game. The defect pareto—the bar graph showing the number of defects by type caught by the defect inspector and identified by the e-beam review system—drives the actions of the defect engineers in the fab. However, it’s not necessarily the tallest bar in the graph that tells the experienced defect engineer how to fix a defect problem. Far too often, the tallest bar is the insidious “SNV”—SEM Non-Visual. Some fabs bluntly label this category “Not Found.”

It might be more accurate to call the category “Not Found Again.” The defect inspection system did indeed find these defects and reported them in the KLARF, the output file that lists the locations of the defects detected on the wafer along with some descriptive information such as the size of the scattering signal associated with them. The “Not Found” problem arose when the wafer was moved to the e-beam review system to identify defect type. As the e-beam review system drove to the sites of the defects found by the inspection tool, sometimes it didn’t see a defect. This situation can arise for any of several reasons. First, the inspection system could have experienced a glitch, a result of electrostatic discharge or system noise, and therefore reported a false event. Second, misalignment between the coordinate system of the inspector and that of the e-beam review system could have resulted in the defect lying outside the field of view (FOV) of the e-beam review system. Third, the inspection system could have detected a defect at a previous layer that’s covered by a film transparent to the (optical) inspection system but not to the e-beam review system. Fourth, the defect could have arisen from nuisance variation, such as line-edge roughness, that shows up as a defect when the inspector uses a die-to-die detection algorithm, but is not evident in a review image, which is viewed alone. In any of these cases, the defect will be classified as “Not Found” or “SNV.”

SNV Type One: False events. As defined above, false events are a rare occurrence for today’s wafer inspection systems. Advances in signal processing algorithms, mechanical and electrical subsystems, and system integration have virtually eliminated false events. (False events are not to be confused with nuisance defects, which are defects arising from real, physical phenomena on the wafer—that defect engineers have designated as not affecting yield, performance or reliability. Examples of nuisance defects besides line-edge roughness might include particles that reside in open areas and bridges within dummy pattern. Nuisance defects can be culled from defects-of-interest (DOI) through multiple means, including choice of wavelength, aperture and polarization in the inspection recipe, and by various defect classification schemes post-detection. Nuisance defects like particles on open areas might be successfully re-detected by the e-beam review system, then binned or classified as nuisance, or they might be SNV, like line-edge roughness.)

SNV Type Two: Field-of-View Errors. For previous-generation inspection and review tools, insufficient coordinate accuracy often meant that the e-beam review tool had to search for each defect using a large field of view, then “zoom in” to image the defect with sufficient resolution to allow its classification. This strategy had two drawbacks: 1) it was very time-consuming, and thus limited the number of defects that could be reviewed on a wafer so that a statistically representative defect population was nearly impossible to attain; and 2) with a large FOV, the resolution of the image was too low to find the smallest critical defects. It didn’t matter that the ultimate resolution of the review tool was a couple of nanometers; if that resolution had to be compromised while the system was searching for defects, a significant number of defects would be missed. Defect engineers began to realize that, while resolution of the e-beam system is necessary for defect classification, the tool’s ultimate resolution is useful only if the defects of interest can be located reliably. 

Recent advances in stage accuracy on the wafer inspection and review tools, and improved communication between the tools, have now made it possible for e-beam review tools to drive directly to the location of the defect using a sub-micron field of view. The latest e-beam review tools can now reliably and efficiently locate the smallest yield-critical defects reported by the latest inspection systems and, without zooming in, image these defects for classification. This breakthrough has had a tremendous effect on the reduction of SNV counts, and the redistribution of these counts to appropriate defect classes (see Figure). Having a defect pareto that more accurately represents the defects on the wafer allows defect engineers to direct their efforts toward solving the most critical problems.

SNV Types 3 and 4: Previous-Layer Defects and Nuisance Variation. With the matter of false events out of the way, and having ensured that the review system is looking in the right place, we are left the problem of separating previous-layer defects—which truly should be SEM non-visual—from SNV nuisance, i.e. defects correctly imaged by the e-beam review tool but difficult to identify as defects from the review image. If the layer inspected is transparent to the wavelength band of the optical inspection tool, then the possibility that the defect is from the previous layer should be considered. In some cases the previous layer was also inspected, in which case defect source analysis (DSA) can be used to compare the locations of the previous layer’s results to those of the current layer. If the possibility of previous-layer defects has been ruled out, the expertise of the defect engineer is essential for determining the source of the “defect.” If it’s nuisance variation, it may be possible to hone the defect classification schemes to disposition nuisance variation defects into their own category in the defect pareto. Alternatively, the defect engineer may need to adjust the recipe of the inspection system to lower its capture rate for these SNV defects, through choice of a different aperture, wavelength band or polarization mode.

Why does it matter that the SNV defects are properly categorized? Defect engineers act on the information given by the defect pareto, and a high SNV count can disguise or hide real problems. For example, some of these mysterious, disappearing defects may be important DOI lying just outside the field of view of a previous-generation review tool. A misleading defect pareto can result in a delay in getting a new process to yield, or even a delay in getting a new chip to market. Using every means possible to ensure that the defect pareto properly represents the defects on the wafer—especially those defects that affect device yield, performance or reliability—gives fabs the best chance to bring their products to market profitably and on time.

Rebecca Howland, Ph.D., is a senior director in the corporate group and Christina Wang is a senior product marketing manager in the e-beam technology division at KLA-Tencor.


Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”