Category Archives: Device Architecture

Amkor Technology Inc. (Nasdaq: AMKR), a semiconductor packaging and test service provider, this week announced it has shipped 700 million RF and front-end advanced system-in-package (SiP) modules for mobile device applications.

“Reaching this milestone affirms our leadership role in advanced SiP technologies,” said Steve Kelley, CEO and President of Amkor Technology Inc. “Our broad technology portfolio and engineering talent make Amkor an excellent choice for customers seeking high-performance, miniaturized solutions. In addition to building today’s laminate-based SiPs, we are also developing wafer-level SiP technology to enable the next generation of thinner, higher-performance electronic products.”

An advanced SiP module is composed of multiple semiconductor components with different functionalities which are combined into a single integrated circuit (“IC”) package. Advanced SiPs allow designers to squeeze more functionality into a smaller space, while increasing system performance and lowering system power consumption. Advanced SiPs use a variety of interconnect technologies including wire-bond, flip chip, copper pillars and through silicon vias (TSVs).

Amkor’s laminate-based SiPs are manufactured in high volumes and have fast cycle-time, making them very cost-effective. The company’s wafer-based Silicon Wafer Integrated Fan-out (SWIFT™) and Silicon-less Integrated Module (SLIM™) technologies provide thinner packages at finer line/space geometries and higher densities than laminate-based SiPs. Both SWIFT and SLIM offer a lower-cost alternative to TSV-based 2.5D and 3D packaging.

Researchers at MIT and other institutions have found a new phenomenon in the behavior of a kind of quasiparticles called plasmons as they move along tiny ribbons of two-dimensional materials such as graphene and TMDs (transition metal dichalcogenides), which have a hexagonal structure resembling chicken wire. The team found that these plasmons can be separated into two different streams moving in opposite directions at the edges of the ribbons, like traffic on a two-lane highway, without the need for strong magnetic fields or other exotic conditions.

The new research was carried out by MIT associate professor of mechanical engineering Nicholas X. Fang, recent PhD graduate from that department Anshuman Kumar, and four other researchers from the University of Wisconsin at Milwaukee, Hong Kong Polytechnic University, and the University of Minnesota. The work was reported in a paper in the journal Physical Review B.

Other groups had previously observed such separated flows, Fang says, but that previous work required the use of powerful magnetic fields. Instead, the new process relies largely on optical effects, he says, using beams of circularly polarized light.

The findings are based on exotic states of matter that can occur in two-dimensional materials that, unlike graphene, have a characteristic known as a bandgap, necessary for devices such as transistors or solar cells (and also in graphene that is modified to have a bandgap). These states of matter are based on quantum physics phenomena such as Berry curvature, which occur in configurations known as massive Dirac systems. Although such systems are a hot area of research these days, the researchers say this particular class of phenomena, involving surface electromagnetic properties known as surface plasmons, has been relatively unexplored until now.

Clustering in “valleys”

In the new work, the team showed that shining beams of circularly polarized light onto the graphene ribbons causes electrons in the material to cluster into two different “valleys” in the electronic band structure. The peculiar symmetry properties of this system gives rise to a phenomenon called Berry curvature, which can be thought of as an artificial magnetic field.

Under these conditions, these valleys correspond to motions of the plasmons — which are a kind of oscillation of electron density in the material — in opposite directions on the two edges of the material. The graphene ribbons are just 50 nanometers (billionths of a meter) in width.

This effective magnetic field can be measured by sending in a second polarized beam, whose transmission can then be detected so that the changes in its polarization give a direct measurement of the effects taking place in the surface plasmons.

“This is exciting,” Fang explains, because it opens up a whole new approach to both manipulating the electromagnetic behavior of such systems and measuring the results of these manipulations.

This could suggest possibilities for new kinds of electro-optical devices, he says. For example, some experimental photonic systems require devices called optical isolators, which prevent beams of light in precision optical systems from being reflected back to their source and causing interference. But these isolators, which require strong magnetic fields, are inherently bulky, he says, limiting the usefulness of such systems. “With this concept,” he says, “it’s possible to replace these bulky optical isolators with one monolayer of two-dimensional material.”

Chip-scale isolation

With such a system, Kumar says, it should be possible “to do chip-scale optical isolation without the need for a magnetic field.” To achieve the same degree of optical isolation that this system would provide with a beam of light, Kumar says, with a conventional system would require a magnetic field with a strength of 7 tesla — a very strong field that would require a special research facility. (By comparison, the Earth’s magnetic field measures just 32 millionths of a tesla).

Theoretically, this could lead to applications such as new types of memory devices where information could be both written and read by using beams of polarized light, making them relatively immune to electromagnetic or other kinds of interference, the researchers say.

Nanoelectronics research center imec presents at OFC 2016, the international event for both the science and business of optical communications held March 20-24, performance improvements of various key building blocks of its wafer-scale integrated silicon photonics platform (iSiPP). The new results expand imec’s iSiPP device portfolio to support 50Gb/s non-return-to-zero (NRZ) lane rates, and are an important milestone for the realization of high data rate silicon integrated optical interconnects targeting high density, high bandwidth, low power telecom and datacom transceivers, as well as for low cost large volume applications such as sensors or LiDAR.

Through process and design optimizations, imec has improved the operating speed of the silicon based traveling-wave mach-zehnder modulators and ring modulators to reach 50Gb/s NRZ lane rates. In addition, a C-band GeSi electro-absorption modulator was developed with electro-optical bandwidth beyond 50GHz, enabling NRZ modulation at 56Gb/s and beyond.  All modulator types can be driven with competitive drive voltages of 2Vpp or below, enabling compatibility with power efficient CMOS driver circuits.

The responsivity of the high-speed Ge photodetectors has been improved to 1A/W, enabling highly sensitive 50Gb/s NRZ receivers both in the C-band and the O-band. Also, edge coupling structures were developed for broadband optical coupling to high-NA and lensed fiber with less than 3dB insertion loss in the C-band. Moreover, designers can exploit the superior patterning fidelity provided by 193-nm lithography, enabling robust active and passive waveguide devices.

The 50Gb/s components are included in imec’s 200mm silicon photonics multi-project wafer (MPW) offer, and are supported by a Process Design Kit (PDK). The MPW service is available via Europractice IC service and MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs. Imec’s active iSiPP50G run is now open for registration (deadline June 28th 2016) with first wafers out in January 9th 2017.

Imec also provides technology customization options with dedicated wafer fabrication services supported by a PDK. This service enables the use of full-size reticles, delivery of full wafers, and access to specialty modules enabling high efficiency integrated heaters, MOSCAP devices and flip-chip assembly amongst others.

The PDK’s have been validated with silicon data, based on a minimum of two process runs for most of the components, and describe the process and device performance statistics. They are supported in various EDA environments and include DRC, supporting first-time right designs.

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IRT Nanoelec, an R&D consortium focused on information and communication technologies (ICT) using micro- and nanoelectronics, today announced the first co-integration of a III-V/silicon laser and silicon Mach Zehnder modulator demonstrating 25 Gbps transmission on a single channel. This transmission rate usually is achieved using an external source, over a 10 km single-mode fiber.

Current interconnect technologies, which use micro-optics integration to assemble a discrete laser and a silicon photonic circuit, will soon reach their limits and new, different solutions will have to be found to handle increasing traffic.

Integrating photonics capabilities on silicon chips is replacing currently established technologies, vastly increasing bandwidth, density and reliability, while dramatically reducing energy consumption. In the age of photonics-on-silicon, data transmission will be measured in terabits per second.

“Jointly obtained by STMicroelectronics and Leti in the frame of the IRT Nanoelec cooperation, these results, especially fabricating the laser directly on silicon, demonstrate IRT Nanoelec’s worldwide leadership in III/V-on-silicon integration to achieve high-data-rate fiber-optic modules,” said Stéphane Bernabé, project manager. “IRT Nanoelec and its partners on this project, Leti, STMicroelectronics, Samtec and Mentor Graphics, are paving the way to integrating this technology in next-generation transceivers for optical data links.”

To achieve these recent results, silicon photonics circuits integrating the modulator were processed first on a 200mm SOI wafer, although 300mm wafers also could be used in the near future. Then, a two-inch wafer of III-V material was directly bonded on the wafer. In the third step, the hybrid wafer was processed using conventional semiconductor and/or MEMS process steps to produce an integrated modulator-and-laser transmitter.

IRT Nanoelec launched its silicon photonics program in 2012, with core members Mentor Graphics, STMicroelectronics and CNRS. The program brings together, under one roof, the expertise and equipment needed to address the entire photonics-on-silicon value chain.

Leti, which will attend the Optical Fiber Communication Conference in Anaheim, Calif., March 20-24, and have a booth at the Exhibition Hall (3759), is a major innovation player in III-V/silicon integration for high-data-rate fiber optics modules.

Two-dimensional electronic devices could inch closer to their ultimate promise of low power, high efficiency and mechanical flexibility with a processing technique developed at the Department of Energy’s Oak Ridge National Laboratory.

A team led by Olga Ovchinnikova of ORNL’s Center for Nanophase Materials Sciences Division used a helium ion microscope, an atomic-scale “sandblaster,” on a layered ferroelectric surface of a bulk copper indium thiophosphate. The result, detailed in the journal ACS Applied Materials and Interfaces, is a surprising discovery of a material with tailored properties potentially useful for phones, photovoltaics, flexible electronics and screens.

This diagram illustrates the effect of helium ions on the mechanical and electrical properties of the layered ferroelectric: a.) Disappearance domains in the exposed area; as the mound forms yellow regions (ferroelectricity) gradually disappear; b.) Mechanical properties of the material; warmer colors indicate hard areas, cool colors indicate soft areas; c.) Conductivity enhancement; warmer colors show insulating areas, cooler colors show more conductive areas. Credit: ORNL

This diagram illustrates the effect of helium ions on the mechanical and electrical properties of the layered ferroelectric: a.) Disappearance domains in the exposed area; as the mound forms yellow regions (ferroelectricity) gradually disappear; b.) Mechanical properties of the material; warmer colors indicate hard areas, cool colors indicate soft areas; c.) Conductivity enhancement; warmer colors show insulating areas, cooler colors show more conductive areas. Credit: ORNL

“Our method opens pathways to direct-write and edit circuitry on 2-D material without the complicated current state-of-the-art multi-step lithographic processes,” Ovchinnikova said.

She and colleague Alex Belianinov noted that while the helium ion microscope is typically used to cut and shape matter, they demonstrated that it can also be used to control ferroelectric domain distribution, enhance conductivity and grow nanostructures. Their work could establish a path to replace silicon as the choice for semiconductors in some applications.

“Everyone is looking for the next material – the thing that will replace silicon for transistors,” said Belianinov, the lead author. “2-D devices stand out as having low power consumption and being easier and less expensive to fabricate without requiring harsh chemicals that are potentially harmful to the environment.”

Reducing power consumption by using 2-D-based devices could be as significant as improving battery performance. “Imagine having a phone that you don’t have to recharge but once a month,” Ovchinnikova said.

ARM and TSMC announced a multi-year agreement to collaborate on a 7nm FinFET process technology which includes a design solution for future low-power, high-performance compute SoCs. The new agreement expands the companies’ long-standing partnership and advances leading-edge process technologies beyond mobile and into next-generation networks and data centers. Additionally, the agreement extends previous collaborations on 16nm and 10nm FinFET that have featured ARM Artisan foundation Physical IP.

“Existing ARM-based platforms have been shown to deliver an increase of up to 10x in compute density for specific data center workloads,” said Pete Hutton, executive vice president and president of product groups, ARM. “Future ARM technology designed specifically for data centers and network infrastructure and optimized for TSMC 7nm FinFET will enable our mutual customers to scale the industry’s lowest-power architecture across all performance points.”

“TSMC continuously invests in advanced process technology to support our customer’s success,” said Dr. Cliff Hou, vice president, R&D, TSMC. “With our 7nm FinFET, we have expanded our Process and Ecosystem solutions from mobile to high performance compute. Customers designing their next generation high-performance computing SoCs will benefit from TSMC’s industry-leading 7nm FinFET, which will deliver more performance improvement at the same power or lower power at the same performance as compared to our 10nm FinFET process node. Jointly optimized ARM and TSMC solutions will enable our customers to deliver disruptive, first-to-market products.”

This latest agreement builds on ARM and TSMC’s success with previous generations of 16nm FinFET and 10nm FinFET process technology. The joint innovations from previous TSMC and ARM collaborations have enabled customers to accelerate their product development cycles and take advantage of leading-edge processes and IP. Recent benefits include early access to Artisan Physical IP and tape-outs of ARM Cortex-A72 processor on 16nm FinFET and 10nm FinFET.

Ceramic capacitors are used in a wide variety of electronics, ranging from computers and mobile phones to telecommunications transmitter stations and high voltage laser power supplies. Capacitors act, in a way, like batteries. They are “dielectric” – they act as an electronic insulator in which an electric field can be sustained with minimum loss of power. Their dielectric properties allow them to store electricity and then release it. One of the most widely used ceramics in capacitors is lead zirconate titanate, but it is hazardous to the health and the environment once it’s disposed. Scientists are trying to find other less hazardous ceramic materials for use in capacitors.

Perovskite oxynitrides – cheap and easily fabricated materials with a distinctive crystalline structure – are particularly promising. But ceramics manufactured from these materials need to be made denser to improve their insulating properties. This is usually done by applying intense heat; a process called “sintering”. However, sintering the material can lead to a change in its chemical composition, turning it from an insulator to an electrical conductor.

The researchers sintered the perovskite powder SrTaO2N at a temperature of 1723 Kelvin (1450° Celsius) for three hours. They then “annealed” the material by heating it with flowing ammonia at 1223 Kelvin (950° Celsius) for 12 hours and then allowing it to slowly cool.

They found that the surface of the material after this process (but not its interior) displayed an important dielectric property called “ferroelectricity”. This was the first time that a ferroelectric response has been observed on oxynitride perovskite ceramics, they say, making it promising as a new dielectric material for multi-layered ceramic capacitors.

A team of scientists from Hokkaido University and the multinational electronics company TDK Corporation in Japan has developed a method to improve the insulating properties of the oxynitride perovskite SrTaO2N for potential use as a ceramic capacitor. Credit: Tanusin Phunya/ 123rf

A team of scientists from Hokkaido University and the multinational electronics company TDK Corporation in Japan has developed a method to improve the insulating properties of the oxynitride perovskite SrTaO2N for potential use as a ceramic capacitor. Credit: Tanusin Phunya/ 123rf

Semico’s Inflection Point Indicator is a model developed by Semico Research, which has a history of accurately predicting semiconductor revenue inflection points four quarters in advance. After analyzing current trends, Semico announced this model indicates the semiconductor industry is repeating the pattern from 2011-2012, albeit at a muted level. Just in the past 4-5 years, the major end markets served by the semiconductor industry–tablets, notebooks, smartphones–have matured, causing growth rates to slow. On top of that, compared to 2012, most of the world’s economies are forecast to be weaker in 2016, with the exception of India. Finally, DRAM prices are expected to be weaker this year, compared to 2012. The positive growth in 2013-2014 was primarily due to the memory shortage and the subsequent rising prices.

Average selling prices (ASPs) in January recovered on lower revenues, which were down 6% year over year. Although ASPs rose 4.0% in January, they are still historically low.

Semico president Jim Feldhan commented, “In the past 8 months, the industry has seen ASPs in the $0.41 range 5 times. One has to go back to May 2009 to find a lower price, and 2009 was not a good year!”

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The IPI Report is Semico’s most popular report series that accurately predicts semiconductor revenue inflection points four quarters in advance.

GLOBALFOUNDRIES today announced new advanced radio-frequency (RF) silicon solutions, further expanding the portfolio of Silicon Germanium (SiGe) power amplifier (PA) technologies designed to enable performance-optimized cellular and Wi-Fi solutions in increasingly sophisticated mobile devices and hardware.

GLOBALFOUNDRIES’ 5PAx and 1K5PAx, together called PAx, are the latest extensions to its broad family of SiGe-based PA technologies. The advanced offerings deliver optimized PA, LNA and switch technology with improved power efficiency, noise figure and insertion loss enabling more power efficient next-generation Wi-Fi and cellular solutions for faster data access and uninterrupted connections.

“Mobile suppliers are facing mounting pressure to expand network capacity as wireless data consumption continues to increase rapidly,” said Dr. Bami Bastani, senior vice president of GLOBALFOUNDRIES RF business unit. “Our broad portfolio of high-performance SiGe power amplifier technologies provides a distinct design, performance and cost advantage that enables our mobility customers to deliver cost-effective solutions with faster data throughput, support wider coverage areas, and consume less power.”

Skyworks, a leader in high-performance analog semiconductor solutions, plans to use the technology to enhance both the power capability and efficiency for the next generation of mobile WLAN products and high-performance WLAN products, including access points, routers and IoT applications.

“The advances that are part of GLOBALFOUNDRIES’ SiGe PAx technologies enable RF front-end solutions for all levels of performance and complexity,” said Bill Vaillancourt, vice president and general manager of Mobile Connectivity at Skyworks Solutions. “With these advanced features and the ability to minimize form factor by implementing multiple RF functions on a chip, GLOBALFOUNDRIES’ latest PAx offerings enhance the capabilities of integrated semiconductor solutions that support customers’ needs for high performance, cost effective technologies addressing portable wireless communication devices.”

There are four technologies in GLOBALFOUNDRIES’ SiGe PA family, SiGe 5PAe, 1KW5PAe, and now 5PAx and 1K5PAx. All four offerings feature GLOBALFOUNDRIES’ proven through-silicon via technology and provide significant performance, integration functionality and cost advantages for customers who are currently using gallium arsenide (GaAs)-based alternatives. Today, there are more than three billion SiGe power amplifiers shipped worldwide using this family of technologies, and GLOBALFOUNDRIES has recently invested in additional manufacturing capacity to address the anticipated growth in the mobile sector. The newest offerings, 5PAx and 1K5PAx, are optimized to meet the rigorous demands of evolving mobile standards like 802.11ac, which demands three times faster data throughput than the previous generation of standards.

For 5GHz applications, SiGe 5PAx, the follow-on to SiGe 5PAe, supports 2dB gain along with a 5 percent PAE and 0.2dB low noise amplifier (LNA) improvements relative to the previous generation. SiGe 1K5PAx, like its predecessor 1KW5PAe, is built on a high-resistivity substrate, and is tuned for integration and higher performance. It features RF switches with approximately 15 percent better Ron-Coff compared to 1KW5PAe, and like 1KW5PAe, enables designers to minimize form factor by implementing multiple functions, such as power amplifiers, RF switches and LNAs, on a single chip.

Chemical precursors (inorganic and organic) used to form high dielectric constant (High-K) materials, metals and metal nitrides needed in advanced ICs are forecasted to reach $400M USD in global sales by 2020, as highlighted in TECHCET’s 2016 Critical Materials Report. Estimated to have totaled over $258M in 2015, this market consists of ~51% high-k metal precursors used for gate dielectrics and capacitors, and ~49% other metal precursors used for electrode and interconnect processes.

The largest usage for High K ALD and CVD (Atomic Layer Deposition and Chemical Vapor Deposition) precursors will continue to be capacitor formation for volatile memory devices through 2020. However, it is expected that revenues for High-K gate oxides processes may surpass memory capacitors by 2021. Compared to CVD, the ALD process relies on unique properties of precursors to self-limit reactions at the atomic level, so ALD precursors are generally chemically engineered complex molecules that command relatively higher average selling prices.

Atomic Layer Etching (ALE) is a new technology similar to ALD, in that alternating sequential surface-limited steps remove precise layers. When engineering atom-scale device features, chip fabricators will continue to rely on such high precision processes employing new and existing materials to enable high quality surfaces. Besides the physical plasma assisted path to ALE employing Cl2 and Ar ions, the chemical path to ALE uses metal organic compounds and hydro fluoric acid, and recent research is focused on using tin(II) acetylacetonate and other beta-diketonates.

Understanding the complex dynamics of materials interactions are critical to the successful use of novel processes and materials in IC HVM. Challenges and opportunities relating to the affordable, controllable, and safe implementation of new materials will be presented in detail at the Critical Materials Conference 2016—open to the public May 5-6, in Hillsboro, Oregon—in conjunction with the private Critical Materials Council (CMC) meetings. For more info on TECHCET’s Report or to Register for the CMC Conference, please go to www.cmcfabs.org/seminars/ or contact [email protected]

TECHCET’s work is focused on process materials supply-chains and materials technology trends for Semiconductor, Display, Solar/PV, and LED manufacturing industries. The company has been responsible for producing the Critical Material Reports for SEMATECH and the industry since 2000. This work continues to benefit the Critical Materials Council, now organized as CMC Fabs. For more info please go to: www.cmcfabs.org or www.techcet.com