Category Archives: EULV

Vacuum pumps, pressure gauges and vacuum valves combined make up the biggest expense on the bill of materials for semiconductor OEMs. In 2016, just over $1.9 billion of vacuum subsystems were consumed by the semiconductor industry and more than half were supplied by European vendors, according to VLI Research.

Vacuum-Subsystem-image1

Vacuum subsystems sales account for one third of expenditures on all critical subsystems used on semiconductor manufacturing equipment (excluding optical subsystems). The increase in vacuum process intensity of the semiconductor industry means that by 2022, the market for vacuum subsystems could be up to 62 percent higher than today’s value of $1.9 billion, reaching a market size of $3.1 billion.

The growing number of vacuum process steps has been driven by multiple patterning and the successful introduction of 3D NAND. Both require additional deposition and etch steps and, in the case of 3D NAND, longer and more difficult etch processes. On the negative side, this has increased costs for chipmakers and is driving the adoption of Extreme Ultraviolet lithography (EUV) which reduces the reliance on multiple patterning. However, even with EUV (which is a vacuum process), the number of deposition and etch steps are still expected to increase, albeit at a lower rate. This explains why the forecast is for sales of vacuum subsystems to outgrow the market over the next five years.

Vacuum-Subsystem-image2

The top five vacuum subsystem suppliers account for 68 percent of the market and is dominated by four European based vendors. In 2016, over 58 percent of all vacuum subsystems were sold by European companies and is a reflection of the European origins of vacuum technology. The Japanese vendors as a group make up 21 percent of the total while North American vendors supply 16 percent.

There is a push for more localisation of vacuum subsystem supply especially in Korea and China but to date this has not resulted in a serious local supplier emerging to challenge the incumbents. The strong hold that Europeans and Japanese have on the technology mean that we are unlikely to see any meaningful regional shifts in supply in the foreseeable future.

The expectation is that vacuum subsystems suppliers will continue to make a valuable contribution to semiconductor manufacturing over the long-term as the trend for more vacuum process steps continues.

By Ed Korczynski, Senior Technical Editor

The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

“Mix and Match” has long been a mantra for lithographers in the deep-sub-wavelength era of IC device manufacturing. In general, forming patterns with resolution at minimum pitch as small as 1/4 the wavelength of light can be done using off-axis illumination (OAI) through reticle enhancement techniques (RET) on masks, using optical proximity correction (OPC) perhaps derived from inverse lithography technology (ILT). Lithographers can form 40-45nm wide lines and spaces at the same half-pitch using 193nm light (from ArF lasers) in a single exposure.

Figure 1 shows that application-specific tri-layer photoresists are used to reach the minimum resolution of 193nm-immersion (193i) steppers in a single exposure. Tighter half-pitch features can be created using all manner of multi-patterning processes, including Litho-Etch-Litho-Etch (LELE or LE2) using two masks for a single layer or Self-Aligned Double Patterning (SADP) using sidewall spacers to accomplish pitch-splitting. SADP has been used in high volume manufacturing (HVM) of logic and memory ICs for many years now, and Self-Aligned Quadruple Patterning (SAQP) has been used in at least one leading memory fab.

FIGURE 1. Basic tri-layer resist (TLR) technology uses thin Photoresist over silicon-containing Hard-Mask over Spin-On Carbon (SOC), for patterning critical layers of advanced ICs. (Source: Brewer Science)

FIGURE 1. Basic tri-layer resist (TLR) technology uses thin Photoresist over silicon-containing Hard-Mask over Spin-On Carbon (SOC), for patterning critical layers of advanced ICs. (Source: Brewer Science)

Next-Generation Lithography (NGL) generally refers to any post-optical technology with at least some unique niche patterning capability of interest to IC fabs: Extreme Ultra-Violet (EUV), Directed Self-Assembly (DSA), and Nano-Imprint Lithography (NIL). Though proponents of each NGL have dutifully shown capabilities for targeted mask layers for logic or memory, the capabilities of ArF dry and immersion (ArFi) scanners to process >250 wafers/ hour with high uptime dominates the economics of HVM lithography.

The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

It is looking most likely that the answer is “all of the above.” EUV and NIL could be used for single layers. For other unique patterning application, ArF/ArFi steppers will be used to create a basic grid/template which will be cut/trimmed using one of the available NGL. Each mask layer in an advanced fab will need application-specific patterning integration, and one of the rare commonalities between all integrated litho modules is the overwhelming need to improve pattern overlay performance.

Naga Chandrasekaran, Micron Corp. vice president of Process R&D, provided a fantastic overview of the patterning requirements for advanced memory chips in a presentation during Nikon’s LithoVision technical symposium held February 21st in San Jose, California prior to the start of SPIE-AL. While resolution improvements are always desired, in the mix-and-match era the greatest challenges involve pattern overlay issues.

“In high volume manufacturing, every nanometer variation translates into yield loss, so what is the best overlay that we can deliver as a holistic solution not just considering stepper resolution?” asks Chandrasekaran.

“We should talk about cost per nanometer overlay improvement.”

Extreme Ultra-Violet (EUV)

As touted by ASML at SPIE-AL, the brightness and stability and availability of tin-plasma EUV sources continues to improve to 200W in the lab “for one hour, with full dose control,” according to Michael Lercel, ASML’s director of strategic marketing. ASML’s new TWINSCAN NXE:3350B EUVL scanners are now being shipped with 125W power sources, and Intel and Samsung Electronics reported run their EUV power sources at 80W over extended periods.

During Nikon’s LithoVision event, Mark Phillips, Intel Fellow and Director of Lithography Technology Development for Logic, summarized recent progress of EUVL technology: ~500 wafers-per-day is now standard, and ~1000 wafer-per-day can sometimes happen. However, since grids can be made with ArFi for 1/3 the cost of EUVL even assuming best productivity for the latter, ArFi multi-patterning will continue to be used for most layers.

“Resolution is not the only challenge,” reminded Phillips. “Total edge-placement-error in patterning is the biggest challenge to device scaling, and this limit comes before the device physics limit.”

Directed Self-Assembly (DSA)

DSA seems most suited for patterning the periodic 2D arrays used in memory chips such as DRAMs. “Virtual fabrication using directed self-assembly for process optimization in a 14nm DRAM node” was the title of a presentation at SPIE-AL by researchers from Coventor in which DSA compared favorably to SAQP.

Imec presented electrical results of DSA-formed vias, providing insight on DSA processing variations altering device results. In an exclusive interview with Solid State Technology and SemiMD, imec’s Advanced Patterning Department Director Greg McIntyre reminds us that DSA could save one mask in the patterning of vias which can all be combined into doublets/triplets, since two masks would otherwise be needed to use 193i to do LELE for such a via array. “There have been a lot of patterning tricks developed over the last few years to be able to reduce variability another few nanometers. So all sorts of self-alignments.”

While DSA can be used for shrinking vias that are not doubled/tripled, there are commercially proven spin-on shrink materials that cost much less to use as shown by Kaveri Jain and Scott Light from Micron in their SPIE-AL presentation, “Fundamental characterization of shrink techniques on negative-tone development based dense contact holes.” Chemical shrink processes primarily require control over times, temperatures, and ambients inside a litho track tool to be able repeatably shrink contact hole diameters by 15-25 nm.

Nano-Imprint Litho (NIL)

For advanced IC fab applications, the many different options for NIL technology have been narrowed to just one for IC HVM. The step-and-pattern technology that had been developed and trademarked as “Jet and Flash Imprint Lithography” or “J-FIL” by, has been commercialized for HVM by Canon NanoTechnologies, formerly known as Molecular Imprints (http://cnt.canon.com/). Canon shows improvements in the NIL mask-replication process, since each production mask will need to be replicated from a written master. To use NIL in HVM, mask image placement errors from replication will have to be reduced to ~1nm, while the currently available replication tool is reportedly capable of 2-3nm (3 sigma).

Figure 2 shows normalized costs modeled to produce 15nm half-pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. Key to throughput is fast filling of the 26mmx33mm mold nano-cavities by the liquid resist, and proper jetting of resist drops over a thin adhesion layer enables filling times less than 1 second.

FIGURE 2. Relative estimated costs to pattern 15nm half- pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. (Source: Canon)

FIGURE 2. Relative estimated costs to pattern 15nm half- pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. (Source: Canon)

Researchers from Toshiba and SK Hynix described evaluation results of a long-run defect test of NIL using the Canon FPA-1100 NZ2 pilot production tool, capable of 10 wafers per hour and 8nm overlay, in a presentation at SPIE-AL titled, “NIL defect performance toward high- volume mass production.” The team categorized defects that must be minimized into fundamentally different categories—template, non-filling, separation-related, and pattern collapse—and determined parallel paths to defect reduction to allow for using NIL in HVM of memory chips with <20nm half-pitch features.

Nano-electronics research center imec and Cadence Design Systems, Inc. today announced that the companies completed the first tapeout of a 5nm test chip using extreme ultraviolet (EUV) as well as 193 immersion (193i) lithography. To produce this test chip, imec and Cadence optimized design rules, libraries and place-and-route technology to obtain optimal power, performance and area (PPA) scaling via Cadence (R) Innovus (TM) Implementation System. Using a processor design, imec and Cadence successfully taped out a set of designs using EUV lithography as well as Self-Aligned Quadruple Patterning (SAQP) for 193i lithography, where metal pitches were scaled from the nominal 32nm pitch down to 24nm to push the limit of patterning.

The Innovus Implementation System is a next-generation physical implementation solution that enables system-on-chip (SoC) developers to deliver designs with best-in-class PPA while accelerating time to market. Driven by a massively parallel architecture with breakthrough optimization technologies, the Innovus Implementation System provides typically 10 to 20 percent better PPA and up to 10X full-flow speedup and capacity gain. For more information on the Innovus Implementation System, please visit http://www.cadence.com/news/innovus.

“Our collaboration with Cadence plays an important part in the development of the world’s most advanced geometries including 5nm and below,” said An Steegen, senior vice president of Process Technology at imec. “Together, we developed the necessary technology to enable tapeouts for advanced technology nodes such as this test chip. The Cadence next-generation platform is easy to use, which helps our engineering team stay productive in developing the rule set for advanced nodes.”

“By achieving this milestone, Cadence and imec continue to demonstrate our dedication toward pushing patterning technologies to increasingly smaller nodes,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “With imec technology and the Cadence Innovus Implementation System, we’ve created a working flow that can pave the way for developing innovative next-generation mobile and computer advanced-node designs.”

The eBeam Initiative, a forum dedicated to the education and promotion of new semiconductor manufacturing approaches based on electron beam (eBeam) technologies, today announced the completion of its fourth annual eBeam Initiative members’ perceptions survey. A record 64 industry luminaries representing 35 different companies from across the semiconductor ecosystem–including chip design, equipment, materials, and manufacturing, as well as photomasks–participated in this year’s survey. The eBeam Initiative also completed its first-ever merchant and captive mask makers’ survey. In related news, ZEISS, a company in lithography optics for semiconductor manufacturing, has joined the eBeam Initiative.

Among the results of the members’ perception survey, respondents expressed increased optimism in the implementation of EUV lithography for semiconductor high-volume manufacturing (HVM) compared to last year’s survey, while at the same time acknowledging that EUV lithography is expected to add greater complexity to photomask manufacturing. In addition, expectations on the use of multi-beam technology for advanced photomask manufacturing continue to remain strong. Results from the eBeam Initiative’s first mask makers survey–which not only provides insight into the challenges and opportunities for photomask manufacturers but also gives mask makers a way to assess their own progress relative to their peers–indicate growing mask complexity across many fronts. The complete results of both surveys will be presented and discussed by an expert panel today during the eBeam Initiative’s annual members meeting at the SPIE Photomask Technology Conference in Monterey, Calif., and are available for download at www.ebeam.org.

Highlights from eBeam Initiative Member Survey

  • 62 percent of respondents predict that multi-beam technology will begin to be used for photomask production by the end of 2016 to address the critical problem of mask write times as the industry moves to smaller geometries.
  • Mask makers appear to be the most optimistic about the availability of multi-beam mask writers, with a near-unanimous 96 percent of mask makers participating in the survey indicating that multi-beam will be used for HVM mask writing by the end of 2018, compared to 65 percent of all equipment suppliers.
  • Among five next-generation lithography (NGL) technologies being considered for advanced semiconductor fabrication, respondents predict EUV as the most likely NGL method to be used in at least one manufacturing step by 2020, with an average confidence rating of 62%.
  • At the same time, 59 percent of respondents predict that EUV will drive the need for complex mask shapes.

Highlights from Mask Makers Survey (data from Q3 2014 through Q2 2015)

  • Mask sets below the 22-nm logic node are exceeding 60 masks for the first time, while mask sets have seen a long-term growth rate of 13 percent since the 250-nm node.
  • Average mask writes times have exceeded the nine-hour mark (9.6 hours) while the longest write time reported was 72 hours.
  • A strong majority (75 percent) of mask makers predict that they will modulate exposure dose on a per-shot basis in 2017.

“eBeam technology is critical to enabling the continuation of Moore’s Law, regardless of which lithography approach is used for semiconductor design and cost scaling,” stated Dr. Markus Waiblinger, senior product manager, strategic business unit Semiconductor Metrology Systems of ZEISS. “As an innovator in the use of eBeam technology for optical and EUV mask inspection, review and repair solutions, ZEISS applauds the eBeam Initiative for educating the semiconductor supply chain about new developments in eBeam technology and for providing a forum for greater collaboration. Efforts like the annual members’ survey and now their first mask makers’ survey play an important role in fulfilling that charter, and we’re pleased to have the opportunity to participate as a new member of the eBeam Initiative.”

“On behalf of the eBeam Initiative, I wish to thank all of our members–including our newest member ZEISS–for their participation in our fourth annual members’ perception survey,” stated Aki Fujimura, CEO of D2S, the managing company sponsor of the eBeam Initiative. “2015 has truly been an exciting year for the Initiative, as members of the eBeam community continue to step forward with new solutions to solve some of the semiconductor and photomask industry’s most pressing manufacturing challenges. Interest and excitement in eBeam technology continues to grow, which is reflected in the record turnout of responses that we received for our annual survey, as well as the strong reception from the global mask community toward our inaugural mask makers’ survey. Feedback from these surveys is invaluable in helping guide our education efforts within the eBeam supply chain, and we look forward to presenting our results for both surveys at the SPIE Photomask Conference later today.”

Veeco Instruments Inc. announced today that its new Odyssey Ion Beam Deposition (IBD) Upgrade for the NEXUS IBD-LDD System has repeatedly produced photomask blanks with zero deposition defects larger than 70nm. This represents a significant milestone toward the manufacture of semiconductor devices with advanced extreme ultraviolet (EUV) lithography.

EUV mask blank defects are, as a practical matter, impossible to repair and can render a semiconductor device useless. Because of this, mask blank defects have been a key obstacle toward high volume manufacturing. Veeco’s low-defect Odyssey IBD technology clears the way for further EUV manufacturing advancements for semiconductor devices.

“EUV lithography brings chipmakers the ability to manufacture higher performing devices at lower cost compared to manufacturing methods which rely on multiple patterning steps,” said Ron Kool, Senior Vice President of EUV Product and Service Marketing at ASML. “As ASML is making steady progress preparing the scanner and light source for industrial high volume manufacturing, the readiness of the EUV industry, including mask blanks, is critically important to our customers. Veeco’s dedication to the Odyssey upgrade program, done in coordination with customers, consortia, and other industry stakeholders, is a model for EUV infrastructure advancements.”

Veeco IBD technology features extremely low particulate deposition and precise control of optical properties for single or multi-layer processes. These technology features are required for defect-free, high volume EUV manufacturing. Currently, all of the leading EUV mask blank manufacturers use the Veeco NEXUS IBD-LDD system.

“Veeco is committed to working with our customers and industry partners to advance the EUV roadmap and increase the output of defect-free mask blanks,” said Jim Northup, Senior Vice President and General Manager of Veeco Advanced Deposition & Etch. “We have made significant investments in the Odyssey upgrade and consolidated our optical coating and ion beam resources in a single R&D site to ensure ongoing development of our IBD technology.”

Blog Review October 14 2013


October 14, 2013

At the recent imec International Technology Forum Press Gathering in Leuven, Belgium, imec CEO Luc Van den hove provided an update on blood cell sorting technology that combines semiconductor technology with microfluidics, imaging and high speed data processing to detect tumorous cancer cells. Pete Singer reports.

Pete Singer attended imec’s recent International Technology Forum in Leuven, Belgium. There, An Steegan, senior vice president process technology at imec, said FinFETs will likely become the logic technology of choice for the upcoming generations, with high mobility channels coming into play for the 7 and 5nm generation (2017 and 2019). In DRAM, the MIM capacitor will give way to the SST-MRAM. In NAND flash, 3D SONOS is expected to dominate for several generations; the outlook for RRAM remains cloudy.

At Semicon Europa last week, Paul Farrar, general manager of G450C, provided an update on the consortium’s progress in demonstrating 450mm process capability. He said 25 tools will be installed in the Albany cleanroom by the end of 2013, progress has been made on notchless wafers with a 1.5mm edge exclusion zone, they have seen significant progress in wafer quality, and automation and wafer carriers are working.

Phil Garrou reports on developments in 3D integration from Semicon Taiwan. He notes that at the Embedded Technology Forum, Hu of Unimicron looked at panel level embedded technology.

Kathryn Ta of Applied Materials connects how demand for mobile devices is driving materials innovation. She says that about 90 percent of the performance benefits in the smaller (sub 28nm) process nodes come from materials innovation and device architecture. This number is up significantly from the approximate 15 percent contribution in 2000.

Tony Massimini of Semico says the MEMS market is poised for significant growth thanks to major expansion of applications in smart phone and automotive. In 2013, Semico expects a total MEMS market of $16.8 B but by 2017 it will have expanded to $28.5 B, a 70 percent increase in a mere four years time.

Steffen Schulze and Tim Lin of Mentor Graphics look at different options for reducing mask write time. They note that a number of techniques have been developed by EDA suppliers to control mask write time by reducing shot count— from simple techniques to align fragments in the OPC step, to more complex techniques of simplifying the data for individual writing passes in multi-pass writing.

If you want to see SOI in action, look no further than the Samsung Galaxy S4 LTE. Peregrine Semi’s main antenna switch on BSOS substrates from Soitec enables the smartphone to support 14 frequency bands simultaneously, for a three-fold improvement in download times.

Vivek Bakshi notes that a lot of effort goes into enabling EUV sources for EUVL scanners and mask defect metrology tools to ensure they meet the requirements for production level tools. Challenges include modeling of sources, improvement of conversion efficiency, finding ways to increase source brightness, spectral purity filter development and contamination control. These and other issues are among topics that were proposed by a technical working group for the 2013 Source Workshop in Dublin, Ireland.


Dr. Vivek Bakshi blogs about EUV Lithography (EUVL) and related topics of interest. He has edited two books on EUVL and is an internationally recognized expert on EUV Source Technology and EUV Lithography. He consults, writes, teaches and organizes EUVL related workshops. WWW.euvlitho.com

In order to bring EUVL scanners into high volume manufacturing (HVM) of computer chips, its throughput of 10 wafers per hour (WPH) needs to increase. That brings up three questions: how much do we need to increase the current throughput for HVM insertion, what needs to be done to increase throughput, and how quickly can this increase be achieved?

Throughput of EUVL scanner for HVM insertion

Imaging by EUVL scanner offers a higher k1 value than is available from 193 immersion (193i) based lithography. A higher k1 value results in better imaging and lower lithography process complexity, hence the attraction of EUVL as an optical projection lithography.

Today, 193i scanners are used in a double pattering process to print the smallest features needed in HVM. Toward 14 nm and smaller nodes, if EUVL is not ready, chipmakers will need to use quadruple patterning with 193i scanners, combined with increased optical proximity correction (OPC) and design rules restrictions to print increasingly smaller features. This is not an attractive option for chipmakers, hence their increasing emphasis on EUVL readiness. As manufacturers evaluate available technology, switching from double patterning-based 193i to EUVL, throughput is most often mentioned as the criterion for evaluation.

As printing of circuits is a sequential process, in double patterning (DP) the same wafer is exposed twice in a 193i scanner. Between the two exposures, there are many additional processing steps to enable the DP process. Hence, we need less than 50% throughput from an EUVL scanner (as compared to 193i scanners) to achieve a given feature size. In the case of quadruple pattering, an EUVL scanner needs less than 25% throughput to compare with an immersion scanner due to the four exposures.  After accounting for the additional processes of deposition, etch, ash and metrology, the equivalent throughput of an EUVL scanner may become less than 40% and 20% to compete with double and quadruple patterning, respectively. Thus, to match the throughput of a 200 WPH 193i scanner for DP process , we need less than 80 WPH and 40 WPH from an EUVL scanner. This is an important point, as it’s often said in press that an EUVL scanner must reach the throughput of a 193i scanner to be considered equal. (Cost of Ownership wise, the Lithography team of the International Technology Roadmap for Semiconductors (ITRS) has already shown that EUVL is more cost-effective than 193i DP for next generation lithography (NGL) [1]).

How to increase EUVL scanner throughput

Of course, EUVL scanners still need to boost their throughput numbers from the current 10 WPH.  For economic reasons, it’s best to have throughput as high as possible from an EUVL scanner.  Although much focus is placed on sources for improving throughput, other things can be done to increase the productivity of an EUVL scanner.

To better understand the challenge, let’s start with a model that estimates throughput of an EUVL scanner for 1) a given source power, 2) scanner parameters, and 3) reflection/transmission efficiency of various components [2]. EUVL scanners are not very efficient in transferring photons from source to wafer. Hence, in addition to increasing the number of photons available to the scanner, we can also work to increase its transmission. It is important to note the relationship of scanner throughput to scanner’s overhead time and resist sensitivity. [2] For example, for 50 W of source power at intermediate focus (IF), 20 mJ resist will allow 30 WPH while 10 mJ resist will allow 55 WPH. For a 10 mJ resist at 80 WPH, we need 115 W of power for 18 s overhead time, while for the 10 s overhead time we need only 50 W of power! [2]

There are additional factors that can help increase throughput. By decreasing the resist sensitivity to out-of-band radiation, the need for spectral purity filters may be eliminated. Reflection of mask as well as effective reflection of optics can be increased as well. Optical throughput of the NXE3300B is supposed to be 50% more than the NXE3100 [3] so there is already progress in increasing scanner throughput.

EUV sources are a difficult challenge due to the inherent complexity of reliable and repeatable generation of high temperature plasma of 40 eV for a production environment.  Current EUV source conversion efficiency (CE) is only 2 % (i.e., 2% of input energy is converted into EUV photons). Of these photons, only about 10% can be collected due to the limitations of collector optics, debris mitigation and spectral purity filters. We need improvement in each of these areas to enable higher power and increased throughput. CE of 5.5 % has been demonstrated recently, larger collectors are being developed and debris mitigation techniques will continue to improve – all allowing more photons to reach the wafer.

How higher scanner throughput can be achieved quickly

There is no magic bullet, so lots of innovative solutions are needed to lessen various loss factors to reach 100 W of source power. Beyond that, we may need different approaches to key source components  such as fuel delivery. In meetings at the 2012 International Workshop on EUV and Soft X-Ray Sources (Dublin, Ireland, October 8-11), the largest annual gathering of EUV source experts, we can expect discussion on some of these key topics in EUV source development. The workshop will include:

· Several papers on how to increase CE of sources for both EUV and beyond BEUV ( 6.x nm) LPP sources

· New designs to allow higher power DPP sources

· Data on the latest SPF of up to 80% transmission, improved collector optics, and other topics

I look forward to seeing the latest results from the industry’s source experts and will report them on this site.

In summary, I expect a rather slow but steady increase in EUV source power, and I’m still on record as predicting enough throughput by 2014 to allow adoption of EUVL scanners for HVM by leading chipmakers.

References:

1. Lithography Chapter, International Technology Roadmap for Semiconductors (2009).

2. Chapter 3, “EUV Source Technology,” in EUV Lithography, Vivek Bakshi (Editor), SPIE Press 2008, for discussion of a general throughput model for an EUVL scanner.

3. Rudy Peters, ASML presentation at the 2011 EUVL Symposium.

Dr. Vivek Bakshi blogs about EUV Lithography (EUVL) and related topics of interest. He has edited two books on EUVL and is an internationally recognized expert on EUV Source Technology and EUV Lithography. He consults, writes, teaches and organizes EUVL related workshops. WWW.euvlitho.com

Vivek Bakshi, EUV Litho Inc., February 28, 2013

Technical Highlights

The 2013 SPIE Advanced Lithography EUVL Conference started with many of us looking forward to Sam Sivakumar’s  kickoff presentation on results from Intel’s EUVL pilot line. Sivakumar pointed out that printing vias and cuts is the real advantage of EUVL over 193nm immersion based lithography (193i). In order to investigate the feasibility of extreme ultraviolet Lithography (EUVL), his group produced the same 22 nm products that Intel manufactures using 193i scanners. Products made using EUVL demonstrated equal or better performance, and most importantly lacked EUV-specific defect nodes. He noted source power and particles added to the mask during manufacturing as two major challenges for EUVL. The source power issue is not new, but particles on pellicles can make EUVL manufacturing prohibitive.

Surprisingly, in the third paper of the session, ASML presented elegant results on development of EUVL pellicles – with 86% transmission (against 90% needed) that meet imaging and mechanical requirements and only need some scaling. These pellicles have almost no effect on imaging, unless the particles are larger than 1 micron, and can be fully cleaned as well. Also, if the pellicle breaks by accident, ASML said they can clean the mask using a dry clean process.

Scanner Status by ASML

ASML is essentially an integrator and their update was full of continuous improvements. NXE3300B is a solid improvement over NXE3100. In their presentations, one sees ASML’s style of making innovation and improvement part of business as usual. What I like the most about ASML is that they do not play the "blame game." They never say in public, "if sources are ready, we will have the tool ready." If they become an EUVL source supplier through their acquisition of Cymer, we will see if this attitude changes.

The most important information that I got out of ASML’s presentation was how source power will relay to throughput, a relationship that will help us figure out the progress of EUVL. Scanner stages are ready for 100 wafers per hour (WPH) tools and if mask fields need to be split for higher numerical aperture (NA), I expect that they will be able to turn this knob a little to partially compensate for throughput loss. NXE3100 scanners are supposed to have a throughput range of 6 – 60 WPH and NXE3300B scanners of 50-125 WPH. The ratio of source power to WPH will increase from about 1 now (10 WPH for 10 W with NXE3000) to 1.25 (43 WPH at 55 W for NXE3100 in the near future). For NXE3300B, the ratio will rise to 1.6 (80 W for 50 WPH) and then to 2 (250 W for 125 WPH). I expect this to be due mostly to higher dose requirements, plus a few other factors such as availability and reduced scanner throughput at higher NA.

Source Technology Status

Some progress has been made, but a large gap remains. 40 W in 2014 from Cymer looks promising. I am also somewhat optimistic about 60 W with 100% duty cycle (DC) and long term operation by the end of next year, at least in non-integrated sources.

1) Ushio, maker of laser-assisted discharge produced plasma (LDP) sources, showed that they now have > 80% availability for their 6 W source at IMEC’s 3100. They have now demonstrated 51 W at 80% DC for 1 hour and 74 W at 12% DC for couple of minutes. As it has taken them a long time to realize acceptable high availability of 6 W sources, we know that scaling is no small task. It was not clear if LDP will be used for first NXE3300B prototypes, as was done for NXE3100.

2) Gigaphoton had > 7 W in 2012 from their Sn laser produced plasma (LPP) sources but they noted the scaling challenge and went back to the drawing board to address the issues of reliable droplet generation, pre-pulse laser for high conversion efficiency (CE) and debris mitigation. After proof of principal of their new design, they are working now to scale up their source from a current 10 W at low duty cycle, using 20 micron drops and 5 kW CO2 laser. Their new approach looks technically solid and I am expecting good progress this year. For 250 W Sn LPP sources, they are working on a 40 kW CO2 laser module.

3) Cymer’s sources in the field are averaging 10 W today with > 65% availability. These sources have >  0.5% dose stability. For upgrades, they have a 40 W source with 0.2% dose stability that they have used for 100% duty cycle for six one-hour runs. They also had a one-hour run of a 55 W source and feasibility of 60 W was demonstrated. This technology is for NXE3100 sources and they expect it to be ready for the scanners by Q3 of this year. They still will need to transfer this technology to NXE3300B, so I am not sure when the 80 W sources needed for these scanners will be ready. I will be delighted if 40 -50 W sources are ready and in the field in 2014. The Cymer team has done good work and has a roadmap for 250 W; but inasmuch as they have talked for many years about delivering high levels of source power and have not been able to do so, there was some skepticism in the audience toward their roadmap.

New Technical Solutions

The conference presented a large number of solutions for EUVL challenges, and several were good news:

1) A paper by Nissan Chemical (8682-9) titled, "The novel solution for negative impact of out-of- band (OBB) radiation and outgassing by top coat materials in EUVL," provided welcome news about OOB radiation and resist outgassing. Topcoat on resist was shown to eliminate OOB radiation from source as well as outgassing. It was a relief, as there has been ongoing discussion about the extent of OOB radiation, its effect on imaging and losses in a spectral purity filter (SPF).  So now we may not have to worry about OOB radiation, SPF losses and contamination from resists may be a thing of the past.

2) It looks like resist suppliers are working hard to make EUV resists ready, with several good resist papers presented. Among them was a nice review by JSR Micro (#8682-28) titled, "Novel EUV resist materials and process for 20 nm half-pitch and beyond." EUVL resists need to simultaneously meet the requirements of sensitivity, line edge roughness (LER) and resolution. One challenge that has been pointed out repeatedly is that a higher-than-expected dose is needed for best possible performance from a given resist. High absorbing resists (hybrid resists and resists with metal oxide particles) were presented as options in several papers and may allow us to adequately deal with increasing dose demand. As these resists will be more sensitive, I think that they will provide some relief from the increase in the source power requirements coming from shot noise based limitations.

3) Directed self assembly (DSA) was presented by IMEC as an aid for improving EUV resists performance (8682-10). We can expect to see increasing use of DSA in EUV resists.

4) Mask blank defects have been a challenge that has consistently proven hard to mitigate.  Lasertech (8679-17) showed data from their tool that can detect 1 nm high and 33 nm wide defects with 100% accuracy. As shown in many papers, the number of defects in mask substrates and mask blanks remains stubbornly high. However, in the last session of the conference, a paper by IBM (8679-53) delivered good news on mask defect repair for phase and amplitude by nano machining. By looking at mask defects using AIT (mask inspection tool from CXRO), they were able to model the  number of multilayers (ML) that may need to be  removed or added to the mask blank so that the Bossung curve for the resulting ML is what is expected for a defect-free ML! They presented many examples, and I believe that although this process seems laborious, it may get widely adopted along with mask blank defect reduction to address this leading challenge for EUVL.

5) As we move to higher NA, absorber thickness becomes a larger issue due to higher shadowing. One solution presented utilizes phase-shifted masks, which are a short stack of ML etched into the mask blank, and topped by thin absorber to provide destruction interference to enable thinner absorber layers. New materials choices of Ni and Ag were presented in papers as alternatives to the current set of mask absorbers.

6) As EUVL moves to the 10 nm node and below, one option for achieving increasingly smaller patterning is double patterning with EUV. Intel confirmed success for this process in their pilot line and in the last paper of the conference IMEC and AMAT demonstrated 9 nm HP dense L/S patterning using NXE3300B!

New Challenges

The conference also delivered a list of new EUVL challenges. I already mentioned the challenge of particles added to the pellicles. As EUVL is readied for smaller nodes with high NA optics, the angle of incidence on the mask is going to increase. Options to address this issue include 1) breaking the exposure field into two or four parts, 2) adding two additional mirrors to the scanners and 3) increasing mask size from the current 6 inches to 9 inches.

Winfred Kaiser of Zeiss summarized various technical options for the industry.  In his paper, he suggested "going with 6 inch masks with quarter field and 8x magnification" as the best option for 0.5 NA. However, breaking the pattern into many parts will further downgrade the throughput.  Harry Levinson of Global Foundries offered "6 x magnification with 9 Inch masks" as the best solution for 0.5 NA. He also stressed the need to continue working with 6 inch masks as long as we can. Going to a larger mask means upgrading mask infrastructure tools to handle 9 inch masks, which will be very difficult and could take a couple of years. However, this approach may involve changing only the handling part of tools, while leaving the key technical core of the tools the same. In any case, moving to 9 inch masks will be painful for mask makers and we can expect to hear more on this topic from them.

Best Papers

The following four papers seemed outstanding to me:

1) A paper by Harry Levinson titled "Considerations for high-numerical aperture EUV" (8679-41) was my first choice. He not only elegantly outlined the technical challenges, he also proposed a comprehensive set of business solutions and challenges to their implementation.

2) A paper by Luigi Scaccabarozzi  of ASML, "Investigation of EUV pellicle feasibility" (8679-3), showed how quickly this supplier has addressed a critical challenge which could have been a showstopper.

3) A paper by Shannon Hill of NIST titled, "Relationship between resist outgassing and witness sample contamination in the NXE outgas qualification using electrons and EUV" (8679-19) was an excellent technical work looking into the mechanism of resist outgassing and contamination. His group has continued to lead in the basic work of understanding the mechanism of contamination in EUV.

4) A paper that I would like to cite for its excellent presentation style was offered by Ken Goldberg of CXRO as "Commissioning a new EUV Fresnel zone plate mask-imaging microscope for lithography generations reaching 8 nm" (8679-44). His outstanding talk set the standard for how to present a complex topic and immense technical achievements in a very elegant way, and the audience was very impressed. I will recommend that SPIE post Ken’s paper on their website as a standard for SPIE authors wishing to make an excellent technical presentation.

Other Observations

– Despite moving the conference to a larger venue, there was still standing room only for key talks.

– 450 mm was not mentioned once in any paper in the EUV sessions!

– Although sources remain the biggest challenge in EUVL, discussion on this topic was limited pretty much to suppliers showing their roadmaps. I spoke to many people about the source power issue and the lack of funding for source R&D. All agreed, but acknowledged that no action by the industry has been taken yet. Part of the issue, as some mentioned, is that source R&D needs cannot be fully addressed until ASML’s acquisition of Cymer is final, as then it will be something for ASML to address.

Summary of HVM Readiness of EUVL

Hynix presented their 2009 cost of ownership (COO) calculations for various next-generation lithography (NGL) techniques. They indicated that COO for an EUVL scanner at about 35 WPH would be the same as COO for double patterning. They said the COO equation has not changed much since 2009, although I think it will change some for smaller nodes, since for them higher source power will be needed.

I expect 40 W sources in the field next year. I will be delighted if NXE 3300Bs are in the field by the end of 2014 with a source as well, but I am not sure if 80 W sources will be ready by then.  I do not think we will have 100 W sources in field before 2015. However, I do not want EUVL HVM insertion to shift from 2014 to 2015, so I can win my bet with Lithoguru Chris Mack and claim his Lotus as my own!

Bring Me the Rhinoceros

Last month, I decided to take a three-month introductory course on Zen Koans in the local Zen Monastery. (For those not familiar with Buddhism, a koan is a question without a real answer, and is aimed at getting the student to think deeply.) The first Koan, which students can study many years in a traditional Zen monastery, is called the Mu Koan. It goes like this:

A monk asked his Master ZhaoZhou, "Does a Dog have the Buddha nature, or not?"

Master ZhaoZhou replied, "Mu" (Japanese for No).

One of the central ideas in Buddhism is that all things have Buddha nature, so this answer does not make sense. A pupil is supposed to work with this Koan for a long time. There is no standard answer and the master judges each pupil’s answer differently. I had the homework of applying this Koan to whatever was happening to me during the week, and report back what I learned. As I was at the SPIE Advanced Lithography conference, I decided to rephrase the Koan as "250 W is needed for HVM adoption of EUVL and EUVL will be in HVM in the next two years. Does that mean we will have 250 W sources ready?"  Having spent over ten years in the EUVL source business, I think I will answer my own Koan with a Mu, while still acknowledging EUVL as the leading technology in the next two years. I will continue to give a dialogue on this topic in my blog in coming weeks.

I would like to leave my readers with the second Koan from my class called "Bring Me the Rhinoceros," and invite you to contemplate how it relates to the "Art and Science of Making Computer Chips."

One day, Master Yanguan called to his assistant, "Bring me the rhinoceros fan."

The assistant said, "It is broken."

Master Yanguan replied, "In that case, bring me the rhinoceros."

Second Koan used here is from a book by John Tarrant titled "Bring Me the Rhinoceros," Shambhala Press, 2012.

Dr. Vivek Bakshi blogs about EUV Lithography (EUVL) and related topics of interest. He has edited two books on EUVL and is an internationally recognized expert on EUV Source Technology and EUV Lithography. He consults, writes, teaches and organizes EUVL related workshops. WWW.euvlitho.com

I got good bit of feedback on my last blog in which I discussed the differences between physics and engineering of EUV Sources, and the implications of that difference. I was glad to see that it generated some re-evaluation of current thinking (as intended) and now would like to clarify few points.

First is the supplier commitment. One can have lots of great technical options backed by beautiful physics, but if there are no suppliers to turn ideas into commercial products, technology will go nowhere. EUV source technology will succeed as it has three large suppliers, each with current business experience in supplying light sources for scanners.  In the end, we may not have this many suppliers due to business and/or technology consolidation, but right now we do. For EUV sources for metrology, there is an even larger number of potential suppliers who are working to find a way to meet industry requirements. With this backing and competition among suppliers to outperform one another, we ought to see success.

The real question is whether scanners that can produce ~40 wafers per hour (WPH), which  I expect to be ready by 2014, will deliver cost of ownership (COO) sufficient to convince leading chip-makers to switch from 193nm based technology. The challenge is to estimate the point where the COO of EUVL will cross that of 193nm, making it more cost effective technology. Will it be at 15nm or 7nm? What product, what wafer size?  I do not have sufficient information to make this prediction right now, but I expect some acceptance of EUVL in high volume manufacturing (HVM) by the end of 2014.

Just because a technology cannot scale up in power does not mean that it will poorly serve EUVL in the process of development. Last week I gave an example of synchrotrons. They have provided low throughput printing to support development of current EUVL technology, and will continue to do so for future versions of EUVL. So let us continue that very wise investment! Supplier Energetiq has 10W source technology that has aided EUVL very well so far. Present designs may not scale up to the required brightness for mask defect metrology tools, but this supplier is looking at new physics for scaling, as they demonstrated in the last two Source Workshops in Dublin.

So it is a matter of realizing what cannot be done with present physics, and finding new ways to achieve scaling. We have seen >5% conversion efficiency and high debris mitigation techniques at low rep rates. Let us see how far these approaches can scale up. If they do not (over a reasonable period), then we need to quickly pick up another potential solution from a host of possibilities. These will become available to us if we continue to look for new physics, including development of new materials and chemistry. We can research the physics of EUVL with a very tiny fraction of what we have spent on engineering development of the technology. I still believe in the power of innovation and competition to help us move forward, but for this effort we must engage universities, national labs and independent research organizations to generate new ideas leading to new solutions. Only then will we be in a position to solve the persistent problem of low throughput in EUVL scanners.

Dr. Vivek Bakshi blogs about EUV Lithography (EUVL) and related topics of interest. He has edited two books on EUVL and is an internationally recognized expert on EUV Source Technology and EUV Lithography. He consults, writes, teaches and organizes EUVL related workshops. WWW.euvlitho.com

I am frequently asked by my consulting clients and colleagues when EUV sources will be ready to support high volume manufacturing (HVM) of semiconductors. It is a difficult question to answer, partly because readiness metrics have been a moving target, or the latest performance data is not very clear. For example, how many wafers per hour will make it cost-effective to adopt EUVL over the alternatives of triple or quadruple 193 nm immersion lithography for a given  product at a specified feature size for 300 mm or 450 mm wafers? Is the latest data in pulse mode and integrated, and for how long an operation?

Even if the targets are clear, there is still uncertainty because source progress has not increased as much as predicted  by  supplier roadmaps. Last week in a press release (see http://optics.org/news/4/1/26), ASML was quoted as saying, “40 W sources are providing good dose controls and will be used in NXE3300B to be shipped in 2013. 60 W sources have been successfully tested with no sign of performance degradation from debris.”  But can we take these numbers at face value and expect sources to be ready as promised in the supplier roadmaps?

As EUV source technology has been the main reason for the delay in EUVL for HVM, it is worthwhile spending some time  pondering why this is so and what we know. When I look at what I know about source technology status, my only data is what is shown at industry conferences by source suppliers or chip-makers. Most presentations are about achievements which have been significant, but not sufficient. Unfortunately, no one talks much about what is not working, except to say "We’ll fix the problems and here is our roadmap."

Given the many delays in HVM-ready EUVL, we should know by now that looking at roadmaps and press releases may not be the best way to predict technology readiness. Presumably, customers who own the latest EUVL scanners get confidential updates on source readiness so they have a better idea of what needs to be fixed. But these are chip- makers and not source experts, and their information may end with predictions from roadmaps which I suspect are very close to those shown in public by source suppliers. Of course, I have no clue about what additional information source customers may have, except that all of them list EUV source as the #1 problem in their public presentations.

One of the most repeated statements I hear on this topic is, “The physics is known and it is just an engineering challenge.” In other words, it is all about figuring out how quickly solutions can be engineered. I tend to disagree with this statement, and here’s why:

Let’s start by defining physics and engineering. Per Webster’s dictionary, “Physics is science dealing with the properties, changes, interactions of matter and energy,” while “Engineering is concerned with putting scientific knowledge to practical uses and planning, designing, construction or management of machinery.”

In other words, something is not physically possible if the physics is not there. Even if something is possible at low repetition rates, it does not mean that physics will support power scaling without near-impossible engineering. Figuring out physics is like seeing our target in a forest. Yes, we can see it, but can we build a freeway to it for 24 x 7 traffic? Take nuclear fusion as an example:  the physics is there, but we have yet to power a light bulb from a fusion reactor after more than 50 years of research. At least EUVL scanners are in the field and are printing wafers every day for process development. So how large is the remaining engineering challenge for EUV sources? Isn’t finding that out the real challenge in EUVL? 

This assertion that "only engineering challenges remain for source technology” is usually backed by low to very low repeatable data, e.g.,: “Yes, we have 70 W and we got this for 10 s in standalone mode at 10% duty cycle, but it means we know the physics and all we have to do is to engineer this result into a 24 x7 product that can be integrated into a scanner.”

You may remember that  Xe discharge produced plasma (DPP) sources worked very well but never went beyond 5 W, once we finally figured out that collectable power would never exceed 5 W due to etendue limits (i.e., one can collect light only from a very small part of the plasma). In addition, it is not possible to mitigate all the heat that higher power produces in Xe DPP sources. So we had to use different physics by changing the fuel to tin, which was easier to engineer for power scaling using DPP and eventually source suppliers have put more focus on tin based laser produced plasma (LPP). But LPP sources utilize different physics than DPP to heat the plasma, so we had to use slightly different physics  to create new systems  of LPP Sn. These systems were initially based on 1 micron (mm) lasers and today we are using 10 mm lasers, according to results from lab physics experiments. Now the focus is on other aspects of Sn LPP to achieve HVM targets, including 1) changing of the delivery system from droplet to mist targets, and 2) pulse shaping and pre-pulsing to increase conversion efficiency. With each new twist, slightly different physics are added to the mix.  So I am not sure if Sn LPP will scale up without our introducing new designs based on somewhat different physics, such as going to ion beam targets or something else.

So the question comes down to this: do we have a physics solution that we can engineer? If so, how do we assess that solution? Surprisingly, the size of the machine is not necessarily an indication – we cannot say DPP is superior to LPP because it is more compact. Synchrotrons, which are rather large machines, very reliably generate EUV photons on 24×7 time scale. In fact, their contribution to EUVL development has been so immense, I do not know where we would be without them. In addition to their size, coherence and cost have been raised as issues for these very reliable sources of EUV photons. Can we reduce the size/cost to make synchrotrons a potential source for fabs? Have we looked at them seriously enough in the light of current source technology, recent developments in technology and our future needs? Not really, in my opinion, and we need to do this for both plasma and non-plasma based sources.

In short, we have not quite figured out the physics for EUV sources that can be quickly scaled up in power and engineered to make products. Some will disagree with me that this is not so for 100 W sources,  but I think I am probably right  for 250 W or 1000 W EUV sources – which will be needed as we go to higher NA scanners, smaller printed features  and 450 mm wafers.