Category Archives: Materials and Equipment

(September 14, 2010) — Brion Technologies, a division of ASML, debuted the Tachyon NXE software to optimize predictive modeling for ASML Extreme Ultraviolet (EUV) scanners. EUV scanners enable smaller, faster, cheaper and more energy-efficient semiconductors. The accurate EUV modeling in Tachyon NXE will reduce development time and cost to produce chips on EUV systems, according to the company.

The Tachyon NXE software package integrates with existing Tachyon products to enable EUV lithography process simulation. In developing Tachyon NXE, Brion has incorporated TWINSCAN NXE:3100 scanner characteristics, models, and data to accurately describe the optical performance of the system. By simulating the behavior of the new scanner in software, this Tachyon NXE model can efficiently predict and correct NXE-specific effects before the start of chip production, helping to decrease EUV mask re-spins and shorten the learning cycles during final mask development.  

The Optical Proximity Correction (Tachyon OPC+) and Lithography Manufacturability Check (Tachyon LMC) applications from Brion can now incorporate the new software model of ASML’s EUV pre-production scanners, 6 of which will ship before mid-2011. These applications have been optimized for accuracy, file size and run-time as uniquely required by EUV. In multiple DRAM test cases, Brion has demonstrated the capability to perform full field (~8 cm2) EUV mask data correction in less than 8 hours on a single Tachyon system.

Jim Koonmen, general manager of Brion, spoke with senior technical editor Debra Vogler about the industry transition to EUV and the software’s role. Listen to the podcast: Download or Play Now

ASML and Brion are committed to providing widespread access to the accurate NXE:3100 and NXE:3300 scanner models and to continuously improve the entire lithographic process for chipmakers. Brion will continue to invest in Tachyon NXE to continuously improve its capabilities, while developing a separate product that will enable customer access to NXE-specific effects within a broad range of simulation tools. This second product will be available soon.

Computational lithography is the use of computer modeling to predict, correct, optimize and verify imaging performance of the lithography process over a range of patterns, processes, and system conditions. Read an article on computational lithography demands here.

EUV is a lithographic method using a source wavelength 15 times shorter than current lithography systems, enabling semiconductor scaling to resolutions of 10nm and smaller. Read a recent article about EUV lithography here.

Brion Technologies is a division of ASML (lithography system provider) focused on computational lithography for integrated circuits. For more information: www.brion.com or www.asml.com

Follow Solid State Technology on Twitter.com via editors Pete Singer, twitter.com/PetesTweetsPW and Debra Vogler, twitter.com/dvogler_PV_semi. Or join our Facebook group

September 13, 2010 – For all the good cheer around semiconductor capex in 2010, some are suggesting the party’s almost over.

Gartner’s just-released forecast update pegs semiconductor equipment spending more than doubling (122%) this year — but slowing to 10% growth in 2011, and 7.4% in 2012.

But that might not be low enough. Barclays’ CJ Muse is reducing his capex estimate for 2011 to -10% (vs. +20%), with wafer-fab equipment spending slipping to ~$25B. Reason behind his new "subdued" outlook: "weakening demand outlook across the entire technology food chain," and softening trends particularly in foundry and DRAM, he writes in a recent research note. Muse says we’ve seen this pattern before: the 2004-2006 cycle, in which a strong year (60%+ in 2004) was followed by a period of digestion (flat in 2005), and then another strong year (19% in 2006).

Using "simple math," Muse calculates 3Q10 order runrates for WFE spending (US frontend equipment) of $26B-0$34B, which means $25B in total WFE spending in 2011 means frontend orders will soon reach a peak. "Orders will begin to rollover in the months of 4Q10 and potentially into 1Q11," he writes.

One thing Muse emphasizes as a big takeaway from what he calls "this demand-abbreviated cycle" is the small amount of capacity that has been added — only 0.3% in 1H10, citing SICAS statistics, and actually declining 11% since exiting 2009. Also by SICAS stats, leading-edge capacity (<60nm) added only ~500k wspm. So, no big overhang of capacity, shrinks are getting more difficult (more complicated tools for critical layers, e.g. immersion litho) means capital intensity is still growing — assuming there is a macroeconomic recovery into and through 2011, "we think this speaks to 2012 being a better year than 2011 for capex spending," Muse says. Key drivers to watch, NAND strength, DRAM demand elasticity as prices fall, and continued strong demand for smartphones and iPads, which drives business at foundries.

In general, Muse sees four trends supporting 2011:

— Foundries are gearing up. There’s an "arms race" among foundries, Muse says, as GlobalFoundries and Samsung enter the fray to battle TSMC et al.

— NAND demand holding up. There are three or four big projects on the boards that will be ramping up investments.

— Korea rising. As the Koreans continue to rake in profits, they are spending on DRAM — more on technology (shrinks) than on new capacity.

— Deep pockets in Taiwan. Nanya/Inotera will spend, too, helped by conglomerate Formosa Plastics.

Narrowing down 2011 capex trends by segment:

— Logic, -5% vs. 2010. Led by Intel’s countercyclical investment cycle and 22nm ramp, but "roughly flat spending elsewhere." There looks to be less reuse at Intel, at least for lithography (with ASML upending some Nikon tools). Any negative impact could be from iPads eating netbook sales.

Capex: Logic, in US $M. (Source: Barclays Capital)

— Foundry, -20%+ vs. 2010. Top foundries should see utilization rates become seasonally weak in 4Q10-1Q11. TSMC spending down -30% related to fabless pullbacks (e.g. Nvidia), though the foundry should increase yields during the timeframe. Muse notes, though, that TSMC CEO Morris Chang likely will switch on capex "at the first sign of macro clouds lifting." For UMC, spending should reduce as Xilinx shifts sourcing to Samsung and TSMC. On the other hand, Samsung LSI should increase its spending, and GlobalFoundries might only slip a little.

Capex: Foundry, in US $M. (Source: Barclays Capital)

— DRAM, -15% vs. 2010. Seasonal weakness through 1Q11 as DRAM pricing rolls over, but "soft landings" for Tier 1 suppliers Samsung, Hynix, and Micron, the first two of whom should achieve or break $1/GB for DDR3 as they ramp their 4Xnm process technologies. Micron will reduce its DRAM capex (utilizing Nanya/Inotera for production), but look for Elpida/Rexchip/Powerchip to keep capex similar to 2010 levels to stay competitive. Samsung will continue to spend as Tier 2 competitors struggle for funding.

Capex: DRAM, in US $M. (Source: Barclays Capital)

— NAND flash, +19% vs. 2010. Here’s where the money seems to be for 2011: NAND pricing is rolling over, Apple always needs more memory, and there are "well-financed projects" from Samsung (Line 16, $2.5B WFE), Toshiba/Sandisk ($2.0B WFE), and IM Flash ($1.5B WFE).

Capex: NAND flash memory, in US $M. (Source: Barclays Capital)

(September 10, 2010) — Speaking at the MEPTEC Forecast Luncheon (Santa Clara, CA 9/8/10), Gartner VP of semiconductor manufacturing research, Jim Walker, noted that equipment spending is mostly on technology, foundry and memory. And for the first time, 2 SATS companies (ASE and SPIL) joined the top 20 capital spenders in 2010. He also predicts solid growth for advanced packaging tooling with memory ATE and copper wire bonders being the top performers. Walker told attendees that the conversion to copper wire from gold is a wise move for the industry — with even some high-end packaging joining the conversion.

Podcast: Download or Play Now

Overall, Gartner sees a 31.5% semiconductor growth in 2010, with PCs, cell phones, and LEDs being the key drivers. (Also listen to an interview with Bob Johnson, Gartner, here)

Hear additional comments on the forecast and the overall economic outlook in the podcast interview with Walker, including his thoughts on how the memory cycle will impact capex.

(September 7, 2010) — Since Intel’s Bohr published his seminal paper on interconnect scaling in 1995 the IC community has been searching for a manufacturable low-k dielectric which could scale to below K = 2.0.

Since 1997, the ITRS roadmap requirements for low-k have been continually relaxed due to the difficulty in achieving an electrically reliable, manufacturable process with either spin-on organic or inorganic dielectrics or C-doped CVD materials. Chemical companies, equipment companies, and the IDMs and foundries have spent hundreds of millions of dollars trying to find this “holy grail”. Many trade press and technical articles over the last decade have documented the issues such as CTE and fracture toughness that have arose when trying to integrate highly porous low-k dielectrics.

The most recent ITRS roadmap (2009) indicates that low-k introduction to manufacturing has followed the following timeline.

 

90nm 

65nm 

45nm

k =

3.0

3.0

2.7-2.8

Now, as dense carbon-doped oxides (k = 2.8) attempt to evolve into porous carbon-doped oxides with k < 2.5 (ULK ) there have been widely reported problems in manufacture, test, assembly, and packaging of these fragile chips. Most fabs and foundries have reported that they are struggling to see their way to a manufacturable k < 2.5 solution. In fact the 2009 ITRS roadmap points to a “red brick wall” when attempting to go past kef f= 2.5.

SBA Materials

Several years ago, SBA Materials CTO Mark Philips and his team started developing “Block Polymer Templated Inorganic Oxides” (USP 6,592,764) which self-assemble into materials with controlled structure and physical properties. These spin-on dielectrics (SBAM uLK) combine an amphiphilic block copolymer (structure-directing template) with silicon alkoxide esters. The block copolymer and silicate esters are self-assembled and the silicon compounds are polymerized to form mesoscopically structured silicon composites. The template is then removed (thermal, UV and/or E-Beam) leaving a porous alkylated silicon dioxide low-k dielectric.

Properties of three grades of the new dielectrics are shown in the table below.

 

 

Units

uLK – 120

uLK – 122

uLK – 124
Dielectric constant  

2.0

2.2

2.4
Leakage

A/cm2

10-11

10-11

10-11
Breakdown voltage

MV/cm

>5

>5

>5
Modulus

GPa

6.0

7.3

8.6
Hardness

GPa

0.8

1.0

1.2
Fracture characteristic  

Ductile

Ductile

Ductile

Microindent photos of uLK 124 show a clean ductile indent vs many of the low-k materials currently available which show brittle fracture during such testing.

SBA reports that their uLK materials can be integrated into existing fab lines using equipment and process flows already in place. While spin-on materials would be a change for IC fabs that currently use CVD ILD dielectrics, CTO Phillips insists that this has not been a problem with current customers since spin coating is a well-known technique for materials deposition.

SBA has agreements in place with Asian chemical producers to manufacture, bottle, and supply under their label, to ensure quantity and IC grade quality that a start-up would not be trusted to deliver, reveals SBA CEO Bill Cook. While SBA reports that their uLK materials “…are in advanced qualification at 3 of the top 10 IC fabs in the world,” they are not ready to reveal exactly who yet, because of secrecy agreements that are in place. It is thought that all three of the lead customers are in Asia.

SBA is currently working with IMEC and will be jointly presenting their first SBAM uLK processing paper this October at the Advanced Metals Conference in Albany, NY.

Dr. Phil Garrou is a contributing editor for Solid State Technology and Advanced Packaging on www.ElectroIQ.com. Read his blog, Insights from the Leading Edge.

Follow Solid State Technology on Twitter.com via editors Pete Singer, twitter.com/PetesTweetsPW and Debra Vogler, twitter.com/dvogler_PV_semi. Or join our Facebook group

(September 7, 2010) — Nordson DAGE, a subsidiary of Nordson Corporation (NASDAQ: NDSN) and provider of bond testing technology, introduced Paragon intelligent bond testing software for semiconductor packaging. Paragon provides flexible analysis and high accuracy and repeatability of test data by monitoring of all aspects of the Nordson DAGE bondtester.

Highly intuitive with a configurable interface, Paragon software offers easily accessible test set-up parameters, a check list enabling a quick start; advanced features (including semi-automatic test routines), a unique database search engine wizard, and reporting. Data presentation is enhanced by extensive charting functionality, allowing several graphs to be displayed at once, also including the images from the camera systems with the results. 

Follow Advanced Packaging on Twitter.com by clicking www.twitter.com/advpackaging. Or join our Facebook group

Paragon software monitors life tests on the Nordson DAGE bond test tool, load cartridge and calibration jig, and health checks. Automatic alerts can prevent downtime and Paragon includes advanced failure mode grading.

Nordson DAGE is a unit of the Nordson Corporation and manufactures and supports a complete range digital X-ray inspection systems and bond test equipment for the printed circuit board assembly and semiconductor industries.  For more information, visit www.nordsondage.com.

September 3, 2010 – Researchers at Rice U. say they’ve figured out that new switching memory they built with electrically manipulated 10nm graphite strips doesn’t actually need the graphite — good ol’ reliable silicon oxide will do just fine.

Last year a team led by Rice prof. James Tour showed that electrical current could break and reconnect graphite strips, creating a memory bit.

Now, grad student Jun Yao shows in a Nano Letters paper that the same thing can be achieved with silicon oxide between semiconducting sheets of polycrystalline silicon (as top/bottom electrodes); applying a charge forms a chain of nanosized silicon crystals — as small as 5nm — which can be repeatedly broken and reconnected by varying the voltage. As a proof of concept, he cut a carbon nanotube to localize the switching site, sliced out a thin piece of silicon oxide by focused ion beam, and identified a nanoscale silicon pathway under a transmission electron microscope.

What’s important here? Silicon oxide switches or memory locations require only two terminals, not three (flash memory) because the device doesn’t have to hold a charge. It also can be stacked in 3D arrays, which is the direction memory is going, and would be compatible with conventional CMOS manufacturing technology. And while there are questions about what to do with conventional memory below 20nm, "our technique is perfectly suited for sub-10nm circuits," Tour says in a statement. These SiOx circuits offer similar specs as the original graphite device: high on-off ratios, "excellent" endurance, and <100ns switching. They’re also radiation-resistant (i.e. suitable for defense/aerospace radiation-hardened applications).

From the paper abstract:

Through cross-sectional transmission electron microscopy, we determine that the switching takes place through the voltage-driven formation and modification of silicon (Si) nanocrystals (NCs) embedded in the SiOx matrix, with SiOx itself also serving as the source of the formation of this Si pathway. The small sizes of the Si NCs (d ~ 5nm) suggest that scaling to ultrasmall domains could be feasible. Meanwhile, the switch also shows robust nonvolatile properties, high ON/OFF ratios (>105), fast switching (sub-100ns), and good endurance (104 write-erase cycles).

Austin design firm Privatran is bench-testing a silicon-oxide chip with 1000 memory elements, in work supported by a number of federal groups (NSF, plus the science arms of the Army, Air Force, and Navy). And a Rice spinoff company, NuPGA, is using vertical silicon oxide embedded in vias for rewritable gate array designs.

 

(September 3, 2010 – Marketwire) — Palomar Technologies introduced the fully automated 3800 Ultra Flexible Click to EnlargeDie Bonder, created for flexibility, high accuracy and precision.

The 3800 is based on Palomar’s three-generation Model 3500 Die Bonder. The 3.5 um repeatability 3 sigma and 2600 UPH over a 907.1 x 508mm work area enables its user to achieve high accuracy, precision and speed with flexibility in a wide variety of applications. Mutiple options include pulse heat and steady state stages for eutectic die attach applications.

Common applications include eutectic die attach, laser diode packaging and high-power LED packaging. Complex packages, often found in military, optoelectronic and medical devices industries, are well suited for the 3800. The 3800 is designed to eliminate additional bonders in the packaging facility.

Palomar Technologies provides high-precision wire bonders, gold wire bonders, die bonders and automated component placement systems. Find Palomar on the web at www.palomartechnologies.com. Visit Palomar’s blog at www.solutions.palomartechnologies.com.

Follow Advanced Packaging on Twitter.com by clicking www.twitter.com/advpackaging. Or join our Facebook group

(September 3, 2010) — SEMI Europe Grenoble Office announced that 10 semiconductor equipment and product providers will present their latest technologies at SEMICON Taiwan, September 8-10, in the French Pavilion.

The pavilion is organized by UBI France in close collaboration with SEMI Europe Grenoble Office, as well as the worldwide competitive cluster MINALOGIC, which is devoted to IC design and fabrication and associated embedded software. Most of the exhibiting companies and organizations have co-development programs on 3D applications with CEA-Leti. The National Research Institute is co-exhibiting at SEMICON Taiwan to help them promote their products and services.

French exhibitors include:

CEA-Leti
CEA is a French research and technology public organization, with activities in four main areas: energy, information technologies, healthcare technologies and defense and security. Within CEA, the Laboratory for Electronics & Information Technology (CEA-Leti) works with companies to increase their competitiveness through technological innovation and transfers. CEA-Leti is focused on micro- and nanotechnologies and their applications, from wireless devices and systems, to biology and healthcare or photonics. Nanoelectronics and microsystems (MEMS) are at the core of its activities. As a major player in MINATEC campus, CEA-Leti operates 8,000-m² state-of-the-art clean rooms, on 24/7 mode, on 200mm and 300mm wafer standards. With 1,200 employees, CEA-Leti trains more than 150 Ph.D. students and hosts 200 assignees from partner companies. Strongly committed to the creation of value for the industry, CEA-Leti puts a strong emphasis on intellectual property and owns more than 1,500 patent families. www.leti.fr. Get all the latest research information from CEA-Leti in these interviews with SST senior technical editor Debra Vogler: Research updates on EUV, mask, cleaning, etc from Leti

FOGALE nanotech
FOGALE nanotech, a globally recognized reference in the field of high accuracy dimensional metrology, is introducing MEMSCAN, the first inspection and metrology solution fully dedicated to MEMS manufacturing. Developed in partnership with MEMS manufacturers, MEMSCAN fits perfectly with MEMS manufacturing requirements for surface micromachining and wafer-level packaging process control. Both metrology and IR inspection are performed in one shot with one tool. www.fogale.fr/~fogaleco/pages/home.php Fogale launched a North American initiative in 2007.

IBS
IBS recently introduced PULSION, the next-generation of plasma immersion ion implanter (PIII). Its unique polarization mode and pulsed-plasma configuration, using dual region chamber (CR) technology, delivers process stability, ultra-low energy and high throughput for advanced memory and logic applications. These applications include ultra-shallow junctions, without energy contamination; thin dielectric modification, nano- precipitates synthesis, hydrogen implantation, trench doping or conformal doping, and solar cells. IBS is partnering with Axcelis to deliver world-class support for PULSION. www.ion-beam-services.com/

LCP’S Consultants
LCP’S Consultants is a company created in 1996 to support SMEs, large enterprises and other organizations in establishing and following up on R&D projects. They concentrate on microelectronics, and micro- and nanotechnologies both for manufacturing and applications.

Presto Engineering
Presto helps IDMs and fabless customers improve new device predictability and speed to market by complementing their internal resources with comprehensive chip test and analysis. Supported by unique technical skills and extensive industry experience, Presto’s product-engineering services include RF and 3D integration and state-of-the-art ATE, reliability testing, failure analysis and fault isolation. www.presto-eng.com. Presto recently partnered with WIN to offer GaAs testing services.

Riber
Riber develops and manufactures molecular beam epitaxy (MBE) systems and evaporation sources and cells essential for manufacturing compound semiconductor materials used in numerous industrial, scientific and consumer applications, including new information technologies, OLED screens and new-generation solar cells. The company’s MPVD 300 offers all the benefits of the molecular beam deposition technology: atomic control, abrupt interfaces and low thermal budget for silicon-based novel devices. MPVD 300 also allows an innovative solution for introducing new materials and developing new structures to further improve CMOS-based Si devices. www.riber.com/ Riber has partnered with researchers at IMEC on Ge and III-V semiconductor work.

SET
Smart Equipment Technology is a world-leading supplier of high-accuracy die-to-die, die-to-wafer bonding and nanoimprint lithography (NIL) solutions. Its FC300 High Force Device Bonder is a new generation of high-accuracy and high-force system for populating wafers up to 300 mm. The FC300 features automated handling of chips and substrates up to 100mm from waffle packs, plus a robotic option that enables chip picking from diced wafers and automated handling of larger substrates. SET has developed a substrate chuck and a bond head with localized confinement that operates safely with reducing gases such as forming gas or formic acid vapor. This configuration has been successfully implemented on SET bonder models FC150 and FC300, especially in the case of chip-to wafer bonding applications. www.set-sas.fr/en/index.xml Smart Equipment Technology has collaborated with IMEC on 3D packaging

Satin Technologies

Follow Solid State Technology on Twitter.com via editors Pete Singer, twitter.com/PetesTweetsPW and Debra Vogler, twitter.com/dvogler_PV_semi. Or join our Facebook group

Formerly known as Satin IP Technologies, Satin Technologies delivers software solutions for fact-based, design-quality monitoring and closure. Working within customers’ design flows, the company’s VIP Lane® turns customers’ design practices (for IP blocks, SoCs, embedded systems) into a robust and reliable set of quality criteria and metrics. These customer-based parameters are used to create automated, sharable dashboards and quality compliance reports. By providing an alternative to manually filled, time-consuming checklists and documents, VIP Lane delivers effective flow integration and on-the-fly quality monitoring at no overhead to design teams. www.satin-tech.com

FantastIC Sourcing
FantastIC Sourcing is a distributor and sourcing specialist of electronic components multi- brands focused on quality, cost efficiency and rapidity. Our team has provided service and expertise for more than a decade to OEMs, contract manufacturers, and industry majors around the world, as well as dynamic domestic actors, producers of consumer goods, wireless, telecommunication, automotive, robotics, computer, aerospace and medical assembled electronic systems. Our mission is to offer to our customer the best quality, service and products in the shortest lead time to prevent supply chain disruption. www.fantast-ic.com.

UBIFRANCE
UBIFRANCE, the French agency for international business development, comes under the aegis of France’s Ministry for the Economy, Industry & Employment. UBIFRANCE lies at the heart of France’s public-sector export support framework. With 64 Trade Commissions in 44 countries, UBIFRANCE offers a comprehensive range of products and services aimed at accompanying French-based companies in their development on export markets. www.ubifrance.com/

SEMI Europe Grenoble Office is the new association merging JEMI France and SEMI. Learn more at www.semi.org/eu

Global competitive cluster Minalogic fosters research-led innovation in intelligent miniaturized products and solutions for industry. For more information, visit www.minalogic.org

(September 1, 2010 – BUSINESS WIRE) — At the inaugural Global Technology Conference, GLOBALFOUNDRIES showcased its upcoming open-access 28nm Analog/Mixed-Signal (AMS) production design flow development kit. The company is making the flow available to customers as a platform to build upon proven foundry methodologies and enable successful design. GLOBALFOUNDRIES has teamed with Cadence Design Systems to deliver this AMS production design flow.

“Collaboration and openness have never been more essential to enabling innovation at advanced technology nodes,” said Richard Trihy, director of design methodology at GLOBALFOUNDRIES. “We are working closely with our ecosystem partners to deliver optimized design solutions. Customers can build on the leading-edge 28nm production design flow platform we’ve developed with Cadence to differentiate their designs and product offerings.” 

Follow Solid State Technology on Twitter.com via editors Pete Singer, twitter.com/PetesTweetsPW and Debra Vogler, twitter.com/dvogler_PV_semi. Or join our Facebook group

The AMS flow is designed to emphasize the advanced features of GLOBALFOUNDRIES’ 28nm Gate First High-k Metal Gate (HKMG) technology. The flow includes silicon-driven guidelines and recommendations for better manufacturability. Customers will have access to IP, libraries, reference kits and foundry collateral, which will allow them to recreate the design and flow to meet their individual design specifications. GLOBALFOUNDRIES also will be the first in the industry to support a flow with DRC+, GLOBALFOUNDRIES’ silicon-validated solution that goes beyond standard Design Rule Checking (DRC) and uses two-dimensional shape-based pattern-matching to enable a 100-fold speed improvement in identifying complex semiconductor manufacturing issues without sacrificing accuracy.

GLOBALFOUNDRIES has joined with Cadence to deliver the major elements of the AMS production design flow in Q3 2010, with all of the flow steps supported by the GLOBALFOUNDRIES PDK. The reference flow contains PCells that enable critical advanced features within Cadence Virtuoso custom design tools. The complete production-level AMS flow is expected to be released to customers in Q4 2010, with silicon validation scheduled for early 2011.

The flow encompasses analog block design and mixed signal design, demonstrating mixed analog and digital design with GLOBALFOUNDRIES PDKs and partner standard cell libraries. All aspects of the design are covered in the reference flow including managing parasitic concerns, rapid circuit layout prototyping, analog layout guidelines and routing, simulation (e.g., choice of corners, Monte Carlo), inductor synthesis, metal fill and EM/IR analysis.

The design flow is also augmented with whitepapers and collateral on common challenges and GLOBALFOUNDRIES-recommended solutions. In addition, the flow incorporates top-level physical signoff steps for manufacturing using GLOBALFOUNDRIES 28nm requirements for DRC, lithography simulation and CMP.

GLOBALFOUNDRIES is a full-service semiconductor foundry with global manufacturing. For more information on GLOBALFOUNDRIES, visit http://www.globalfoundries.com

Solid-state, fiber-based, and ultrafast lasers continue to make inroads in microelectronics processing applications, specifically for silicon wafer dicing in the semiconductor industry and in a variety of laser-based cutting and texturizing applications in the photovoltaics industry.

This article is republished with permission from Laser Focus World, OptoIQ.com

While most of these laser-based cutting methods rely on linear movement of the laser beam along a substrate, Electro Scientific Industries (ESI; Portland, OR) has developed a production-ready system that incorporates its new laser-based "zero-overlap" technique for dicing ultrathin (less than 50 μm thick) silicon wafers. By keeping pulse energies and repetition rates high, yet separating the pulses spatially along the scribe line, ESI says its turnkey system improves throughput, yield, and die-break strength of ultrathin wafers compared to linear laser-based dicing methods or conventional mechanical sawing methods.

A laser-based "zero-overlap" technique spatially separates high-energy laser pulses for more effective material removal (a). The laser parameters can be adjusted to selectively optimize material-removal rates for different layers. A dry etch removes what little heat-affected zone remains after laser processing (b). (Courtesy of Electro Scientific Industries)

Ultrathin wafer challenges

The unstoppable progression of Moore’s law is driving the semiconductor industry toward 3D integration and such advanced packaging architectures as stacked memory and logic, as well as through-silicon-via (TSV) interconnects. As wafers move to thinner form factors, mechanical wafer-dicing techniques fall short due to cracking, chipping, and other yield and quality issues. The ESI 9900 enables full-cut dicing of ultrathin wafers and scribing logic or system-on-chip (SoC) wafers on die-attach films (DAFs) in one integrated system. Because these wafers often have delicate, brittle, low-κ dielectric materials on the topmost layers of the wafer, cutting through these layers without damage is critical.

The ‘zero-overlap’ technique

The 9900 zero-overlap technique uses a galvanometer-based positioning system to rapidly distribute the thermal energy from a 355 nm commercially available UV laser (with approximate 8 μm spot size) to spatially separated points along the desired scribe line of a wafer. Pulsing at around 240 kHz, the laser energy is delivered in multiple passes in spatially separate pulses that avoid the debris, heat buildup, and plume interactions of linear laser-based scribing methods. The spatial separation allows the use of higher laser-fluence values for higher wafer-cutting speeds (a few meters per second) than would be possible using linear movement of the laser beam. In addition, the laser pattern can be selectively optimized to control material removal rates for different semiconductor layers (see figure).

"The system singulates the top device layer, through the silicon, and then through the DAF with robotic wafer handling, dry etch, and cleaning steps in one fully automated process," says Matthew Knowles, product marketing manager at ESI.

Even though ESI has shown that this technique minimizes the heat-affected zone (HAZ) of the substrate being processed, they admit that any laser-based process is a thermal process and some HAZ exists. To maximize die strength and minimize kerf width of the cut, the zero-overlap process is followed by a conventional dry etch. Currently, ESI can produce clean cuts with a 20 μm kerf width after the laser cut and etch process. The 9900 also has software that includes customer-specific recipes of laser dicing parameters unique to the materials being processed.

"We are currently working with customers to optimize the laser and etch processes and are encouraged by the high die break strengths and high production yields we are seeing," says David Lord, product manager in ESI’s Semiconductor Products Division. "Our goal is to minimize cost of ownership for the customer and enable our customers to fully adopt 3D integration into their high-volume manufacturing environments."–Gail Overton

More Laser Focus World Current Issue Articles
More Laser Focus World Archives Issue Articles