by Debra Vogler, senior technical editor, SST/AP

March 2, 2010 – Mentor Graphics Corp. unveiled its FloTHERM IC productivity tool targeting the semiconductor industry for thermal characterization and design at the recent SEMI-THERM Symposium (Santa Clara, CA USA). The new tool is a Web-based platform that automates the design tasks associated with full-spectrum thermal characterization and validation.

Ian Clark, product marketing manager at Mentor Graphics, told SST that the metrics in the tool are generated by the software automatically placing the package of interest in a virtual representation of the standard JEDEC test environments and performing a calculation using the tool’s solver. In one example (Figure 1), he noted that the metric of interest is the junction-to-moving air thermal resistance (Θjma). The tool output shows the surface temperatures of the test board and package in the free post-processing viewer, FloVIZ. "For this metric, the appropriate JEDEC test environment is the moving air (forced convection) configuration," explained Clark.

Figure 1. Surface temperature distribution on the test board and package for the moving air (forced convection) test environment as shown in the FloVIZ viewer.

In another example, Clark explained, the metric of interest is the junction-to-ambient thermal resistance (Θja). Figure 2 shows the surface temperatures of the test board and package and the flow field. "For this metric, the appropriate JEDEC test environment is the still air (natural convection) configuration," said Clark.

Figure 2. Surface temperature distribution on the test board and package and the flow field for the still air (natural convection) test environment as shown in the FloVIZ viewer.

According to the company, a typical semiconductor thermal team spends ~60% of its time on standard package thermal characterization and design, and the remaining time for customer-specific characterizations. The FloTHERM IC tool dramatically reduces the time spent on thermal characterization and design by providing an automated process that includes pre-verified thermal models to reduce the risk of modelling errors. Clark also noted that the tool can achieve reductions of up to 25% in the time usually needed for customer-specific characterizations.

The FloTHERM IC tool is based on Mentor Graphics technologies including FloTHERM computational fluid dynamics (CFD) software, used to simulate airflow, temperature and heat transfer in electronic systems, and the FloTHERM PACK Smart Parts modeling tool.

by Robin Bornoff, Mentor Graphics Corp.

February 16, 2010 – Most people imagine integrated circuit designers spending their days laying out unimaginably small, complex features on silicon. But the IC design process spans many disciplines, including the job of packaging those powerful but delicate silicon chips. IC packages must deliver signals to and from the chip inside, but equally important, they must carry potentially destructive heat away from the active component.

Package thermal design and evaluation are both labor- and time-intensive tasks when done the traditional way. This involves special standardized fixturing, a "thermal die," a host of measurement tools, and up to six weeks of preparation and testing.

But some form of testing is indispensable. Ever-improving processes and tools allow IC designers to pack more functionality into smaller chips with each passing year. One by-product of these steady improvements is the greater concentration of heat within devices that execute millions of operations per second, every second. IC design teams must find ways to minimize heat generation and buildup, and thermal testing is part of the process.

Producers have learned to expect up to 20% of initial thermal designs to fall short of specified targets and fail their first evaluation, requiring additional test iterations. Product planners usually build a cushion into their development timelines, but even liberal padding won’t salvage a schedule that suffers the delays that result from too many cycles of redesign and evaluation.

Small wonder, then, that IC manufacturers are constantly exploring better solutions to the costly problem of package evaluation and testing.

A methodology in transition

Traditionally, package design engineers have followed a complex but universally-accepted physical test regime that evaluates the thermal performance of new packaging configurations within a standard environment defined by the JEDEC Solid State Technology Association.

The tests are performed by mounting the packaged part on a JEDEC-standard board and testing the assembly in natural-convection and forced-convection environments. A thermal die equipped with integrated forward-biased diodes measures the junction temperature inside the packaged part. The cycle time for collecting each set of data ranges from 4 to 6 weeks. This long time span encompasses the re-design and assembly of the package, plus the actual testing steps.

While the results usually correlate well with the device’s behavior in the real world, physical testing has a glaring weakness: it isn’t possible to evaluate the thermal performance of a new product or package until the first prototypes arrive. This occurs relatively late in the design process, when setbacks are least affordable. Fortunately, most (80% to 90%) of new designs pass satisfactorily. But first-round failures face a schedule delay of up to six weeks.

Business calculations anticipate a certain proportion of failures. Once a device has failed, there is a crash effort to modify and re-test the design. Obviously this process, with its multi-week delays, is not one that can be repeated again and again while engineers fine-tune the design. After a device has used up its allotment of risk, developers must rely on proven, high-confidence measures to correct any remaining problems. It is not an atmosphere conducive to experimentation or innovation. There simply isn’t enough time to try alternative approaches and optimize thermal performance.

But the intense pressures in today’s product-development environment have fostered a demand for both short cycles and low risk. No longer is it practical to rush package designs to completion in the expectation that "most" will meet their thermal goals. Increasingly, IC and package designers are turning to thermal modeling tools to perform complex tests in the virtual realm and deliver predictions without prototypes — at least not in their tangible hardware form. Proposed designs can be validated early and often, minimizing the risk of prototype test failure.

Thermal modeling and virtual packages

Modern thermal modeling solutions are based on a discipline known as computational fluid dynamics (CFD). It is a field well known and appreciated among mechanical designers who must consider fluid flows — whether the fluid is water, atomized fuel, or heated air — in their designs. Forecasting fluid behaviors for even the simplest systems with ordinary manual calculations is almost impossibly complex. CFD comes to the rescue by accepting inputs about a particular flow environment and processing millions of numerical equations to develop a composite result that accurately predicts fluid flow.

Until recently, CFD was the province of trained specialists who could design optimized calculating grids called meshes, define cavities and boundaries, and generally minister to a set of rarified input requirements. Today, that situation is changing and CFD solutions for flow applications including high-temperature thermal analysis are within the reach of engineering and IC package design departments throughout the industry. (IDT, for example, recently used CFD thermal analysis in a packaging decision for a recent product launch.)

Late-breaking CFD advancements are emerging to further assist IC package designers. Web-based solutions are now available to generate thermal models of IC components, test boards, and associated elements. These sophisticated generators produce reliable and accurate "virtual" packages in just a fraction of the time required when using traditional methods. The models are tailor-made for CFD analysis.

Today, two formerly daunting and time-consuming tasks — first, model creation and then CFD analysis — can be handled efficiently by accessible software-based tools. The packaging engineer is liberated from the constraints of physical testing and can freely experiment with new ideas and design variants without risking an entire project’s success.

A tour of a simulation procedure

An accurate CFD analysis relies on the accuracy of the model from which it works. An engineer begins his or her thermal evaluation not by running a CFD application, but by entering IC package parameters into the web-based model development tool. These characteristics include package type and size, lead or ball count, substrate cross-section, die size, and more. The model generator sits atop a database that supports a host of package types and variants. It can produce any of three different model types:

– The detailed model. This model describes package features in full. This method’s thermal performance calculations are the most accurate of all the approaches but the process requires significantly more computing resources than the other alternatives.

– The two-resistor compact model. This model is generated using a computational implementation of the JEDEC standards for the Junction-to-Case and Junction-to-Board resistances. The burden on computing resources is very small but the worst-case error in junction temperature predictions can approach 30% and vary greatly between differing package types.

– The DELPHI compact model. This is a significant improvement over two-resistor models. In many applications, the model will predict the junction temperature to an accuracy of 10% while greatly reducing simulation time. DELPHI compact modeling standards are currently being adopted by JEDEC.

The thermal resistor method of component representation discloses no proprietary intellectual property regarding the design or construction of the package. Therefore, the model can be freely delivered to system integrators, who can further verify that the thermal performance of the package within their actual product is compliant.

Once a thermal model of the package is generated, the CFD analysis can proceed. The model supplants the hardware prototypes of the past, yet supports the same level of rigor in the testing process. And crucially, it is easy to modify, test again, modify again, and so on.

To run the thermal analysis the engineer must define a JEDEC standard environment for the CFD-based thermal simulation tool, and then insert the package model into that domain. The simulation results provide a complete understanding of the thermal performance of the design. They include not only the temperature difference between ambient and the junction, but also the temperature of every point within the "system."

The simulation quickly points out any regions that exhibit high thermal resistance. These are obvious areas for improvement in thermal performance. Heat spreaders, slugs, and increased copper plane thickness are among the solutions that can remove heat from the silicon and reduce temperatures.

Figure 1. Thermal simulation of a plastic BGA device using 1oz copper planes in the package substrate to dissipate heat. With temperatures approaching the maximum in some areas, the device is not suitable for its intended application.

Figure 1 depicts the results from a simulation on a mixed-signal device housed in a plastic ball grid array (BGA), while Figure 2 provides a close-up view of the immediate die area. As the scale reveals, the temperature in that critical area is in the 124°C range — too hot for the health of the chip. The virtual device used in the simulation incorporates conventional 1oz copper planes to manage the heat transfer and these are not doing an adequate job.

Figure 2. Close-up view of the BGA showing the 124°C heat buildup in the center of the die area.

Thus, the simulation has provided insights that can help the designer improve the performance of the product. A more robust heat transfer medium is needed, and the modeling toolset offers slugs and other heat spreaders. It is important to note that this whole process can occur very early in the development cycle since software constructs are much easier to "prototype" than are hardware packages. Designers can evaluate many different designs and optimize the thermal performance in the time it would take to test just one or two variants with hardware-based analysis.

Pursuing this line of thinking, one might add a slug to the device and boost the thickness of the copper planes to 2 oz. Indeed, this does improve the heat situation, as shown in the simulation in Figure 3a. The scale reveals that the maximum temperature is now 115°C, well within the planned limits. However, both measures add cost to the device. Will just one of the two treatments suffice?

Figure 3. a) A simulation of the BGA with 2 oz. copper planes and a heat slug added. The temperatures are now well under maximum levels, though at added cost; b) results after removing the slug. The temperatures have been held to an acceptable level (119°C) while maintaining costs close to those of the more basic package scheme described in Fig. 1.

The simulation in Fig. 3b proves that it will. The slug can be eliminated at the cost of just a few more degrees of heat buildup. The final peak temperature, 119°C, is still safely within limits. Both of these simulations can be completed in hours instead of the days required for hardware-based testing. All of the simulations shown in this example were developed with the Mentor Graphics FloTHERM analysis package using models generated on the FloTHERM PACK web-based toolset.

Conclusion

Until now, hardware tests have been the standard operating procedure for conducting thermal analysis. But these procedures are time-consuming and today’s market pressures demand results much faster than ever before.

Package designers are increasingly turning to software-based device modeling and CFD analysis solutions. These tools bypass hardware prototypes and allow timely evaluation of new concepts, eliminating time-consuming fabrication of trial components, thermal dice, and other fixturing. Now, it is possible to preview the impact of design decisions and changes without risking project success.

Acknowledgment

FloTHERM is a registered trademark of Mentor Graphics Corp.

Biography

Robin Bornoff received a mechanical engineering degree from Brunel U. (UK) in 1992 followed by a PhD in 1995 for CFD research. He is FloTHERM and FloVENT product marketing manager at Mentor Graphics Corp., Mechanical Analysis Division, 81 Bridge Road Hampton Court Surrey KT8 9HH, UK; ph.: +44 (0)20 8487 3084; e-mail [email protected].